Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-asm_system
Pull "Disintegrate and delete asm/system.h" from David Howells:
"Here are a bunch of patches to disintegrate asm/system.h into a set of
separate bits to relieve the problem of circular inclusion
dependencies.
I've built all the working defconfigs from all the arches that I can
and made sure that they don't break.
The reason for these patches is that I recently encountered a circular
dependency problem that came about when I produced some patches to
optimise get_order() by rewriting it to use ilog2().
This uses bitops - and on the SH arch asm/bitops.h drags in
asm-generic/get_order.h by a circuituous route involving asm/system.h.
The main difficulty seems to be asm/system.h. It holds a number of
low level bits with no/few dependencies that are commonly used (eg.
memory barriers) and a number of bits with more dependencies that
aren't used in many places (eg. switch_to()).
These patches break asm/system.h up into the following core pieces:
(1) asm/barrier.h
Move memory barriers here. This already done for MIPS and Alpha.
(2) asm/switch_to.h
Move switch_to() and related stuff here.
(3) asm/exec.h
Move arch_align_stack() here. Other process execution related bits
could perhaps go here from asm/processor.h.
(4) asm/cmpxchg.h
Move xchg() and cmpxchg() here as they're full word atomic ops and
frequently used by atomic_xchg() and atomic_cmpxchg().
(5) asm/bug.h
Move die() and related bits.
(6) asm/auxvec.h
Move AT_VECTOR_SIZE_ARCH here.
Other arch headers are created as needed on a per-arch basis."
Fixed up some conflicts from other header file cleanups and moving code
around that has happened in the meantime, so David's testing is somewhat
weakened by that. We'll find out anything that got broken and fix it..
* tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-asm_system: (38 commits)
Delete all instances of asm/system.h
Remove all #inclusions of asm/system.h
Add #includes needed to permit the removal of asm/system.h
Move all declarations of free_initmem() to linux/mm.h
Disintegrate asm/system.h for OpenRISC
Split arch_align_stack() out from asm-generic/system.h
Split the switch_to() wrapper out of asm-generic/system.h
Move the asm-generic/system.h xchg() implementation to asm-generic/cmpxchg.h
Create asm-generic/barrier.h
Make asm-generic/cmpxchg.h #include asm-generic/cmpxchg-local.h
Disintegrate asm/system.h for Xtensa
Disintegrate asm/system.h for Unicore32 [based on ver #3, changed by gxt]
Disintegrate asm/system.h for Tile
Disintegrate asm/system.h for Sparc
Disintegrate asm/system.h for SH
Disintegrate asm/system.h for Score
Disintegrate asm/system.h for S390
Disintegrate asm/system.h for PowerPC
Disintegrate asm/system.h for PA-RISC
Disintegrate asm/system.h for MN10300
...
This commit is contained in:
Linus Torvalds
@@ -6,7 +6,6 @@
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#define _ASM_PARISC_ATOMIC_H_
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#include <linux/types.h>
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#include <asm/system.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
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35
arch/parisc/include/asm/barrier.h
Normal file
35
arch/parisc/include/asm/barrier.h
Normal file
@@ -0,0 +1,35 @@
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#ifndef __PARISC_BARRIER_H
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#define __PARISC_BARRIER_H
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/*
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** This is simply the barrier() macro from linux/kernel.h but when serial.c
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** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
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** hasn't yet been included yet so it fails, thus repeating the macro here.
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**
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** PA-RISC architecture allows for weakly ordered memory accesses although
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** none of the processors use it. There is a strong ordered bit that is
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** set in the O-bit of the page directory entry. Operating systems that
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** can not tolerate out of order accesses should set this bit when mapping
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** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
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** of the processor implemented the PSW O-bit). The PCX-W ERS states that
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** the TLB O-bit is not implemented so the page directory does not need to
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** have the O-bit set when mapping pages (section 3.1). This section also
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** states that the PSW Y, Z, G, and O bits are not implemented.
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** So it looks like nothing needs to be done for parisc-linux (yet).
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** (thanks to chada for the above comment -ggg)
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**
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** The __asm__ op below simple prevents gcc/ld from reordering
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** instructions across the mb() "call".
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*/
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#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
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#define rmb() mb()
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#define wmb() mb()
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#define smp_mb() mb()
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#define smp_rmb() mb()
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#define smp_wmb() mb()
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#define smp_read_barrier_depends() do { } while(0)
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#endif /* __PARISC_BARRIER_H */
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@@ -1,7 +1,7 @@
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#ifndef _PARISC_DELAY_H
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#define _PARISC_DELAY_H
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#include <asm/system.h> /* for mfctl() */
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#include <asm/special_insns.h> /* for mfctl() */
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#include <asm/processor.h> /* for boot_cpu_data */
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@@ -9,7 +9,6 @@
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#define _ASM_DMA_H
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#include <asm/io.h> /* need byte IO */
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#include <asm/system.h>
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#define dma_outb outb
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#define dma_inb inb
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6
arch/parisc/include/asm/exec.h
Normal file
6
arch/parisc/include/asm/exec.h
Normal file
@@ -0,0 +1,6 @@
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#ifndef __PARISC_EXEC_H
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#define __PARISC_EXEC_H
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#define arch_align_stack(x) (x)
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#endif /* __PARISC_EXEC_H */
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48
arch/parisc/include/asm/ldcw.h
Normal file
48
arch/parisc/include/asm/ldcw.h
Normal file
@@ -0,0 +1,48 @@
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#ifndef __PARISC_LDCW_H
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#define __PARISC_LDCW_H
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#ifndef CONFIG_PA20
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/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
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and GCC only guarantees 8-byte alignment for stack locals, we can't
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be assured of 16-byte alignment for atomic lock data even if we
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specify "__attribute ((aligned(16)))" in the type declaration. So,
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we use a struct containing an array of four ints for the atomic lock
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type and dynamically select the 16-byte aligned int from the array
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for the semaphore. */
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#define __PA_LDCW_ALIGNMENT 16
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#define __ldcw_align(a) ({ \
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unsigned long __ret = (unsigned long) &(a)->lock[0]; \
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__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
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& ~(__PA_LDCW_ALIGNMENT - 1); \
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(volatile unsigned int *) __ret; \
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})
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#define __LDCW "ldcw"
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#else /*CONFIG_PA20*/
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/* From: "Jim Hull" <jim.hull of hp.com>
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I've attached a summary of the change, but basically, for PA 2.0, as
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long as the ",CO" (coherent operation) completer is specified, then the
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16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
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they only require "natural" alignment (4-byte for ldcw, 8-byte for
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ldcd). */
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#define __PA_LDCW_ALIGNMENT 4
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#define __ldcw_align(a) (&(a)->slock)
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#define __LDCW "ldcw,co"
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#endif /*!CONFIG_PA20*/
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/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
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#define __ldcw(a) ({ \
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unsigned __ret; \
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__asm__ __volatile__(__LDCW " 0(%2),%0" \
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: "=r" (__ret), "+m" (*(a)) : "r" (a)); \
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__ret; \
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})
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#ifdef CONFIG_SMP
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# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
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#endif
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#endif /* __PARISC_LDCW_H */
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@@ -16,7 +16,6 @@
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#include <asm/pdc.h>
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#include <asm/ptrace.h>
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#include <asm/types.h>
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#include <asm/system.h>
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#include <asm/percpu.h>
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#endif /* __ASSEMBLY__ */
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@@ -169,6 +168,7 @@ struct thread_struct {
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* Return saved PC of a blocked thread. This is used by ps mostly.
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*/
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struct task_struct;
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unsigned long thread_saved_pc(struct task_struct *t);
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void show_trace(struct task_struct *task, unsigned long *stack);
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@@ -59,4 +59,45 @@
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#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
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#define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
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#ifndef __ASSEMBLY__
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/* The program status word as bitfields. */
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struct pa_psw {
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unsigned int y:1;
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unsigned int z:1;
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unsigned int rv:2;
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unsigned int w:1;
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unsigned int e:1;
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unsigned int s:1;
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unsigned int t:1;
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unsigned int h:1;
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unsigned int l:1;
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unsigned int n:1;
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unsigned int x:1;
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unsigned int b:1;
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unsigned int c:1;
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unsigned int v:1;
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unsigned int m:1;
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unsigned int cb:8;
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unsigned int o:1;
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unsigned int g:1;
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unsigned int f:1;
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unsigned int r:1;
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unsigned int q:1;
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unsigned int p:1;
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unsigned int d:1;
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unsigned int i:1;
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};
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#ifdef CONFIG_64BIT
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#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
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#else
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#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif
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40
arch/parisc/include/asm/special_insns.h
Normal file
40
arch/parisc/include/asm/special_insns.h
Normal file
@@ -0,0 +1,40 @@
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#ifndef __PARISC_SPECIAL_INSNS_H
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#define __PARISC_SPECIAL_INSNS_H
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#define mfctl(reg) ({ \
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unsigned long cr; \
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__asm__ __volatile__( \
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"mfctl " #reg ",%0" : \
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"=r" (cr) \
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); \
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cr; \
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})
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#define mtctl(gr, cr) \
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__asm__ __volatile__("mtctl %0,%1" \
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: /* no outputs */ \
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: "r" (gr), "i" (cr) : "memory")
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/* these are here to de-mystefy the calling code, and to provide hooks */
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/* which I needed for debugging EIEM problems -PB */
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#define get_eiem() mfctl(15)
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static inline void set_eiem(unsigned long val)
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{
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mtctl(val, 15);
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}
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#define mfsp(reg) ({ \
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unsigned long cr; \
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__asm__ __volatile__( \
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"mfsp " #reg ",%0" : \
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"=r" (cr) \
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); \
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cr; \
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})
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#define mtsp(gr, cr) \
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__asm__ __volatile__("mtsp %0,%1" \
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: /* no outputs */ \
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: "r" (gr), "i" (cr) : "memory")
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#endif /* __PARISC_SPECIAL_INSNS_H */
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@@ -1,7 +1,6 @@
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/spinlock_types.h>
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12
arch/parisc/include/asm/switch_to.h
Normal file
12
arch/parisc/include/asm/switch_to.h
Normal file
@@ -0,0 +1,12 @@
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#ifndef __PARISC_SWITCH_TO_H
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#define __PARISC_SWITCH_TO_H
|
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struct task_struct;
|
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extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
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#define switch_to(prev, next, last) do { \
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(last) = _switch_to(prev, next); \
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} while(0)
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|
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#endif /* __PARISC_SWITCH_TO_H */
|
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@@ -1,165 +0,0 @@
|
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#ifndef __PARISC_SYSTEM_H
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#define __PARISC_SYSTEM_H
|
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#include <linux/irqflags.h>
|
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|
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/* The program status word as bitfields. */
|
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struct pa_psw {
|
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unsigned int y:1;
|
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unsigned int z:1;
|
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unsigned int rv:2;
|
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unsigned int w:1;
|
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unsigned int e:1;
|
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unsigned int s:1;
|
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unsigned int t:1;
|
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|
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unsigned int h:1;
|
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unsigned int l:1;
|
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unsigned int n:1;
|
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unsigned int x:1;
|
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unsigned int b:1;
|
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unsigned int c:1;
|
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unsigned int v:1;
|
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unsigned int m:1;
|
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|
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unsigned int cb:8;
|
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|
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unsigned int o:1;
|
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unsigned int g:1;
|
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unsigned int f:1;
|
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unsigned int r:1;
|
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unsigned int q:1;
|
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unsigned int p:1;
|
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unsigned int d:1;
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unsigned int i:1;
|
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};
|
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|
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#ifdef CONFIG_64BIT
|
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#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW + 4))
|
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#else
|
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#define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
|
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#endif
|
||||
|
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struct task_struct;
|
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|
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extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
|
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|
||||
#define switch_to(prev, next, last) do { \
|
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(last) = _switch_to(prev, next); \
|
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} while(0)
|
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|
||||
#define mfctl(reg) ({ \
|
||||
unsigned long cr; \
|
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__asm__ __volatile__( \
|
||||
"mfctl " #reg ",%0" : \
|
||||
"=r" (cr) \
|
||||
); \
|
||||
cr; \
|
||||
})
|
||||
|
||||
#define mtctl(gr, cr) \
|
||||
__asm__ __volatile__("mtctl %0,%1" \
|
||||
: /* no outputs */ \
|
||||
: "r" (gr), "i" (cr) : "memory")
|
||||
|
||||
/* these are here to de-mystefy the calling code, and to provide hooks */
|
||||
/* which I needed for debugging EIEM problems -PB */
|
||||
#define get_eiem() mfctl(15)
|
||||
static inline void set_eiem(unsigned long val)
|
||||
{
|
||||
mtctl(val, 15);
|
||||
}
|
||||
|
||||
#define mfsp(reg) ({ \
|
||||
unsigned long cr; \
|
||||
__asm__ __volatile__( \
|
||||
"mfsp " #reg ",%0" : \
|
||||
"=r" (cr) \
|
||||
); \
|
||||
cr; \
|
||||
})
|
||||
|
||||
#define mtsp(gr, cr) \
|
||||
__asm__ __volatile__("mtsp %0,%1" \
|
||||
: /* no outputs */ \
|
||||
: "r" (gr), "i" (cr) : "memory")
|
||||
|
||||
|
||||
/*
|
||||
** This is simply the barrier() macro from linux/kernel.h but when serial.c
|
||||
** uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
|
||||
** hasn't yet been included yet so it fails, thus repeating the macro here.
|
||||
**
|
||||
** PA-RISC architecture allows for weakly ordered memory accesses although
|
||||
** none of the processors use it. There is a strong ordered bit that is
|
||||
** set in the O-bit of the page directory entry. Operating systems that
|
||||
** can not tolerate out of order accesses should set this bit when mapping
|
||||
** pages. The O-bit of the PSW should also be set to 1 (I don't believe any
|
||||
** of the processor implemented the PSW O-bit). The PCX-W ERS states that
|
||||
** the TLB O-bit is not implemented so the page directory does not need to
|
||||
** have the O-bit set when mapping pages (section 3.1). This section also
|
||||
** states that the PSW Y, Z, G, and O bits are not implemented.
|
||||
** So it looks like nothing needs to be done for parisc-linux (yet).
|
||||
** (thanks to chada for the above comment -ggg)
|
||||
**
|
||||
** The __asm__ op below simple prevents gcc/ld from reordering
|
||||
** instructions across the mb() "call".
|
||||
*/
|
||||
#define mb() __asm__ __volatile__("":::"memory") /* barrier() */
|
||||
#define rmb() mb()
|
||||
#define wmb() mb()
|
||||
#define smp_mb() mb()
|
||||
#define smp_rmb() mb()
|
||||
#define smp_wmb() mb()
|
||||
#define smp_read_barrier_depends() do { } while(0)
|
||||
#define read_barrier_depends() do { } while(0)
|
||||
|
||||
#define set_mb(var, value) do { var = value; mb(); } while (0)
|
||||
|
||||
#ifndef CONFIG_PA20
|
||||
/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
|
||||
and GCC only guarantees 8-byte alignment for stack locals, we can't
|
||||
be assured of 16-byte alignment for atomic lock data even if we
|
||||
specify "__attribute ((aligned(16)))" in the type declaration. So,
|
||||
we use a struct containing an array of four ints for the atomic lock
|
||||
type and dynamically select the 16-byte aligned int from the array
|
||||
for the semaphore. */
|
||||
|
||||
#define __PA_LDCW_ALIGNMENT 16
|
||||
#define __ldcw_align(a) ({ \
|
||||
unsigned long __ret = (unsigned long) &(a)->lock[0]; \
|
||||
__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
|
||||
& ~(__PA_LDCW_ALIGNMENT - 1); \
|
||||
(volatile unsigned int *) __ret; \
|
||||
})
|
||||
#define __LDCW "ldcw"
|
||||
|
||||
#else /*CONFIG_PA20*/
|
||||
/* From: "Jim Hull" <jim.hull of hp.com>
|
||||
I've attached a summary of the change, but basically, for PA 2.0, as
|
||||
long as the ",CO" (coherent operation) completer is specified, then the
|
||||
16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
|
||||
they only require "natural" alignment (4-byte for ldcw, 8-byte for
|
||||
ldcd). */
|
||||
|
||||
#define __PA_LDCW_ALIGNMENT 4
|
||||
#define __ldcw_align(a) (&(a)->slock)
|
||||
#define __LDCW "ldcw,co"
|
||||
|
||||
#endif /*!CONFIG_PA20*/
|
||||
|
||||
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
|
||||
#define __ldcw(a) ({ \
|
||||
unsigned __ret; \
|
||||
__asm__ __volatile__(__LDCW " 0(%2),%0" \
|
||||
: "=r" (__ret), "+m" (*(a)) : "r" (a)); \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
# define __lock_aligned __attribute__((__section__(".data..lock_aligned")))
|
||||
#endif
|
||||
|
||||
#define arch_align_stack(x) (x)
|
||||
|
||||
#endif
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/processor.h>
|
||||
#include <asm/special_insns.h>
|
||||
|
||||
struct thread_info {
|
||||
struct task_struct *task; /* main task structure */
|
||||
|
||||
@@ -6,7 +6,6 @@
|
||||
#ifndef _ASMPARISC_TIMEX_H
|
||||
#define _ASMPARISC_TIMEX_H
|
||||
|
||||
#include <asm/system.h>
|
||||
|
||||
#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
|
||||
|
||||
|
||||
@@ -5,7 +5,6 @@
|
||||
* User space memory access functions
|
||||
*/
|
||||
#include <asm/page.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm-generic/uaccess-unaligned.h>
|
||||
|
||||
Reference in New Issue
Block a user