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Merge branch 'linus' into x86/pebs

Browse Source 
Conflicts:

	arch/x86/Kconfig.cpu
	arch/x86/kernel/cpu/intel.c
	arch/x86/kernel/setup_64.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
2008-07-25 11:37:07 +02:00
parent da7878d75b fb2e405fc1
commit 0e2f65ee30
7360 changed files with 544762 additions and 464797 deletions
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1
include/Kbuild
View File

@@ -4,5 +4,6 @@ header-y += sound/
header-y += mtd/
header-y += rdma/
header-y += video/
header-y += drm/
header-y += asm-$(ARCH)/

2
include/acpi/acconfig.h
View File

@@ -63,7 +63,7 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20080321
#define ACPI_CA_VERSION 0x20080609
/*
* OS name, used for the _OS object. The _OS object is essentially obsolete,

1
include/acpi/acdisasm.h
View File

@@ -162,6 +162,7 @@ extern struct acpi_dmtable_info acpi_dm_table_info_dmar_hdr[];
extern struct acpi_dmtable_info acpi_dm_table_info_dmar_scope[];
extern struct acpi_dmtable_info acpi_dm_table_info_dmar0[];
extern struct acpi_dmtable_info acpi_dm_table_info_dmar1[];
extern struct acpi_dmtable_info acpi_dm_table_info_dmar2[];
extern struct acpi_dmtable_info acpi_dm_table_info_ecdt[];
extern struct acpi_dmtable_info acpi_dm_table_info_einj[];
extern struct acpi_dmtable_info acpi_dm_table_info_einj0[];

2
include/acpi/acdispat.h
View File

@@ -221,7 +221,7 @@ acpi_ds_method_error(acpi_status status, struct acpi_walk_state *walk_state);
* dsinit
*/
acpi_status
acpi_ds_initialize_objects(acpi_native_uint table_index,
acpi_ds_initialize_objects(u32 table_index,
struct acpi_namespace_node *start_node);
/*

10
include/acpi/acexcep.h
View File

@@ -108,8 +108,9 @@
#define AE_BAD_HEX_CONSTANT (acpi_status) (0x0007 | AE_CODE_PROGRAMMER)
#define AE_BAD_OCTAL_CONSTANT (acpi_status) (0x0008 | AE_CODE_PROGRAMMER)
#define AE_BAD_DECIMAL_CONSTANT (acpi_status) (0x0009 | AE_CODE_PROGRAMMER)
#define AE_MISSING_ARGUMENTS (acpi_status) (0x000A | AE_CODE_PROGRAMMER)
#define AE_CODE_PGM_MAX 0x0009
#define AE_CODE_PGM_MAX 0x000A
/*
* Acpi table exceptions
@@ -225,6 +226,7 @@ char const *acpi_gbl_exception_names_env[] = {
};
char const *acpi_gbl_exception_names_pgm[] = {
NULL,
"AE_BAD_PARAMETER",
"AE_BAD_CHARACTER",
"AE_BAD_PATHNAME",
@@ -233,10 +235,12 @@ char const *acpi_gbl_exception_names_pgm[] = {
"AE_ALIGNMENT",
"AE_BAD_HEX_CONSTANT",
"AE_BAD_OCTAL_CONSTANT",
"AE_BAD_DECIMAL_CONSTANT"
"AE_BAD_DECIMAL_CONSTANT",
"AE_MISSING_ARGUMENTS"
};
char const *acpi_gbl_exception_names_tbl[] = {
NULL,
"AE_BAD_SIGNATURE",
"AE_BAD_HEADER",
"AE_BAD_CHECKSUM",
@@ -246,6 +250,7 @@ char const *acpi_gbl_exception_names_tbl[] = {
};
char const *acpi_gbl_exception_names_aml[] = {
NULL,
"AE_AML_ERROR",
"AE_AML_PARSE",
"AE_AML_BAD_OPCODE",
@@ -283,6 +288,7 @@ char const *acpi_gbl_exception_names_aml[] = {
};
char const *acpi_gbl_exception_names_ctrl[] = {
NULL,
"AE_CTRL_RETURN_VALUE",
"AE_CTRL_PENDING",
"AE_CTRL_TERMINATE",

2
include/acpi/acglobal.h
View File

@@ -140,7 +140,7 @@ ACPI_EXTERN u32 acpi_gbl_trace_flags;
*/
ACPI_EXTERN struct acpi_internal_rsdt acpi_gbl_root_table_list;
ACPI_EXTERN struct acpi_table_fadt acpi_gbl_FADT;
extern acpi_native_uint acpi_gbl_permanent_mmap;
extern u8 acpi_gbl_permanent_mmap;
/* These addresses are calculated from FADT address values */

4
include/acpi/achware.h
View File

@@ -87,6 +87,8 @@ acpi_status acpi_hw_clear_acpi_status(void);
/*
* hwgpe - GPE support
*/
acpi_status acpi_hw_low_disable_gpe(struct acpi_gpe_event_info *gpe_event_info);
acpi_status
acpi_hw_write_gpe_enable_reg(struct acpi_gpe_event_info *gpe_event_info);
@@ -100,11 +102,9 @@ acpi_status
acpi_hw_clear_gpe_block(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
struct acpi_gpe_block_info *gpe_block);
#ifdef ACPI_FUTURE_USAGE
acpi_status
acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
acpi_event_status * event_status);
#endif /* ACPI_FUTURE_USAGE */
acpi_status acpi_hw_disable_all_gpes(void);

5
include/acpi/acinterp.h
View File

@@ -366,10 +366,7 @@ void acpi_ex_dump_operand(union acpi_operand_object *obj_desc, u32 depth);
void
acpi_ex_dump_operands(union acpi_operand_object **operands,
acpi_interpreter_mode interpreter_mode,
char *ident,
u32 num_levels,
char *note, char *module_name, u32 line_number);
const char *opcode_name, u32 num_opcodes);
#ifdef ACPI_FUTURE_USAGE
void

6
include/acpi/aclocal.h
View File

@@ -98,8 +98,8 @@ union acpi_parse_object;
static char *acpi_gbl_mutex_names[ACPI_NUM_MUTEX] = {
"ACPI_MTX_Interpreter",
"ACPI_MTX_Tables",
"ACPI_MTX_Namespace",
"ACPI_MTX_Tables",
"ACPI_MTX_Events",
"ACPI_MTX_Caches",
"ACPI_MTX_Memory",
@@ -282,8 +282,8 @@ struct acpi_predefined_names {
/* Info structure used to convert external<->internal namestrings */
struct acpi_namestring_info {
char *external_name;
char *next_external_char;
const char *external_name;
const char *next_external_char;
char *internal_name;
u32 length;
u32 num_segments;

38
include/acpi/acmacros.h
View File

@@ -80,12 +80,12 @@
*/
#define ACPI_CAST_PTR(t, p) ((t *) (acpi_uintptr_t) (p))
#define ACPI_CAST_INDIRECT_PTR(t, p) ((t **) (acpi_uintptr_t) (p))
#define ACPI_ADD_PTR(t,a,b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_native_uint)(b)))
#define ACPI_PTR_DIFF(a,b) (acpi_native_uint) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b)))
#define ACPI_ADD_PTR(t, a, b) ACPI_CAST_PTR (t, (ACPI_CAST_PTR (u8,(a)) + (acpi_size)(b)))
#define ACPI_PTR_DIFF(a, b) (acpi_size) (ACPI_CAST_PTR (u8,(a)) - ACPI_CAST_PTR (u8,(b)))
/* Pointer/Integer type conversions */
#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void,(void *) NULL,(acpi_native_uint) i)
#define ACPI_TO_POINTER(i) ACPI_ADD_PTR (void, (void *) NULL, (acpi_size) i)
#define ACPI_TO_INTEGER(p) ACPI_PTR_DIFF (p,(void *) NULL)
#define ACPI_OFFSET(d,f) (acpi_size) ACPI_PTR_DIFF (&(((d *)0)->f),(void *) NULL)
#define ACPI_PHYSADDR_TO_PTR(i) ACPI_TO_POINTER(i)
@@ -296,22 +296,22 @@ struct acpi_integer_overlay {
/*
* Rounding macros (Power of two boundaries only)
*/
#define ACPI_ROUND_DOWN(value,boundary) (((acpi_native_uint)(value)) & \
(~(((acpi_native_uint) boundary)-1)))
#define ACPI_ROUND_DOWN(value, boundary) (((acpi_size)(value)) & \
(~(((acpi_size) boundary)-1)))
#define ACPI_ROUND_UP(value,boundary) ((((acpi_native_uint)(value)) + \
(((acpi_native_uint) boundary)-1)) & \
(~(((acpi_native_uint) boundary)-1)))
#define ACPI_ROUND_UP(value, boundary) ((((acpi_size)(value)) + \
(((acpi_size) boundary)-1)) & \
(~(((acpi_size) boundary)-1)))
/* Note: sizeof(acpi_native_uint) evaluates to either 2, 4, or 8 */
/* Note: sizeof(acpi_size) evaluates to either 4 or 8 (32- vs 64-bit mode) */
#define ACPI_ROUND_DOWN_TO_32BIT(a) ACPI_ROUND_DOWN(a,4)
#define ACPI_ROUND_DOWN_TO_64BIT(a) ACPI_ROUND_DOWN(a,8)
#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a) ACPI_ROUND_DOWN(a,sizeof(acpi_native_uint))
#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a) ACPI_ROUND_DOWN(a,sizeof(acpi_size))
#define ACPI_ROUND_UP_TO_32BIT(a) ACPI_ROUND_UP(a,4)
#define ACPI_ROUND_UP_TO_64BIT(a) ACPI_ROUND_UP(a,8)
#define ACPI_ROUND_UP_TO_NATIVE_WORD(a) ACPI_ROUND_UP(a,sizeof(acpi_native_uint))
#define ACPI_ROUND_UP_TO_NATIVE_WORD(a) ACPI_ROUND_UP(a,sizeof(acpi_size))
#define ACPI_ROUND_BITS_UP_TO_BYTES(a) ACPI_DIV_8((a) + 7)
#define ACPI_ROUND_BITS_DOWN_TO_BYTES(a) ACPI_DIV_8((a))
@@ -322,7 +322,7 @@ struct acpi_integer_overlay {
#define ACPI_ROUND_UP_TO(value,boundary) (((value) + ((boundary)-1)) / (boundary))
#define ACPI_IS_MISALIGNED(value) (((acpi_native_uint)value) & (sizeof(acpi_native_uint)-1))
#define ACPI_IS_MISALIGNED(value) (((acpi_size)value) & (sizeof(acpi_size)-1))
/*
* Bitmask creation
@@ -414,7 +414,7 @@ struct acpi_integer_overlay {
* error messages. The __FILE__ macro is not very useful for this, because it
* often includes the entire pathname to the module
*/
#define ACPI_MODULE_NAME(name) static char ACPI_UNUSED_VAR *_acpi_module_name = name;
#define ACPI_MODULE_NAME(name) static const char ACPI_UNUSED_VAR _acpi_module_name[] = name;
#else
#define ACPI_MODULE_NAME(name)
#endif
@@ -467,19 +467,17 @@ struct acpi_integer_overlay {
/*
* If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header,
* define it now. This is the case where there the compiler does not support
* a __FUNCTION__ macro or equivalent. We save the function name on the
* local stack.
* a __FUNCTION__ macro or equivalent.
*/
#ifndef ACPI_GET_FUNCTION_NAME
#define ACPI_GET_FUNCTION_NAME _acpi_function_name
/*
* The Name parameter should be the procedure name as a quoted string.
* This is declared as a local string ("MyFunctionName") so that it can
* be also used by the function exit macros below.
* The function name is also used by the function exit macros below.
* Note: (const char) is used to be compatible with the debug interfaces
* and macros such as __FUNCTION__.
*/
#define ACPI_FUNCTION_NAME(name) const char *_acpi_function_name = #name;
#define ACPI_FUNCTION_NAME(name) static const char _acpi_function_name[] = #name;
#else
/* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */
@@ -599,7 +597,7 @@ struct acpi_integer_overlay {
/* Stack and buffer dumping */
#define ACPI_DUMP_STACK_ENTRY(a) acpi_ex_dump_operand((a),0)
#define ACPI_DUMP_OPERANDS(a,b,c,d,e) acpi_ex_dump_operands(a,b,c,d,e,_acpi_module_name,__LINE__)
#define ACPI_DUMP_OPERANDS(a,b,c) acpi_ex_dump_operands(a,b,c)
#define ACPI_DUMP_ENTRY(a,b) acpi_ns_dump_entry (a,b)
#define ACPI_DUMP_PATHNAME(a,b,c,d) acpi_ns_dump_pathname(a,b,c,d)
@@ -635,7 +633,7 @@ struct acpi_integer_overlay {
#define ACPI_FUNCTION_VALUE_EXIT(s) do { } while(0)
#define ACPI_FUNCTION_ENTRY() do { } while(0)
#define ACPI_DUMP_STACK_ENTRY(a) do { } while(0)
#define ACPI_DUMP_OPERANDS(a,b,c,d,e) do { } while(0)
#define ACPI_DUMP_OPERANDS(a,b,c) do { } while(0)
#define ACPI_DUMP_ENTRY(a,b) do { } while(0)
#define ACPI_DUMP_TABLES(a,b) do { } while(0)
#define ACPI_DUMP_PATHNAME(a,b,c,d) do { } while(0)

30
include/acpi/acnamesp.h
View File

@@ -86,8 +86,7 @@ acpi_status acpi_ns_initialize_devices(void);
acpi_status acpi_ns_load_namespace(void);
acpi_status
acpi_ns_load_table(acpi_native_uint table_index,
struct acpi_namespace_node *node);
acpi_ns_load_table(u32 table_index, struct acpi_namespace_node *node);
/*
* nswalk - walk the namespace
@@ -108,12 +107,11 @@ struct acpi_namespace_node *acpi_ns_get_next_node(acpi_object_type type, struct
* nsparse - table parsing
*/
acpi_status
acpi_ns_parse_table(acpi_native_uint table_index,
struct acpi_namespace_node *start_node);
acpi_ns_parse_table(u32 table_index, struct acpi_namespace_node *start_node);
acpi_status
acpi_ns_one_complete_parse(acpi_native_uint pass_number,
acpi_native_uint table_index,
acpi_ns_one_complete_parse(u32 pass_number,
u32 table_index,
struct acpi_namespace_node *start_node);
/*
@@ -201,7 +199,7 @@ acpi_ns_pattern_match(struct acpi_namespace_node *obj_node, char *search_for);
acpi_status
acpi_ns_get_node(struct acpi_namespace_node *prefix_node,
char *external_pathname,
const char *external_pathname,
u32 flags, struct acpi_namespace_node **out_node);
acpi_size acpi_ns_get_pathname_length(struct acpi_namespace_node *node);
@@ -265,28 +263,30 @@ acpi_object_type acpi_ns_get_type(struct acpi_namespace_node *node);
u32 acpi_ns_local(acpi_object_type type);
void
acpi_ns_report_error(char *module_name,
acpi_ns_report_error(const char *module_name,
u32 line_number,
char *internal_name, acpi_status lookup_status);
const char *internal_name, acpi_status lookup_status);
void
acpi_ns_report_method_error(char *module_name,
acpi_ns_report_method_error(const char *module_name,
u32 line_number,
char *message,
const char *message,
struct acpi_namespace_node *node,
char *path, acpi_status lookup_status);
const char *path, acpi_status lookup_status);
void acpi_ns_print_node_pathname(struct acpi_namespace_node *node, char *msg);
void
acpi_ns_print_node_pathname(struct acpi_namespace_node *node, const char *msg);
acpi_status acpi_ns_build_internal_name(struct acpi_namestring_info *info);
void acpi_ns_get_internal_name_length(struct acpi_namestring_info *info);
acpi_status acpi_ns_internalize_name(char *dotted_name, char **converted_name);
acpi_status
acpi_ns_internalize_name(const char *dotted_name, char **converted_name);
acpi_status
acpi_ns_externalize_name(u32 internal_name_length,
char *internal_name,
const char *internal_name,
u32 * converted_name_length, char **converted_name);
struct acpi_namespace_node *acpi_ns_map_handle_to_node(acpi_handle handle);

12
include/acpi/acpi_bus.h
View File

@@ -259,6 +259,7 @@ struct acpi_device_perf {
/* Wakeup Management */
struct acpi_device_wakeup_flags {
u8 valid:1; /* Can successfully enable wakeup? */
u8 prepared:1; /* Has the wake-up capability been enabled? */
u8 run_wake:1; /* Run-Wake GPE devices */
};
@@ -335,6 +336,8 @@ void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context);
int acpi_bus_get_status(struct acpi_device *device);
int acpi_bus_get_power(acpi_handle handle, int *state);
int acpi_bus_set_power(acpi_handle handle, int state);
bool acpi_bus_power_manageable(acpi_handle handle);
bool acpi_bus_can_wakeup(acpi_handle handle);
#ifdef CONFIG_ACPI_PROC_EVENT
int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data);
int acpi_bus_generate_proc_event4(const char *class, const char *bid, u8 type, int data);
@@ -376,14 +379,19 @@ acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int);
#define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->archdata.acpi_handle))
#ifdef CONFIG_PM_SLEEP
int acpi_pm_device_sleep_state(struct device *, int, int *);
int acpi_pm_device_sleep_state(struct device *, int *);
int acpi_pm_device_sleep_wake(struct device *, bool);
#else /* !CONFIG_PM_SLEEP */
static inline int acpi_pm_device_sleep_state(struct device *d, int w, int *p)
static inline int acpi_pm_device_sleep_state(struct device *d, int *p)
{
if (p)
*p = ACPI_STATE_D0;
return ACPI_STATE_D3;
}
static inline int acpi_pm_device_sleep_wake(struct device *dev, bool enable)
{
return -ENODEV;
}
#endif /* !CONFIG_PM_SLEEP */
#endif /* CONFIG_ACPI */

4
include/acpi/acpi_drivers.h
View File

@@ -87,7 +87,9 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_device *device, int domain,
-------------------------------------------------------------------------- */
#ifdef CONFIG_ACPI_POWER
int acpi_enable_wakeup_device_power(struct acpi_device *dev);
int acpi_device_sleep_wake(struct acpi_device *dev,
int enable, int sleep_state, int dev_state);
int acpi_enable_wakeup_device_power(struct acpi_device *dev, int sleep_state);
int acpi_disable_wakeup_device_power(struct acpi_device *dev);
int acpi_power_get_inferred_state(struct acpi_device *device);
int acpi_power_transition(struct acpi_device *device, int state);

2
include/acpi/acpiosxf.h
View File

@@ -144,7 +144,7 @@ void acpi_os_release_mutex(acpi_mutex handle);
void *acpi_os_allocate(acpi_size size);
void __iomem *acpi_os_map_memory(acpi_physical_address where,
acpi_native_uint length);
acpi_size length);
void acpi_os_unmap_memory(void __iomem * logical_address, acpi_size size);

12
include/acpi/acpixf.h
View File

@@ -98,7 +98,7 @@ void acpi_free(void *address);
*/
acpi_status acpi_reallocate_root_table(void);
acpi_status acpi_find_root_pointer(acpi_native_uint * rsdp_address);
acpi_status acpi_find_root_pointer(acpi_size *rsdp_address);
acpi_status acpi_load_tables(void);
@@ -108,15 +108,15 @@ acpi_status acpi_unload_table_id(acpi_owner_id id);
acpi_status
acpi_get_table_header(acpi_string signature,
acpi_native_uint instance,
u32 instance,
struct acpi_table_header *out_table_header);
acpi_status
acpi_get_table(acpi_string signature,
acpi_native_uint instance, struct acpi_table_header **out_table);
u32 instance, struct acpi_table_header **out_table);
acpi_status
acpi_get_table_by_index(acpi_native_uint table_index,
acpi_get_table_by_index(u32 table_index,
struct acpi_table_header **out_table);
acpi_status
@@ -248,9 +248,7 @@ acpi_status acpi_disable_event(u32 event, u32 flags);
acpi_status acpi_clear_event(u32 event);
#ifdef ACPI_FUTURE_USAGE
acpi_status acpi_get_event_status(u32 event, acpi_event_status * event_status);
#endif /* ACPI_FUTURE_USAGE */
acpi_status acpi_set_gpe_type(acpi_handle gpe_device, u32 gpe_number, u8 type);
@@ -260,12 +258,10 @@ acpi_status acpi_disable_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
acpi_status acpi_clear_gpe(acpi_handle gpe_device, u32 gpe_number, u32 flags);
#ifdef ACPI_FUTURE_USAGE
acpi_status
acpi_get_gpe_status(acpi_handle gpe_device,
u32 gpe_number,
u32 flags, acpi_event_status * event_status);
#endif /* ACPI_FUTURE_USAGE */
acpi_status
acpi_install_gpe_block(acpi_handle gpe_device,

10
include/acpi/acstruct.h
View File

@@ -108,7 +108,6 @@ struct acpi_walk_state {
union acpi_operand_object **caller_return_desc;
union acpi_generic_state *control_state; /* List of control states (nested IFs) */
struct acpi_namespace_node *deferred_node; /* Used when executing deferred opcodes */
struct acpi_gpe_event_info *gpe_event_info; /* Info for GPE (_Lxx/_Exx methods only */
union acpi_operand_object *implicit_return_obj;
struct acpi_namespace_node *method_call_node; /* Called method Node */
union acpi_parse_object *method_call_op; /* method_call Op if running a method */
@@ -143,7 +142,7 @@ struct acpi_init_walk_info {
u16 package_init;
u16 object_count;
acpi_owner_id owner_id;
acpi_native_uint table_index;
u32 table_index;
};
struct acpi_get_devices_info {
@@ -189,17 +188,12 @@ struct acpi_evaluate_info {
union acpi_operand_object **parameters;
struct acpi_namespace_node *resolved_node;
union acpi_operand_object *return_object;
u8 param_count;
u8 pass_number;
u8 parameter_type;
u8 return_object_type;
u8 flags;
};
/* Types for parameter_type above */
#define ACPI_PARAM_ARGS 0
#define ACPI_PARAM_GPE 1
/* Values for Flags above */
#define ACPI_IGNORE_RETURN_VALUE 1

27
include/acpi/actables.h
View File

@@ -49,7 +49,7 @@ acpi_status acpi_allocate_root_table(u32 initial_table_count);
/*
* tbfadt - FADT parse/convert/validate
*/
void acpi_tb_parse_fadt(acpi_native_uint table_index, u8 flags);
void acpi_tb_parse_fadt(u32 table_index, u8 flags);
void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length);
@@ -58,8 +58,7 @@ void acpi_tb_create_local_fadt(struct acpi_table_header *table, u32 length);
*/
acpi_status
acpi_tb_find_table(char *signature,
char *oem_id,
char *oem_table_id, acpi_native_uint * table_index);
char *oem_id, char *oem_table_id, u32 *table_index);
/*
* tbinstal - Table removal and deletion
@@ -69,30 +68,28 @@ acpi_status acpi_tb_resize_root_table_list(void);
acpi_status acpi_tb_verify_table(struct acpi_table_desc *table_desc);
acpi_status
acpi_tb_add_table(struct acpi_table_desc *table_desc,
acpi_native_uint * table_index);
acpi_tb_add_table(struct acpi_table_desc *table_desc, u32 *table_index);
acpi_status
acpi_tb_store_table(acpi_physical_address address,
struct acpi_table_header *table,
u32 length, u8 flags, acpi_native_uint * table_index);
u32 length, u8 flags, u32 *table_index);
void acpi_tb_delete_table(struct acpi_table_desc *table_desc);
void acpi_tb_terminate(void);
void acpi_tb_delete_namespace_by_owner(acpi_native_uint table_index);
void acpi_tb_delete_namespace_by_owner(u32 table_index);
acpi_status acpi_tb_allocate_owner_id(acpi_native_uint table_index);
acpi_status acpi_tb_allocate_owner_id(u32 table_index);
acpi_status acpi_tb_release_owner_id(acpi_native_uint table_index);
acpi_status acpi_tb_release_owner_id(u32 table_index);
acpi_status
acpi_tb_get_owner_id(acpi_native_uint table_index, acpi_owner_id * owner_id);
acpi_status acpi_tb_get_owner_id(u32 table_index, acpi_owner_id *owner_id);
u8 acpi_tb_is_table_loaded(acpi_native_uint table_index);
u8 acpi_tb_is_table_loaded(u32 table_index);
void acpi_tb_set_table_loaded_flag(acpi_native_uint table_index, u8 is_loaded);
void acpi_tb_set_table_loaded_flag(u32 table_index, u8 is_loaded);
/*
* tbutils - table manager utilities
@@ -103,14 +100,14 @@ void
acpi_tb_print_table_header(acpi_physical_address address,
struct acpi_table_header *header);
u8 acpi_tb_checksum(u8 * buffer, acpi_native_uint length);
u8 acpi_tb_checksum(u8 *buffer, u32 length);
acpi_status
acpi_tb_verify_checksum(struct acpi_table_header *table, u32 length);
void
acpi_tb_install_table(acpi_physical_address address,
u8 flags, char *signature, acpi_native_uint table_index);
u8 flags, char *signature, u32 table_index);
acpi_status
acpi_tb_parse_root_table(acpi_physical_address rsdp_address, u8 flags);

23
include/acpi/actbl1.h
View File

@@ -300,6 +300,7 @@ struct acpi_table_dbgp {
/*******************************************************************************
*
* DMAR - DMA Remapping table
* From "Intel Virtualization Technology for Directed I/O", Sept. 2007
*
******************************************************************************/
@@ -310,6 +311,10 @@ struct acpi_table_dmar {
u8 reserved[10];
};
/* Flags */
#define ACPI_DMAR_INTR_REMAP (1)
/* DMAR subtable header */
struct acpi_dmar_header {
@@ -382,6 +387,20 @@ struct acpi_dmar_reserved_memory {
#define ACPI_DMAR_ALLOW_ALL (1)
/* 2: Root Port ATS Capability Reporting Structure */
struct acpi_dmar_atsr {
struct acpi_dmar_header header;
u8 flags;
u8 reserved;
u16 segment;
};
/* Flags */
#define ACPI_DMAR_ALL_PORTS (1)
/*******************************************************************************
*
* ECDT - Embedded Controller Boot Resources Table
@@ -1156,9 +1175,9 @@ struct acpi_srat_mem_affinity {
u16 reserved; /* Reserved, must be zero */
u64 base_address;
u64 length;
u32 memory_type; /* See acpi_address_range_id */
u32 reserved1;
u32 flags;
u64 reserved1; /* Reserved, must be zero */
u64 reserved2; /* Reserved, must be zero */
};
/* Flags */

16
include/acpi/actypes.h
View File

@@ -110,10 +110,10 @@
* usually used for memory allocation, efficient loop counters, and array
* indexes. The types are similar to the size_t type in the C library and are
* required because there is no C type that consistently represents the native
* data width.
* data width. ACPI_SIZE is needed because there is no guarantee that a
* kernel-level C library is present.
*
* ACPI_SIZE 16/32/64-bit unsigned value
* ACPI_NATIVE_UINT 16/32/64-bit unsigned value
* ACPI_NATIVE_INT 16/32/64-bit signed value
*
*/
@@ -147,9 +147,9 @@ typedef int INT32;
/*! [End] no source code translation !*/
typedef u64 acpi_native_uint;
typedef s64 acpi_native_int;
typedef u64 acpi_size;
typedef u64 acpi_io_address;
typedef u64 acpi_physical_address;
@@ -186,9 +186,9 @@ typedef int INT32;
/*! [End] no source code translation !*/
typedef u32 acpi_native_uint;
typedef s32 acpi_native_int;
typedef u32 acpi_size;
typedef u32 acpi_io_address;
typedef u32 acpi_physical_address;
@@ -202,10 +202,6 @@ typedef u32 acpi_physical_address;
#error unknown ACPI_MACHINE_WIDTH
#endif
/* Variable-width type, used instead of clib size_t */
typedef acpi_native_uint acpi_size;
/*******************************************************************************
*
* OS-dependent and compiler-dependent types
@@ -219,7 +215,7 @@ typedef acpi_native_uint acpi_size;
/* Value returned by acpi_os_get_thread_id */
#ifndef acpi_thread_id
#define acpi_thread_id acpi_native_uint
#define acpi_thread_id acpi_size
#endif
/* Object returned from acpi_os_create_lock */
@@ -231,7 +227,7 @@ typedef acpi_native_uint acpi_size;
/* Flags for acpi_os_acquire_lock/acpi_os_release_lock */
#ifndef acpi_cpu_flags
#define acpi_cpu_flags acpi_native_uint
#define acpi_cpu_flags acpi_size
#endif
/* Object returned from acpi_os_create_cache */

70
include/acpi/acutils.h
View File

@@ -172,7 +172,7 @@ char *acpi_ut_strstr(char *string1, char *string2);
void *acpi_ut_memcpy(void *dest, const void *src, acpi_size count);
void *acpi_ut_memset(void *dest, acpi_native_uint value, acpi_size count);
void *acpi_ut_memset(void *dest, u8 value, acpi_size count);
int acpi_ut_to_upper(int c);
@@ -245,41 +245,45 @@ void acpi_ut_track_stack_ptr(void);
void
acpi_ut_trace(u32 line_number,
const char *function_name, char *module_name, u32 component_id);
const char *function_name,
const char *module_name, u32 component_id);
void
acpi_ut_trace_ptr(u32 line_number,
const char *function_name,
char *module_name, u32 component_id, void *pointer);
const char *module_name, u32 component_id, void *pointer);
void
acpi_ut_trace_u32(u32 line_number,
const char *function_name,
char *module_name, u32 component_id, u32 integer);
const char *module_name, u32 component_id, u32 integer);
void
acpi_ut_trace_str(u32 line_number,
const char *function_name,
char *module_name, u32 component_id, char *string);
const char *module_name, u32 component_id, char *string);
void
acpi_ut_exit(u32 line_number,
const char *function_name, char *module_name, u32 component_id);
const char *function_name,
const char *module_name, u32 component_id);
void
acpi_ut_status_exit(u32 line_number,
const char *function_name,
char *module_name, u32 component_id, acpi_status status);
const char *module_name,
u32 component_id, acpi_status status);
void
acpi_ut_value_exit(u32 line_number,
const char *function_name,
char *module_name, u32 component_id, acpi_integer value);
const char *module_name,
u32 component_id, acpi_integer value);
void
acpi_ut_ptr_exit(u32 line_number,
const char *function_name,
char *module_name, u32 component_id, u8 * ptr);
const char *module_name, u32 component_id, u8 *ptr);
void acpi_ut_dump_buffer(u8 * buffer, u32 count, u32 display, u32 component_id);
@@ -297,33 +301,35 @@ void ACPI_INTERNAL_VAR_XFACE
acpi_ut_debug_print(u32 requested_debug_level,
u32 line_number,
const char *function_name,
char *module_name,
u32 component_id, char *format, ...) ACPI_PRINTF_LIKE(6);
const char *module_name,
u32 component_id,
const char *format, ...) ACPI_PRINTF_LIKE(6);
void ACPI_INTERNAL_VAR_XFACE
acpi_ut_debug_print_raw(u32 requested_debug_level,
u32 line_number,
const char *function_name,
char *module_name,
const char *module_name,
u32 component_id,
char *format, ...) ACPI_PRINTF_LIKE(6);
const char *format, ...) ACPI_PRINTF_LIKE(6);
void ACPI_INTERNAL_VAR_XFACE
acpi_ut_error(char *module_name,
u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3);
acpi_ut_error(const char *module_name,
u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3);
void ACPI_INTERNAL_VAR_XFACE
acpi_ut_exception(char *module_name,
acpi_ut_exception(const char *module_name,
u32 line_number,
acpi_status status, char *format, ...) ACPI_PRINTF_LIKE(4);
acpi_status status,
const char *format, ...) ACPI_PRINTF_LIKE(4);
void ACPI_INTERNAL_VAR_XFACE
acpi_ut_warning(char *module_name,
u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3);
acpi_ut_warning(const char *module_name,
u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3);
void ACPI_INTERNAL_VAR_XFACE
acpi_ut_info(char *module_name,
u32 line_number, char *format, ...) ACPI_PRINTF_LIKE(3);
acpi_ut_info(const char *module_name,
u32 line_number, const char *format, ...) ACPI_PRINTF_LIKE(3);
/*
* utdelete - Object deletion and reference counts
@@ -376,13 +382,14 @@ acpi_ut_execute_sxds(struct acpi_namespace_node *device_node, u8 * highest);
/*
* utobject - internal object create/delete/cache routines
*/
union acpi_operand_object *acpi_ut_create_internal_object_dbg(char *module_name,
union acpi_operand_object *acpi_ut_create_internal_object_dbg(const char
*module_name,
u32 line_number,
u32 component_id,
acpi_object_type
type);
void *acpi_ut_allocate_object_desc_dbg(char *module_name,
void *acpi_ut_allocate_object_desc_dbg(const char *module_name,
u32 line_number, u32 component_id);
#define acpi_ut_create_internal_object(t) acpi_ut_create_internal_object_dbg (_acpi_module_name,__LINE__,_COMPONENT,t)
@@ -476,7 +483,7 @@ u8 acpi_ut_valid_acpi_name(u32 name);
acpi_name acpi_ut_repair_name(char *name);
u8 acpi_ut_valid_acpi_char(char character, acpi_native_uint position);
u8 acpi_ut_valid_acpi_char(char character, u32 position);
acpi_status
acpi_ut_strtoul64(char *string, u32 base, acpi_integer * ret_integer);
@@ -543,26 +550,29 @@ acpi_status
acpi_ut_initialize_buffer(struct acpi_buffer *buffer,
acpi_size required_length);
void *acpi_ut_allocate(acpi_size size, u32 component, char *module, u32 line);
void *acpi_ut_allocate(acpi_size size,
u32 component, const char *module, u32 line);
void *acpi_ut_allocate_zeroed(acpi_size size,
u32 component, char *module, u32 line);
u32 component, const char *module, u32 line);
#ifdef ACPI_DBG_TRACK_ALLOCATIONS
void *acpi_ut_allocate_and_track(acpi_size size,
u32 component, char *module, u32 line);
u32 component, const char *module, u32 line);
void *acpi_ut_allocate_zeroed_and_track(acpi_size size,
u32 component, char *module, u32 line);
u32 component,
const char *module, u32 line);
void
acpi_ut_free_and_track(void *address, u32 component, char *module, u32 line);
acpi_ut_free_and_track(void *address,
u32 component, const char *module, u32 line);
#ifdef ACPI_FUTURE_USAGE
void acpi_ut_dump_allocation_info(void);
#endif /* ACPI_FUTURE_USAGE */
void acpi_ut_dump_allocations(u32 component, char *module);
void acpi_ut_dump_allocations(u32 component, const char *module);
acpi_status
acpi_ut_create_list(char *list_name,

2
include/acpi/processor.h
View File

@@ -255,7 +255,7 @@ extern void acpi_processor_unregister_performance(struct
int acpi_processor_notify_smm(struct module *calling_module);
/* for communication between multiple parts of the processor kernel module */
extern struct acpi_processor *processors[NR_CPUS];
DECLARE_PER_CPU(struct acpi_processor *, processors);
extern struct acpi_processor_errata errata;
void arch_acpi_processor_init_pdc(struct acpi_processor *pr);

14
include/acpi/reboot.h
View File

@@ -1,9 +1,11 @@
#ifndef __ACPI_REBOOT_H
#define __ACPI_REBOOT_H
#ifdef CONFIG_ACPI
extern void acpi_reboot(void);
#else
static inline void acpi_reboot(void) { }
#endif
/*
* Dummy placeholder to make the EFI patches apply to the x86 tree.
* Andrew/Len, please just kill this file if you encounter it.
*/
#ifndef acpi_reboot
# define acpi_reboot() do { } while (0)
#endif

44
include/asm-alpha/ide.h
View File

@@ -1,44 +0,0 @@
/*
* linux/include/asm-alpha/ide.h
*
* Copyright (C) 1994-1996 Linus Torvalds & authors
*/
/*
* This file contains the alpha architecture specific IDE code.
*/
#ifndef __ASMalpha_IDE_H
#define __ASMalpha_IDE_H
#ifdef __KERNEL__
static inline int ide_default_irq(unsigned long base)
{
switch (base) {
case 0x1f0: return 14;
case 0x170: return 15;
case 0x1e8: return 11;
case 0x168: return 10;
default:
return 0;
}
}
static inline unsigned long ide_default_io_base(int index)
{
switch (index) {
case 0: return 0x1f0;
case 1: return 0x170;
case 2: return 0x1e8;
case 3: return 0x168;
default:
return 0;
}
}
#include <asm-generic/ide_iops.h>
#endif /* __KERNEL__ */
#endif /* __ASMalpha_IDE_H */

3
include/asm-alpha/page.h
View File

@@ -80,9 +80,6 @@ typedef struct page *pgtable_t;
#endif /* !__ASSEMBLY__ */
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
#ifndef CONFIG_DISCONTIGMEM

1
include/asm-alpha/semaphore.h
View File

@@ -1 +0,0 @@
#include <linux/semaphore.h>

5
include/asm-alpha/smp.h
View File

@@ -47,12 +47,13 @@ extern struct cpuinfo_alpha cpu_data[NR_CPUS];
extern int smp_num_cpus;
#define cpu_possible_map cpu_present_map
int smp_call_function_on_cpu(void (*func) (void *info), void *info,int retry, int wait, cpumask_t cpu);
extern void arch_send_call_function_single_ipi(int cpu);
extern void arch_send_call_function_ipi(cpumask_t mask);
#else /* CONFIG_SMP */
#define hard_smp_processor_id() 0
#define smp_call_function_on_cpu(func,info,retry,wait,cpu) ({ 0; })
#define smp_call_function_on_cpu(func,info,wait,cpu) ({ 0; })
#endif /* CONFIG_SMP */

5
include/asm-alpha/socket.h
View File

@@ -62,4 +62,9 @@
#define SO_MARK 36
/* O_NONBLOCK clashes with the bits used for socket types. Therefore we
* have to define SOCK_NONBLOCK to a different value here.
*/
#define SOCK_NONBLOCK 0x40000000
#endif /* _ASM_SOCKET_H */

4
include/asm-arm/arch-at91/at91_mci.h
View File

@@ -75,6 +75,10 @@
#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
#define AT91_MCI_TRTYP_STREAM (2 << 19)
#define AT91_MCI_BLKR 0x18 /* Block Register */
#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
#define AT91_MCR_RDR 0x30 /* Receive Data Register */
#define AT91_MCR_TDR 0x34 /* Transmit Data Register */

7
include/asm-arm/arch-at91/at91_pmc.h
View File

@@ -39,10 +39,14 @@
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
@@ -97,6 +101,7 @@
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */

2
include/asm-arm/arch-at91/at91cap9.h
View File

@@ -118,7 +118,7 @@
#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6

5
include/asm-arm/arch-at91/at91cap9_matrix.h
View File

@@ -106,6 +106,11 @@
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)

11
include/asm-arm/arch-at91/at91sam9260.h
View File

@@ -6,6 +6,8 @@
* Common definitions.
* Based on AT91SAM9260 datasheet revision A (Preliminary).
*
* Includes also definitions for AT91SAM9XE and AT91SAM9G families
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -123,5 +125,14 @@
#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
#endif

2
include/asm-arm/arch-at91/at91sam9rl.h
View File

@@ -110,6 +110,6 @@
#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
#endif

6
include/asm-arm/arch-at91/board.h
View File

@@ -36,6 +36,7 @@
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/spi/spi.h>
#include <linux/usb/atmel_usba_udc.h>
/* USB Device */
struct at91_udc_data {
@@ -45,6 +46,9 @@ struct at91_udc_data {
};
extern void __init at91_add_device_udc(struct at91_udc_data *data);
/* USB High Speed Device */
extern void __init at91_add_device_usba(struct usba_platform_data *data);
/* Compact Flash */
struct at91_cf_data {
u8 irq_pin; /* I/O IRQ */
@@ -73,7 +77,7 @@ struct at91_eth_data {
};
extern void __init at91_add_device_eth(struct at91_eth_data *data);
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
#define eth_platform_data at91_eth_data
#endif

7
include/asm-arm/arch-at91/cpu.h
View File

@@ -21,6 +21,7 @@
#define ARCH_ID_AT91SAM9260 0x019803a0
#define ARCH_ID_AT91SAM9261 0x019703a0
#define ARCH_ID_AT91SAM9263 0x019607a0
#define ARCH_ID_AT91SAM9G20 0x019905a0
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
#define ARCH_ID_AT91CAP9 0x039A03A0
@@ -63,6 +64,12 @@ static inline unsigned long at91_arch_identify(void)
#define cpu_is_at91sam9260() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9G20
#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
#else
#define cpu_is_at91sam9g20() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9261
#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
#else

2
include/asm-arm/arch-at91/hardware.h
View File

@@ -18,7 +18,7 @@
#if defined(CONFIG_ARCH_AT91RM9200)
#include <asm/arch/at91rm9200.h>
#elif defined(CONFIG_ARCH_AT91SAM9260)
#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
#include <asm/arch/at91sam9260.h>
#elif defined(CONFIG_ARCH_AT91SAM9261)
#include <asm/arch/at91sam9261.h>

22
include/asm-arm/arch-at91/timex.h
View File

@@ -27,14 +27,29 @@
#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
#elif defined(CONFIG_ARCH_AT91SAM9260)
#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
#define AT91SAM9_MASTER_CLOCK 90000000
#else
#define AT91SAM9_MASTER_CLOCK 99300000
#endif
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91SAM9261)
#define AT91SAM9_MASTER_CLOCK 99300000
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91SAM9263)
#if defined(CONFIG_MACH_USB_A9263)
#define AT91SAM9_MASTER_CLOCK 90000000
#else
#define AT91SAM9_MASTER_CLOCK 99959500
#endif
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91SAM9RL)
@@ -42,6 +57,11 @@
#define AT91SAM9_MASTER_CLOCK 100000000
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91SAM9G20)
#define AT91SAM9_MASTER_CLOCK 132096000
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91CAP9)
#define AT91CAP9_MASTER_CLOCK 100000000

26
include/asm-arm/arch-ebsa285/hardware.h
View File

@@ -14,7 +14,6 @@
#include <asm/arch/memory.h>
#ifdef CONFIG_ARCH_FOOTBRIDGE
/* Virtual Physical Size
* 0xff800000 0x40000000 1MB X-Bus
* 0xff000000 0x7c000000 1MB PCI I/O space
@@ -50,31 +49,6 @@
#define PCIMEM_SIZE 0x01000000
#define PCIMEM_BASE 0xf0000000
#elif defined(CONFIG_ARCH_CO285)
/*
* This is the COEBSA285 cut-down mapping
*/
#define PCIMEM_SIZE 0x80000000
#define PCIMEM_BASE 0x80000000
#define WFLUSH_SIZE 0x01000000
#define WFLUSH_BASE 0x7d000000
#define ARMCSR_SIZE 0x00100000
#define ARMCSR_BASE 0x7cf00000
#define XBUS_SIZE 0x00020000
#define XBUS_BASE 0x7cee0000
#define PCIO_SIZE 0x00010000
#define PCIO_BASE 0x7ced0000
#else
#error "Undefined footbridge architecture"
#endif
#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000))
#define XBUS_LED_AMBER (1 << 0)
#define XBUS_LED_GREEN (1 << 1)

19
include/asm-arm/arch-ebsa285/memory.h
View File

@@ -42,8 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long);
#endif
#if defined(CONFIG_ARCH_FOOTBRIDGE)
/* Task size and page offset at 3GB */
#define TASK_SIZE UL(0xbf000000)
#define PAGE_OFFSET UL(0xc0000000)
@@ -53,23 +51,6 @@ extern unsigned long __bus_to_virt(unsigned long);
*/
#define FLUSH_BASE 0xf9000000
#elif defined(CONFIG_ARCH_CO285)
/* Task size and page offset at 1.5GB */
#define TASK_SIZE UL(0x5f000000)
#define PAGE_OFFSET UL(0x60000000)
/*
* Cache flushing area.
*/
#define FLUSH_BASE 0x7e000000
#else
#error "Undefined footbridge architecture"
#endif
/*
* Physical DRAM offset.
*/

4
include/asm-arm/arch-ebsa285/vmalloc.h
View File

@@ -7,8 +7,4 @@
*/
#ifdef CONFIG_ARCH_FOOTBRIDGE
#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
#else
#define VMALLOC_END (PAGE_OFFSET + 0x20000000)
#endif

8
include/asm-arm/arch-imx/hardware.h
View File

@@ -73,14 +73,6 @@
*/
extern void imx_gpio_mode( int gpio_mode );
/* get frequencies in Hz */
extern unsigned int imx_get_system_clk(void);
extern unsigned int imx_get_mcu_clk(void);
extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12] */
extern unsigned int imx_get_perclk3(void); /* SSI */
extern unsigned int imx_get_hclk(void); /* SDRAM, CSI, Memory Stick,*/
/* I2C, DMA */
#endif
#define MAXIRQNUM 62

2
include/asm-arm/arch-imx/imx-dma.h
View File

@@ -88,7 +88,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name);
void imx_dma_free(imx_dmach_t dma_ch);
int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio);
imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
#endif /* _ASM_ARCH_IMX_DMA_H */

2
include/asm-arm/arch-imx/imx-uart.h
View File

@@ -4,6 +4,8 @@
#define IMXUART_HAVE_RTSCTS (1<<0)
struct imxuart_platform_data {
int (*init)(struct platform_device *pdev);
void (*exit)(struct platform_device *pdev);
unsigned int flags;
};

18
include/asm-arm/arch-iop13xx/adma.h
View File

@@ -198,17 +198,13 @@ iop_chan_memset_slot_count(size_t len, int *slots_per_op)
static inline int
iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
{
int num_slots;
/* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1
* (1 source => 8 bytes) (1 slot => 32 bytes)
*/
num_slots = 1 + (((src_cnt - 1) << 3) >> 5);
if (((src_cnt - 1) << 3) & 0x1f)
num_slots++;
*slots_per_op = num_slots;
return num_slots;
static const char slot_count_table[] = { 1, 2, 2, 2,
2, 3, 3, 3,
3, 4, 4, 4,
4, 5, 5, 5,
};
*slots_per_op = slot_count_table[src_cnt - 1];
return *slots_per_op;
}
#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)

2
include/asm-arm/arch-iop13xx/dma.h
View File

@@ -1,3 +1,3 @@
#ifndef _IOP13XX_DMA_H
#define _IOP13XX_DMA_H_
#define _IOP13XX_DMA_H
#endif

6
include/asm-arm/arch-iop32x/gpio.h Normal file
View File

@@ -0,0 +1,6 @@
#ifndef __ASM_ARCH_IOP32X_GPIO_H
#define __ASM_ARCH_IOP32X_GPIO_H
#include <asm/hardware/iop3xx-gpio.h>
#endif

6
include/asm-arm/arch-iop33x/gpio.h Normal file
View File

@@ -0,0 +1,6 @@
#ifndef __ASM_ARCH_IOP33X_GPIO_H
#define __ASM_ARCH_IOP33X_GPIO_H
#include <asm/hardware/iop3xx-gpio.h>
#endif

50
include/asm-arm/arch-ixp4xx/fsg.h Normal file
View File

@@ -0,0 +1,50 @@
/*
* include/asm-arm/arch-ixp4xx/fsg.h
*
* Freecom FSG-3 platform specific definitions
*
* Author: Rod Whitby <rod@whitby.id.au>
* Author: Tomasz Chmielewski <mangoo@wpkg.org>
* Maintainers: http://www.nslu2-linux.org
*
* Based on coyote.h by
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define FSG_SDA_PIN 12
#define FSG_SCL_PIN 13
/*
* FSG PCI IRQs
*/
#define FSG_PCI_MAX_DEV 3
#define FSG_PCI_IRQ_LINES 3
/* PCI controller GPIO to IRQ pin mappings */
#define FSG_PCI_INTA_PIN 6
#define FSG_PCI_INTB_PIN 7
#define FSG_PCI_INTC_PIN 5
/* Buttons */
#define FSG_SB_GPIO 4 /* sync button */
#define FSG_RB_GPIO 9 /* reset button */
#define FSG_UB_GPIO 10 /* usb button */
/* LEDs */
#define FSG_LED_WLAN_BIT 0
#define FSG_LED_WAN_BIT 1
#define FSG_LED_SATA_BIT 2
#define FSG_LED_USB_BIT 4
#define FSG_LED_RING_BIT 5
#define FSG_LED_SYNC_BIT 7

1
include/asm-arm/arch-ixp4xx/hardware.h
View File

@@ -45,5 +45,6 @@
#include "nslu2.h"
#include "nas100d.h"
#include "dsmg600.h"
#include "fsg.h"
#endif /* _ASM_ARCH_HARDWARE_H */

7
include/asm-arm/arch-ixp4xx/irqs.h
View File

@@ -128,4 +128,11 @@
#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
/*
* Freecom FSG-3 Board IRQs
*/
#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
#endif

20
include/asm-arm/arch-kirkwood/debug-macro.S Normal file
View File

@@ -0,0 +1,20 @@
/*
* include/asm-arm/arch-kirkwood/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/kirkwood.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE
ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE
orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

1
include/asm-arm/arch-kirkwood/dma.h Normal file
View File

@@ -0,0 +1 @@
/* empty */

40
include/asm-arm/arch-kirkwood/entry-macro.S Normal file
View File

@@ -0,0 +1,40 @@
/*
* include/asm-arm/arch-kirkwood/entry-macro.S
*
* Low-level IRQ helper macros for Marvell Kirkwood platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/kirkwood.h>
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IRQ_VIRT_BASE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check low interrupts
ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
mov \irqnr, #31
ands \irqstat, \irqstat, \tmp
bne 1001f
@ if no low interrupts set, check high interrupts
ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
mov \irqnr, #63
ands \irqstat, \irqstat, \tmp
@ find first active interrupt source
1001: clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm

21
include/asm-arm/arch-kirkwood/hardware.h Normal file
View File

@@ -0,0 +1,21 @@
/*
* include/asm-arm/arch-kirkwood/hardware.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include "kirkwood.h"
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
#endif

26
include/asm-arm/arch-kirkwood/io.h Normal file
View File

@@ -0,0 +1,26 @@
/*
* include/asm-arm/arch-kirkwood/io.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include "kirkwood.h"
#define IO_SPACE_LIMIT 0xffffffff
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
+ KIRKWOOD_PCIE_IO_VIRT_BASE);
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif

63
include/asm-arm/arch-kirkwood/irqs.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* include/asm-arm/arch-kirkwood/irqs.h
*
* IRQ definitions for Marvell Kirkwood SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include "kirkwood.h" /* need GPIO_MAX */
/*
* Low Interrupt Controller
*/
#define IRQ_KIRKWOOD_HIGH_SUM 0
#define IRQ_KIRKWOOD_BRIDGE 1
#define IRQ_KIRKWOOD_HOST2CPU 2
#define IRQ_KIRKWOOD_CPU2HOST 3
#define IRQ_KIRKWOOD_XOR_00 5
#define IRQ_KIRKWOOD_XOR_01 6
#define IRQ_KIRKWOOD_XOR_10 7
#define IRQ_KIRKWOOD_XOR_11 8
#define IRQ_KIRKWOOD_PCIE 9
#define IRQ_KIRKWOOD_GE00_SUM 11
#define IRQ_KIRKWOOD_GE01_SUM 15
#define IRQ_KIRKWOOD_USB 19
#define IRQ_KIRKWOOD_SATA 21
#define IRQ_KIRKWOOD_CRYPTO 22
#define IRQ_KIRKWOOD_SPI 23
#define IRQ_KIRKWOOD_I2S 24
#define IRQ_KIRKWOOD_TS_0 26
#define IRQ_KIRKWOOD_SDIO 28
#define IRQ_KIRKWOOD_TWSI 29
#define IRQ_KIRKWOOD_AVB 30
#define IRQ_KIRKWOOD_TDMI 31
/*
* High Interrupt Controller
*/
#define IRQ_KIRKWOOD_UART_0 33
#define IRQ_KIRKWOOD_UART_1 34
#define IRQ_KIRKWOOD_GPIO_LOW_0_7 35
#define IRQ_KIRKWOOD_GPIO_LOW_8_15 36
#define IRQ_KIRKWOOD_GPIO_LOW_16_23 37
#define IRQ_KIRKWOOD_GPIO_LOW_24_31 38
#define IRQ_KIRKWOOD_GPIO_HIGH_0_7 39
#define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40
#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
/*
* KIRKWOOD General Purpose Pins
*/
#define IRQ_KIRKWOOD_GPIO_START 64
#define NR_GPIO_IRQS GPIO_MAX
#define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
#endif

100
include/asm-arm/arch-kirkwood/kirkwood.h Normal file
View File

@@ -0,0 +1,100 @@
/*
* include/asm-arm/arch-kirkwood/kirkwood.h
*
* Generic definitions for Marvell Kirkwood SoC flavors:
* 88F6180, 88F6192 and 88F6281.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_KIRKWOOD_H
#define __ASM_ARCH_KIRKWOOD_H
/*
* Marvell Kirkwood address maps.
*
* phys
* e0000000 PCIe Memory space
* f1000000 on-chip peripheral registers
* f2000000 PCIe I/O space
* f3000000 NAND controller address window
*
* virt phys size
* fee00000 f1000000 1M on-chip peripheral registers
* fef00000 f2000000 1M PCIe I/O space
*/
#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K
* is the minimal window size
*/
#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
#define KIRKWOOD_REGS_SIZE SZ_1M
#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
/*
* MBUS bridge registers.
*/
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0000
#define IRQ_MASK_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
#define L2_WRITETHROUGH 0x00000010
/*
* Register Map
*/
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
#define GPIO_MAX 50
#endif

14
include/asm-arm/arch-kirkwood/memory.h Normal file
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@@ -0,0 +1,14 @@
/*
* include/asm-arm/arch-kirkwood/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

37
include/asm-arm/arch-kirkwood/system.h Normal file
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@@ -0,0 +1,37 @@
/*
* include/asm-arm/arch-kirkwood/system.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/hardware.h>
#include <asm/arch/kirkwood.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}
#endif

11
include/asm-arm/arch-kirkwood/timex.h Normal file
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@@ -0,0 +1,11 @@
/*
* include/asm-arm/arch-kirkwood/timex.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define CLOCK_TICK_RATE (100 * HZ)
#define KIRKWOOD_TCLK 166666667

47
include/asm-arm/arch-kirkwood/uncompress.h Normal file
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@@ -0,0 +1,47 @@
/*
* include/asm-arm/arch-kirkwood/uncompress.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/serial_reg.h>
#include <asm/arch/kirkwood.h>
#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
static void putc(const char c)
{
unsigned char *base = SERIAL_BASE;
int i;
for (i = 0; i < 0x1000; i++) {
if (base[UART_LSR << 2] & UART_LSR_THRE)
break;
barrier();
}
base[UART_TX << 2] = c;
}
static void flush(void)
{
unsigned char *base = SERIAL_BASE;
unsigned char mask;
int i;
mask = UART_LSR_TEMT | UART_LSR_THRE;
for (i = 0; i < 0x1000; i++) {
if ((base[UART_LSR << 2] & mask) == mask)
break;
barrier();
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

5
include/asm-arm/arch-kirkwood/vmalloc.h Normal file
View File

@@ -0,0 +1,5 @@
/*
* include/asm-arm/arch-kirkwood/vmalloc.h
*/
#define VMALLOC_END 0xfe800000

20
include/asm-arm/arch-loki/debug-macro.S Normal file
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@@ -0,0 +1,20 @@
/*
* include/asm-arm/arch-loki/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/loki.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =LOKI_REGS_PHYS_BASE
ldrne \rx, =LOKI_REGS_VIRT_BASE
orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

1
include/asm-arm/arch-loki/dma.h Normal file
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@@ -0,0 +1 @@
/* empty */

30
include/asm-arm/arch-loki/entry-macro.S Normal file
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@@ -0,0 +1,30 @@
/*
* include/asm-arm/arch-loki/entry-macro.S
*
* Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/loki.h>
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IRQ_VIRT_BASE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
ldr \tmp, [\base, #IRQ_MASK_OFF]
mov \irqnr, #0
ands \irqstat, \irqstat, \tmp
clzne \irqnr, \irqstat
rsbne \irqnr, \irqnr, #31
.endm

15
include/asm-arm/arch-loki/hardware.h Normal file
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@@ -0,0 +1,15 @@
/*
* include/asm-arm/arch-loki/hardware.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include "loki.h"
#endif

26
include/asm-arm/arch-loki/io.h Normal file
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@@ -0,0 +1,26 @@
/*
* include/asm-arm/arch-loki/io.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include "loki.h"
#define IO_SPACE_LIMIT 0xffffffff
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
+ LOKI_PCIE0_IO_VIRT_BASE);
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif

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include/asm-arm/arch-loki/irqs.h Normal file
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/*
* include/asm-arm/arch-loki/irqs.h
*
* IRQ definitions for Marvell Loki (88RC8480) SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include "loki.h" /* need GPIO_MAX */
/*
* Interrupt Controller
*/
#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
#define IRQ_LOKI_COM_A_ERR 6
#define IRQ_LOKI_COM_A_IN 7
#define IRQ_LOKI_COM_A_OUT 8
#define IRQ_LOKI_COM_B_ERR 9
#define IRQ_LOKI_COM_B_IN 10
#define IRQ_LOKI_COM_B_OUT 11
#define IRQ_LOKI_DMA_A 12
#define IRQ_LOKI_DMA_B 13
#define IRQ_LOKI_SAS_A 14
#define IRQ_LOKI_SAS_B 15
#define IRQ_LOKI_DDR 16
#define IRQ_LOKI_XOR 17
#define IRQ_LOKI_BRIDGE 18
#define IRQ_LOKI_PCIE_A_ERR 20
#define IRQ_LOKI_PCIE_A_INT 21
#define IRQ_LOKI_PCIE_B_ERR 22
#define IRQ_LOKI_PCIE_B_INT 23
#define IRQ_LOKI_GBE_A_INT 24
#define IRQ_LOKI_GBE_B_INT 25
#define IRQ_LOKI_DEV_ERR 26
#define IRQ_LOKI_UART0 27
#define IRQ_LOKI_UART1 28
#define IRQ_LOKI_TWSI 29
#define IRQ_LOKI_GPIO_23_0 30
#define IRQ_LOKI_GPIO_25_24 31
/*
* Loki General Purpose Pins
*/
#define IRQ_LOKI_GPIO_START 32
#define NR_GPIO_IRQS GPIO_MAX
#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
#endif

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include/asm-arm/arch-loki/loki.h Normal file
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/*
* include/asm-arm/arch-loki/loki.h
*
* Generic definitions for Marvell Loki (88RC8480) SoC flavors
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_LOKI_H
#define __ASM_ARCH_LOKI_H
/*
* Marvell Loki (88RC8480) address maps.
*
* phys
* d0000000 on-chip peripheral registers
* e0000000 PCIe 0 Memory space
* e8000000 PCIe 1 Memory space
* f0000000 PCIe 0 I/O space
* f0100000 PCIe 1 I/O space
*
* virt phys size
* fed00000 d0000000 1M on-chip peripheral registers
* fee00000 f0000000 64K PCIe 0 I/O space
* fef00000 f0100000 64K PCIe 1 I/O space
*/
#define LOKI_REGS_PHYS_BASE 0xd0000000
#define LOKI_REGS_VIRT_BASE 0xfed00000
#define LOKI_REGS_SIZE SZ_1M
#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
#define LOKI_PCIE0_IO_SIZE SZ_64K
#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
#define LOKI_PCIE1_IO_SIZE SZ_64K
#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
#define LOKI_PCIE0_MEM_SIZE SZ_128M
#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
#define LOKI_PCIE1_MEM_SIZE SZ_128M
/*
* Register Map
*/
#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR 0x0004
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_OFF 0x0000
#define IRQ_MASK_OFF 0x0004
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
#define DDR_REG(x) (DDR_VIRT_BASE | (x))
#define GPIO_MAX 8
#endif

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include/asm-arm/arch-loki/memory.h Normal file
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/*
* include/asm-arm/arch-loki/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

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include/asm-arm/arch-loki/system.h Normal file
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/*
* include/asm-arm/arch-loki/system.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/hardware.h>
#include <asm/arch/loki.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}
#endif

11
include/asm-arm/arch-loki/timex.h Normal file
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/*
* include/asm-arm/arch-loki/timex.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define CLOCK_TICK_RATE (100 * HZ)
#define LOKI_TCLK 180000000

47
include/asm-arm/arch-loki/uncompress.h Normal file
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/*
* include/asm-arm/arch-loki/uncompress.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/serial_reg.h>
#include <asm/arch/loki.h>
#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
static void putc(const char c)
{
unsigned char *base = SERIAL_BASE;
int i;
for (i = 0; i < 0x1000; i++) {
if (base[UART_LSR << 2] & UART_LSR_THRE)
break;
barrier();
}
base[UART_TX << 2] = c;
}
static void flush(void)
{
unsigned char *base = SERIAL_BASE;
unsigned char mask;
int i;
mask = UART_LSR_TEMT | UART_LSR_THRE;
for (i = 0; i < 0x1000; i++) {
if ((base[UART_LSR << 2] & mask) == mask)
break;
barrier();
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

5
include/asm-arm/arch-loki/vmalloc.h Normal file
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/*
* include/asm-arm/arch-loki/vmalloc.h
*/
#define VMALLOC_END 0xfe800000

1
include/asm-arm/arch-msm/irqs.h
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@@ -15,6 +15,7 @@
*/
#ifndef __ASM_ARCH_MSM_IRQS_H
#define __ASM_ARCH_MSM_IRQS_H
/* MSM ARM11 Interrupt Numbers */
/* See 80-VE113-1 A, pp219-221 */

1
include/asm-arm/arch-msm/timex.h
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@@ -14,6 +14,7 @@
*/
#ifndef __ASM_ARCH_MSM_TIMEX_H
#define __ASM_ARCH_MSM_TIMEX_H
#define CLOCK_TICK_RATE 1000000

20
include/asm-arm/arch-mv78xx0/debug-macro.S Normal file
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/*
* include/asm-arm/arch-mv78xx0/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/mv78xx0.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =MV78XX0_REGS_PHYS_BASE
ldrne \rx, =MV78XX0_REGS_VIRT_BASE
orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

1
include/asm-arm/arch-mv78xx0/dma.h Normal file
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/* empty */

39
include/asm-arm/arch-mv78xx0/entry-macro.S Normal file
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/*
* include/asm-arm/arch-mv78xx0/entry-macro.S
*
* Low-level IRQ helper macros for Marvell MV78xx0 platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/mv78xx0.h>
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IRQ_VIRT_BASE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check low interrupts
ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
mov \irqnr, #31
ands \irqstat, \irqstat, \tmp
@ if no low interrupts set, check high interrupts
ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
moveq \irqnr, #63
andeqs \irqstat, \irqstat, \tmp
@ find first active interrupt source
clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm

21
include/asm-arm/arch-mv78xx0/hardware.h Normal file
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/*
* include/asm-arm/arch-mv78xx0/hardware.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include "mv78xx0.h"
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
#endif

26
include/asm-arm/arch-mv78xx0/io.h Normal file
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/*
* include/asm-arm/arch-mv78xx0/io.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include "mv78xx0.h"
#define IO_SPACE_LIMIT 0xffffffff
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
+ MV78XX0_PCIE_IO_VIRT_BASE(0));
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif

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include/asm-arm/arch-mv78xx0/irqs.h Normal file
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/*
* include/asm-arm/arch-mv78xx0/irqs.h
*
* IRQ definitions for Marvell MV78xx0 SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include "mv78xx0.h" /* need GPIO_MAX */
/*
* MV78xx0 Low Interrupt Controller
*/
#define IRQ_MV78XX0_ERR 0
#define IRQ_MV78XX0_SPI 1
#define IRQ_MV78XX0_I2C_0 2
#define IRQ_MV78XX0_I2C_1 3
#define IRQ_MV78XX0_IDMA_0 4
#define IRQ_MV78XX0_IDMA_1 5
#define IRQ_MV78XX0_IDMA_2 6
#define IRQ_MV78XX0_IDMA_3 7
#define IRQ_MV78XX0_TIMER_0 8
#define IRQ_MV78XX0_TIMER_1 9
#define IRQ_MV78XX0_TIMER_2 10
#define IRQ_MV78XX0_TIMER_3 11
#define IRQ_MV78XX0_UART_0 12
#define IRQ_MV78XX0_UART_1 13
#define IRQ_MV78XX0_UART_2 14
#define IRQ_MV78XX0_UART_3 15
#define IRQ_MV78XX0_USB_0 16
#define IRQ_MV78XX0_USB_1 17
#define IRQ_MV78XX0_USB_2 18
#define IRQ_MV78XX0_CRYPTO 19
#define IRQ_MV78XX0_SDIO_0 20
#define IRQ_MV78XX0_SDIO_1 21
#define IRQ_MV78XX0_XOR_0 22
#define IRQ_MV78XX0_XOR_1 23
#define IRQ_MV78XX0_I2S_0 24
#define IRQ_MV78XX0_I2S_1 25
#define IRQ_MV78XX0_SATA 26
#define IRQ_MV78XX0_TDMI 27
/*
* MV78xx0 High Interrupt Controller
*/
#define IRQ_MV78XX0_PCIE_00 32
#define IRQ_MV78XX0_PCIE_01 33
#define IRQ_MV78XX0_PCIE_02 34
#define IRQ_MV78XX0_PCIE_03 35
#define IRQ_MV78XX0_PCIE_10 36
#define IRQ_MV78XX0_PCIE_11 37
#define IRQ_MV78XX0_PCIE_12 38
#define IRQ_MV78XX0_PCIE_13 39
#define IRQ_MV78XX0_GE00_SUM 40
#define IRQ_MV78XX0_GE00_RX 41
#define IRQ_MV78XX0_GE00_TX 42
#define IRQ_MV78XX0_GE00_MISC 43
#define IRQ_MV78XX0_GE01_SUM 44
#define IRQ_MV78XX0_GE01_RX 45
#define IRQ_MV78XX0_GE01_TX 46
#define IRQ_MV78XX0_GE01_MISC 47
#define IRQ_MV78XX0_GE10_SUM 48
#define IRQ_MV78XX0_GE10_RX 49
#define IRQ_MV78XX0_GE10_TX 50
#define IRQ_MV78XX0_GE10_MISC 51
#define IRQ_MV78XX0_GE11_SUM 52
#define IRQ_MV78XX0_GE11_RX 53
#define IRQ_MV78XX0_GE11_TX 54
#define IRQ_MV78XX0_GE11_MISC 55
#define IRQ_MV78XX0_GPIO_0_7 56
#define IRQ_MV78XX0_GPIO_8_15 57
#define IRQ_MV78XX0_GPIO_16_23 58
#define IRQ_MV78XX0_GPIO_24_31 59
#define IRQ_MV78XX0_DB_IN 60
#define IRQ_MV78XX0_DB_OUT 61
/*
* MV78XX0 General Purpose Pins
*/
#define IRQ_MV78XX0_GPIO_START 64
#define NR_GPIO_IRQS GPIO_MAX
#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
#endif

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include/asm-arm/arch-mv78xx0/memory.h Normal file
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/*
* include/asm-arm/arch-mv78xx0/memory.h
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

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include/asm-arm/arch-mv78xx0/mv78xx0.h Normal file
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/*
* include/asm-arm/arch-mv78xx0/mv78xx0.h
*
* Generic definitions for Marvell MV78xx0 SoC flavors:
* MV781x0 and MV782x0.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_MV78XX0_H
#define __ASM_ARCH_MV78XX0_H
/*
* Marvell MV78xx0 address maps.
*
* phys
* c0000000 PCIe Memory space
* f0800000 PCIe #0 I/O space
* f0900000 PCIe #1 I/O space
* f0a00000 PCIe #2 I/O space
* f0b00000 PCIe #3 I/O space
* f0c00000 PCIe #4 I/O space
* f0d00000 PCIe #5 I/O space
* f0e00000 PCIe #6 I/O space
* f0f00000 PCIe #7 I/O space
* f1000000 on-chip peripheral registers
*
* virt phys size
* fe400000 f102x000 16K core-specific peripheral registers
* fe700000 f0800000 1M PCIe #0 I/O space
* fe800000 f0900000 1M PCIe #1 I/O space
* fe900000 f0a00000 1M PCIe #2 I/O space
* fea00000 f0b00000 1M PCIe #3 I/O space
* feb00000 f0c00000 1M PCIe #4 I/O space
* fec00000 f0d00000 1M PCIe #5 I/O space
* fed00000 f0e00000 1M PCIe #6 I/O space
* fee00000 f0f00000 1M PCIe #7 I/O space
* fef00000 f1000000 1M on-chip peripheral registers
*/
#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
#define MV78XX0_CORE_REGS_SIZE SZ_16K
#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
#define MV78XX0_PCIE_IO_SIZE SZ_1M
#define MV78XX0_REGS_PHYS_BASE 0xf1000000
#define MV78XX0_REGS_VIRT_BASE 0xfef00000
#define MV78XX0_REGS_SIZE SZ_1M
#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
#define MV78XX0_PCIE_MEM_SIZE 0x30000000
/*
* Core-specific peripheral registers.
*/
#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define L2_WRITETHROUGH 0x00020000
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0008
#define IRQ_MASK_LOW_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
/*
* Register Map
*/
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700)
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200)
#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200)
#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300)
#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300)
#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000)
#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000)
#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000)
#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000)
#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000)
#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000)
#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000)
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000)
#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000)
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
#define GPIO_MAX 32
#endif

37
include/asm-arm/arch-mv78xx0/system.h Normal file
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@@ -0,0 +1,37 @@
/*
* include/asm-arm/arch-mv78xx0/system.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/hardware.h>
#include <asm/arch/mv78xx0.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
/*
* Enable soft reset to assert RSTOUTn.
*/
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
/*
* Assert soft reset.
*/
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
while (1)
;
}
#endif

9
include/asm-arm/arch-mv78xx0/timex.h Normal file
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@@ -0,0 +1,9 @@
/*
* include/asm-arm/arch-mv78xx0/timex.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define CLOCK_TICK_RATE (100 * HZ)

47
include/asm-arm/arch-mv78xx0/uncompress.h Normal file
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@@ -0,0 +1,47 @@
/*
* include/asm-arm/arch-mv78xx0/uncompress.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/serial_reg.h>
#include <asm/arch/mv78xx0.h>
#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
static void putc(const char c)
{
unsigned char *base = SERIAL_BASE;
int i;
for (i = 0; i < 0x1000; i++) {
if (base[UART_LSR << 2] & UART_LSR_THRE)
break;
barrier();
}
base[UART_TX << 2] = c;
}
static void flush(void)
{
unsigned char *base = SERIAL_BASE;
unsigned char mask;
int i;
mask = UART_LSR_TEMT | UART_LSR_THRE;
for (i = 0; i < 0x1000; i++) {
if ((base[UART_LSR << 2] & mask) == mask)
break;
barrier();
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

5
include/asm-arm/arch-mv78xx0/vmalloc.h Normal file
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@@ -0,0 +1,5 @@
/*
* include/asm-arm/arch-mv78xx0/vmalloc.h
*/
#define VMALLOC_END 0xfe000000

354
include/asm-arm/arch-mxc/board-mx27ads.h Normal file
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/*
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
/* external interrupt multiplexer */
#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
MXC_MAX_VIRTUAL_INTS)
/*
* MXC UART EVB board level configurations
*/
#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
#define MXC_LL_EXTUART_16BIT_BUS
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
/*
* @name Memory Size parameters
*/
/*
* Size of SDRAM memory
*/
#define SDRAM_MEM_SIZE SZ_128M
/*
* PBC Controller parameters
*/
/*
* Base address of PBC controller, CS4
*/
#define PBC_BASE_ADDRESS 0xEB000000
#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
/*
* PBC Interupt name definitions
*/
#define PBC_GPIO1_0 0
#define PBC_GPIO1_1 1
#define PBC_GPIO1_2 2
#define PBC_GPIO1_3 3
#define PBC_GPIO1_4 4
#define PBC_GPIO1_5 5
#define PBC_INTR_MAX_NUM 6
#define PBC_INTR_SHARED_MAX_NUM 8
/* When the PBC address connection is fixed in h/w, defined as 1 */
#define PBC_ADDR_SH 0
/* Offsets for the PBC Controller register */
/*
* PBC Board version register offset
*/
#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
/*
* PBC Board control register 1 set address.
*/
#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
/*
* PBC Board control register 1 clear address.
*/
#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
/*
* PBC Board control register 2 set address.
*/
#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
/*
* PBC Board control register 2 clear address.
*/
#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
/*
* PBC Board control register 3 set address.
*/
#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
/*
* PBC Board control register 3 clear address.
*/
#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
/*
* PBC Board control register 3 set address.
*/
#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
/*
* PBC Board control register 4 clear address.
*/
#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
/*PBC_ADDR_SH
* PBC Board status register 1.
*/
#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
/*
* PBC Board interrupt status register.
*/
#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
/*
* PBC Board interrupt current status register.
*/
#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
/*
* PBC Interrupt mask register set address.
*/
#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
/*
* PBC Interrupt mask register clear address.
*/
#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
/*
* External UART A.
*/
#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
/*
* UART 4 Expanding Signal Status.
*/
#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
/*
* UART 4 Expanding Signal Control Set.
*/
#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
/*
* UART 4 Expanding Signal Control Clear.
*/
#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
/*
* Ethernet Controller IO base address.
*/
#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
/*
* Ethernet Controller Memory base address.
*/
#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
/*
* Ethernet Controller DMA base address.
*/
#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
/* PBC Board Version Register bit definition */
#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
/* PBC Board Control Register 1 bit definitions */
#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
/* PBC Board Control Register 2 bit definitions */
#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
#define PBC_BCTRL2_ATAFEC_EN 0X0010
#define PBC_BCTRL2_ATAFEC_SEL 0X0020
#define PBC_BCTRL2_ATA_EN 0X0040
#define PBC_BCTRL2_IRDA_SD 0X0080
#define PBC_BCTRL2_IRDA_EN 0X0100
#define PBC_BCTRL2_CCTL10 0X0200
#define PBC_BCTRL2_CCTL11 0X0400
/* PBC Board Control Register 3 bit definitions */
#define PBC_BCTRL3_HSH_EN 0X0020
#define PBC_BCTRL3_FSH_MOD 0X0040
#define PBC_BCTRL3_OTG_HS_EN 0X0080
#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
#define PBC_BCTRL3_USB_OTG_ON 0X0800
#define PBC_BCTRL3_USB_FSH_ON 0X1000
/* PBC Board Control Register 4 bit definitions */
#define PBC_BCTRL4_REGEN_SEL 0X0001
#define PBC_BCTRL4_USER_OFF 0X0002
#define PBC_BCTRL4_VIB_EN 0X0004
#define PBC_BCTRL4_PWRGT1_EN 0X0008
#define PBC_BCTRL4_PWRGT2_EN 0X0010
#define PBC_BCTRL4_STDBY_PRI 0X0020
#ifndef __ASSEMBLY__
/*
* Enumerations for SD cards and memory stick card. This corresponds to
* the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
*/
enum mxc_card_no {
MXC_CARD_SD2 = 0,
MXC_CARD_SD3,
MXC_CARD_MS,
MXC_CARD_SD1,
MXC_CARD_MIN = MXC_CARD_SD2,
MXC_CARD_MAX = MXC_CARD_SD1,
};
#endif
#define MXC_CPLD_VER_1_50 0x01
/*
* PBC BSTAT Register bit definitions
*/
#define PBC_BSTAT_PRI_INT 0X0001
#define PBC_BSTAT_USB_BYP 0X0002
#define PBC_BSTAT_ATA_IOCS16 0X0004
#define PBC_BSTAT_ATA_CBLID 0X0008
#define PBC_BSTAT_ATA_DASP 0X0010
#define PBC_BSTAT_PWR_RDY 0X0020
#define PBC_BSTAT_SD3_WP 0X0100
#define PBC_BSTAT_SD2_WP 0X0200
#define PBC_BSTAT_SD1_WP 0X0400
#define PBC_BSTAT_SD3_DET 0X0800
#define PBC_BSTAT_SD2_DET 0X1000
#define PBC_BSTAT_SD1_DET 0X2000
#define PBC_BSTAT_MS_DET 0X4000
#define PBC_BSTAT_SD3_DET_BIT 11
#define PBC_BSTAT_SD2_DET_BIT 12
#define PBC_BSTAT_SD1_DET_BIT 13
#define PBC_BSTAT_MS_DET_BIT 14
#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
0x0))))
/*
* PBC UART Control Register bit definitions
*/
#define PBC_UCTRL_DCE_DCD 0X0001
#define PBC_UCTRL_DCE_DSR 0X0002
#define PBC_UCTRL_DCE_RI 0X0004
#define PBC_UCTRL_DTE_DTR 0X0100
/*
* PBC UART Status Register bit definitions
*/
#define PBC_USTAT_DTE_DCD 0X0001
#define PBC_USTAT_DTE_DSR 0X0002
#define PBC_USTAT_DTE_RI 0X0004
#define PBC_USTAT_DCE_DTR 0X0100
/*
* PBC Interupt mask register bit definitions
*/
#define PBC_INTR_SD3_R_EN_BIT 4
#define PBC_INTR_SD2_R_EN_BIT 0
#define PBC_INTR_SD1_R_EN_BIT 6
#define PBC_INTR_MS_R_EN_BIT 5
#define PBC_INTR_SD3_EN_BIT 13
#define PBC_INTR_SD2_EN_BIT 12
#define PBC_INTR_MS_EN_BIT 14
#define PBC_INTR_SD1_EN_BIT 15
#define PBC_INTR_SD2_R_EN 0x0001
#define PBC_INTR_LOW_BAT 0X0002
#define PBC_INTR_OTG_FSOVER 0X0004
#define PBC_INTR_FSH_OVER 0X0008
#define PBC_INTR_SD3_R_EN 0x0010
#define PBC_INTR_MS_R_EN 0x0020
#define PBC_INTR_SD1_R_EN 0x0040
#define PBC_INTR_FEC_INT 0X0080
#define PBC_INTR_ENET_INT 0X0100
#define PBC_INTR_OTGFS_INT 0X0200
#define PBC_INTR_XUART_INT 0X0400
#define PBC_INTR_CCTL12 0X0800
#define PBC_INTR_SD2_EN 0x1000
#define PBC_INTR_SD3_EN 0x2000
#define PBC_INTR_MS_EN 0x4000
#define PBC_INTR_SD1_EN 0x8000
/* For interrupts like xuart, enet etc */
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
#define MXC_MAX_EXP_IO_LINES 16
/*
* This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
*
*/
#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
/*
* This is System IRQ used by CS8900A for interrupt generation
* taken from platform.h
*/
#define CS8900AIRQ EXPIO_INT_ENET_INT
/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
/*
* This is used to detect if the CPLD version is for mx27 evb board rev-a
*/
#define PBC_CPLD_VERSION_IS_REVA() \
((__raw_readw(PBC_VERSION_REG) & \
(PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
== 0)
/* This is used to active or inactive ata signal in CPLD .
* It is dependent with hardware
*/
#define PBC_ATA_SIGNAL_ACTIVE() \
__raw_writew( \
PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
PBC_BCTRL2_CLEAR_REG)
#define PBC_ATA_SIGNAL_INACTIVE() \
__raw_writew( \
PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
PBC_BCTRL2_SET_REG)
#define MXC_BD_LED1 (1 << 5)
#define MXC_BD_LED2 (1 << 6)
#define MXC_BD_LED_ON(led) \
__raw_writew(led, PBC_BCTRL1_SET_REG)
#define MXC_BD_LED_OFF(led) \
__raw_writew(led, PBC_BCTRL1_CLEAR_REG)
/* to determine the correct external crystal reference */
#define CKIH_27MHZ_BIT_SET (1 << 3)
#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */

5
include/asm-arm/arch-mxc/board-mx31ads.h
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@@ -109,4 +109,9 @@
#define MXC_MAX_EXP_IO_LINES 16
/* mandatory for CONFIG_LL_DEBUG */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */

38
include/asm-arm/arch-mxc/board-mx31lite.h Normal file
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@@ -0,0 +1,38 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
#define MXC_MAX_EXP_IO_LINES 16
/*
* Memory Size parameters
*/
/*
* Size of SDRAM memory
*/
#define SDRAM_MEM_SIZE SZ_128M
/*
* Size of MBX buffer memory
*/
#define MXC_MBX_MEM_SIZE SZ_16M
/*
* Size of memory available to kernel
*/
#define MEM_SIZE (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */

27
include/asm-arm/arch-mxc/board-pcm037.h Normal file
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@@ -0,0 +1,27 @@
/*
* Copyright (C) 2008 Sascha Hauer, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
#define __ASM_ARCH_MXC_BOARD_PCM037_H__
/* mandatory for CONFIG_LL_DEBUG */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */

41
include/asm-arm/arch-mxc/board-pcm038.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
#define __ASM_ARCH_MXC_BOARD_PCM038_H__
/* mandatory for CONFIG_LL_DEBUG */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
#ifndef __ASSEMBLY__
/*
* This CPU module needs a baseboard to work. After basic initializing
* its own devices, it calls baseboard's init function.
* TODO: Add your own baseboard init function and call it from
* inside pcm038_init().
*
* This example here is for the development board. Refer pcm970-baseboard.c
*/
extern void pcm970_baseboard_init(void);
#endif
#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */

67
include/asm-arm/arch-mxc/clock.h Normal file
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@@ -0,0 +1,67 @@
/*
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_CLOCK_H__
#define __ASM_ARCH_MXC_CLOCK_H__
#ifndef __ASSEMBLY__
#include <linux/list.h>
struct module;
struct clk {
struct list_head node;
struct module *owner;
const char *name;
int id;
/* Source clock this clk depends on */
struct clk *parent;
/* Secondary clock to enable/disable with this clock */
struct clk *secondary;
/* Reference count of clock enable/disable */
__s8 usecount;
/* Register bit position for clock's enable/disable control. */
u8 enable_shift;
/* Register address for clock's enable/disable control. */
u32 enable_reg;
u32 flags;
/* get the current clock rate (always a fresh value) */
unsigned long (*get_rate) (struct clk *);
/* Function ptr to set the clock to a new rate. The rate must match a
supported rate returned from round_rate. Leave blank if clock is not
programmable */
int (*set_rate) (struct clk *, unsigned long);
/* Function ptr to round the requested clock rate to the nearest
supported rate that is less than or equal to the requested rate. */
unsigned long (*round_rate) (struct clk *, unsigned long);
/* Function ptr to enable the clock. Leave blank if clock can not
be gated. */
int (*enable) (struct clk *);
/* Function ptr to disable the clock. Leave blank if clock can not
be gated. */
void (*disable) (struct clk *);
/* Function ptr to set the parent clock of the clock. */
int (*set_parent) (struct clk *, struct clk *);
};
int clk_register(struct clk *clk);
void clk_unregister(struct clk *clk);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MXC_CLOCK_H__ */

6
include/asm-arm/arch-mxc/common.h
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@@ -11,10 +11,10 @@
#ifndef __ASM_ARCH_MXC_COMMON_H__
#define __ASM_ARCH_MXC_COMMON_H__
struct sys_timer;
extern void mxc_map_io(void);
extern void mxc_init_irq(void);
extern struct sys_timer mxc_timer;
extern void mxc_timer_init(const char *clk_timer);
extern int mxc_clocks_init(unsigned long fref);
extern int mxc_register_gpios(void);
#endif

49
include/asm-arm/arch-mxc/debug-macro.S Normal file
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@@ -0,0 +1,49 @@
/* linux/include/asm-arm/arch-imx/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/arch/hardware.h>
#ifdef CONFIG_MACH_MX31ADS
#include <asm/arch/board-mx31ads.h>
#endif
#ifdef CONFIG_MACH_PCM037
#include <asm/arch/board-pcm037.h>
#endif
#ifdef CONFIG_MACH_MX31LITE
#include <asm/arch/board-mx31lite.h>
#endif
#ifdef CONFIG_MACH_MX27ADS
#include <asm/arch/board-mx27ads.h>
#endif
#ifdef CONFIG_MACH_PCM038
#include <asm/arch/board-pcm038.h>
#endif
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =MXC_LL_UART_PADDR @ physical
ldrne \rx, =MXC_LL_UART_VADDR @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x40] @ TXDATA
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #0x98] @ SR2
tst \rd, #1 << 3 @ TXDC
beq 1002b @ wait until transmit done
.endm

42
include/asm-arm/arch-mxc/gpio.h Normal file
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@@ -0,0 +1,42 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_GPIO_H__
#define __ASM_ARCH_MXC_GPIO_H__
#include <asm/hardware.h>
#include <asm-generic/gpio.h>
/* use gpiolib dispatchers */
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio))
#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES)
struct mxc_gpio_port {
void __iomem *base;
int irq;
int virtual_irq_start;
struct gpio_chip chip;
};
int mxc_gpio_init(struct mxc_gpio_port*, int);
#endif

38
include/asm-arm/arch-mxc/hardware.h
View File

@@ -1,11 +1,20 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
@@ -17,15 +26,12 @@
# include <asm/arch/mx31.h>
#endif
#include <asm/arch/mxc.h>
/*
* ---------------------------------------------------------------------------
* Board specific defines
* ---------------------------------------------------------------------------
*/
#ifdef CONFIG_MACH_MX31ADS
# include <asm/arch/board-mx31ads.h>
#ifdef CONFIG_ARCH_MX2
# ifdef CONFIG_MACH_MX27
# include <asm/arch/mx27.h>
# endif
#endif
#include <asm/arch/mxc.h>
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

77
include/asm-arm/arch-mxc/iim.h Normal file
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@@ -0,0 +1,77 @@
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_IIM_H__
#define __ASM_ARCH_MXC_IIM_H__
/* Register offsets */
#define MXC_IIMSTAT 0x0000
#define MXC_IIMSTATM 0x0004
#define MXC_IIMERR 0x0008
#define MXC_IIMEMASK 0x000C
#define MXC_IIMFCTL 0x0010
#define MXC_IIMUA 0x0014
#define MXC_IIMLA 0x0018
#define MXC_IIMSDAT 0x001C
#define MXC_IIMPREV 0x0020
#define MXC_IIMSREV 0x0024
#define MXC_IIMPRG_P 0x0028
#define MXC_IIMSCS0 0x002C
#define MXC_IIMSCS1 0x0030
#define MXC_IIMSCS2 0x0034
#define MXC_IIMSCS3 0x0038
#define MXC_IIMFBAC0 0x0800
#define MXC_IIMJAC 0x0804
#define MXC_IIMHWV1 0x0808
#define MXC_IIMHWV2 0x080C
#define MXC_IIMHAB0 0x0810
#define MXC_IIMHAB1 0x0814
/* Definitions for i.MX27 TO2 */
#define MXC_IIMMAC 0x0814
#define MXC_IIMPREV_FUSE 0x0818
#define MXC_IIMSREV_FUSE 0x081C
#define MXC_IIMSJC_CHALL_0 0x0820
#define MXC_IIMSJC_CHALL_7 0x083C
#define MXC_IIMFB0UC17 0x0840
#define MXC_IIMFB0UC255 0x0BFC
#define MXC_IIMFBAC1 0x0C00
/* Definitions for i.MX27 TO2 */
#define MXC_IIMSUID 0x0C04
#define MXC_IIMKEY0 0x0C04
#define MXC_IIMKEY20 0x0C54
#define MXC_IIMSJC_RESP_0 0x0C58
#define MXC_IIMSJC_RESP_7 0x0C74
#define MXC_IIMFB1UC30 0x0C78
#define MXC_IIMFB1UC255 0x0FFC
/* Bit definitions */
#define MXC_IIMHWV1_WLOCK (0x1 << 7)
#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6)
#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5)
#define MXC_IIMHWV1_BOOT_INT (0x1 << 4)
#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3)
#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2)
#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1)
#define MXC_IIMHWV2_WLOCK (0x1 << 7)
#define MXC_IIMHWV2_BP_SDMA (0x1 << 6)
#define MXC_IIMHWV2_SCM_DCM (0x1 << 5)
#endif /* __ASM_ARCH_MXC_IIM_H__ */

32
include/asm-arm/arch-mxc/imx-uart.h Normal file
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@@ -0,0 +1,32 @@
/*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef ASMARM_ARCH_UART_H
#define ASMARM_ARCH_UART_H
#define IMXUART_HAVE_RTSCTS (1<<0)
struct imxuart_platform_data {
int (*init)(struct platform_device *pdev);
int (*exit)(struct platform_device *pdev);
unsigned int flags;
};
int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
#endif

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