From fbf76e4bc278d7cd447af6a6fddc4f1a4ac0d45f Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:53 -0700 Subject: [PATCH 1/8] dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC Document vendor prefix for Tenstorrent in DT bindings. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index f1d1882009ba..21921be22207 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1610,6 +1610,8 @@ patternProperties: description: Tempo Semiconductor "^tenda,.*": description: Shenzhen Tenda Technology Co., Ltd. + "^tenstorrent,.*": + description: Tenstorrent AI ULC "^terasic,.*": description: Terasic Inc. "^tesla,.*": From 4de28f1edcfbd22ade0a69b97a10a43d09f5d4b4 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:54 -0700 Subject: [PATCH 2/8] dt-bindings: riscv: Add Tenstorrent Blackhole compatible Add compatibles for the Tenstorrent Blackhole SoC PCIe card. Reviewed-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- .../bindings/riscv/tenstorrent.yaml | 28 +++++++++++++++++++ MAINTAINERS | 8 ++++++ 2 files changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/tenstorrent.yaml diff --git a/Documentation/devicetree/bindings/riscv/tenstorrent.yaml b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml new file mode 100644 index 000000000000..e15359b2aab6 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/tenstorrent.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/tenstorrent.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tenstorrent SoC-based boards + +maintainers: + - Drew Fustini + - Joel Stanley + +description: + Tenstorrent SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Tenstorrent Blackhole PCIe card + items: + - const: tenstorrent,blackhole-card + - const: tenstorrent,blackhole + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 46126ce2f968..5a29636b2df0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22158,6 +22158,14 @@ F: arch/riscv/boot/dts/spacemit/ N: spacemit K: spacemit +RISC-V TENSTORRENT SoC SUPPORT +M: Drew Fustini +M: Joel Stanley +L: linux-riscv@lists.infradead.org +S: Maintained +T: git https://github.com/tenstorrent/linux.git +F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml + RISC-V THEAD SoC SUPPORT M: Drew Fustini M: Guo Ren From 571e42a1197c432d6bb78e1feb9586b4feb0a981 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:55 -0700 Subject: [PATCH 3/8] dt-bindings: riscv: cpus: Add SiFive X280 compatible Document compatible for the SiFive X280 RISC-V core. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 153d0dac57fb..afb8533f6a08 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -70,6 +70,7 @@ properties: - enum: - sifive,e51 - sifive,u54-mc + - sifive,x280 - const: sifive,rocket0 - const: riscv - const: riscv # Simulator only From b5951b25d72c9c790575fef5656ddde6a9277bd3 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:56 -0700 Subject: [PATCH 4/8] dt-bindings: timers: Add Tenstorrent Blackhole compatible Document clint compatible for the Tenstorrent Blackhole SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index d85a1a088b35..0d3b8dc362ba 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -36,6 +36,7 @@ properties: - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 + - tenstorrent,blackhole-clint # Tenstorrent Blackhole - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} From d6133f79da9f2276e4acdb60864b3a3c5f3ab60d Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:57 -0700 Subject: [PATCH 5/8] dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible Document compatible for the PLIC in the Tenstorrent Blackhole SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f683d696909b..9886b7d73d3c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -64,6 +64,7 @@ properties: - spacemit,k1-plic - starfive,jh7100-plic - starfive,jh7110-plic + - tenstorrent,blackhole-plic - const: sifive,plic-1.0.0 - items: - enum: From 8e88602e99a7523270be29fecc722605aaf1ba03 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:58 -0700 Subject: [PATCH 6/8] riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards Add device tree source describing the Tenstorrent Blackhole SoC and the Blackhole P100 and P150 PCIe cards. There are no differences between the P100 and P150 cards from the perspective of an OS kernel like Linux running on the X280 cores. There is a virtual UART implemented in OpenSBI firmware that allows a console program on the PCIe host to communicate through shared memory with Linux running on the Blackhole card. CONFIG_HVC_RISCV_SBI needs to be enabled. The boot script on the host adds 'console=hvc0' so that the full boot output appears in the console program on the host. Link: https://github.com/tenstorrent/opensbi/ Link: https://github.com/tenstorrent/tt-bh-linux Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/tenstorrent/Makefile | 2 + .../boot/dts/tenstorrent/blackhole-card.dts | 14 +++ .../riscv/boot/dts/tenstorrent/blackhole.dtsi | 108 ++++++++++++++++++ 5 files changed, 126 insertions(+) create mode 100644 arch/riscv/boot/dts/tenstorrent/Makefile create mode 100644 arch/riscv/boot/dts/tenstorrent/blackhole-card.dts create mode 100644 arch/riscv/boot/dts/tenstorrent/blackhole.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 5a29636b2df0..b49471cc3139 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22165,6 +22165,7 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/tenstorrent/linux.git F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml +F: arch/riscv/boot/dts/tenstorrent/ RISC-V THEAD SoC SUPPORT M: Drew Fustini diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 3763d199c70a..cf179c6253ce 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -9,4 +9,5 @@ subdir-y += sifive subdir-y += sophgo subdir-y += spacemit subdir-y += starfive +subdir-y += tenstorrent subdir-y += thead diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile new file mode 100644 index 000000000000..2c81faaba462 --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts b/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts new file mode 100644 index 000000000000..f53667ce73a9 --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-card.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include "blackhole.dtsi" + +/ { + model = "Tenstorrent Blackhole"; + compatible = "tenstorrent,blackhole-card", "tenstorrent,blackhole"; + + memory@400030000000 { + device_type = "memory"; + reg = <0x4000 0x30000000 0x1 0x00000000>; + }; +}; diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi new file mode 100644 index 000000000000..6408810d8d80 --- /dev/null +++ b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright 2025 Tenstorrent AI ULC +/dts-v1/; + +/ { + compatible = "tenstorrent,blackhole"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <50000000>; + + cpu@0 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <0>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@1 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <1>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@2 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <2>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@3 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <3>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + clint0: timer@2000000 { + compatible = "tenstorrent,blackhole-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>, + <&cpu1_intc 0x3>, <&cpu1_intc 0x7>, + <&cpu2_intc 0x3>, <&cpu2_intc 0x7>, + <&cpu3_intc 0x3>, <&cpu3_intc 0x7>; + }; + + plic0: interrupt-controller@c000000 { + compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x0c000000 0x0 0x04000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <128>; + }; + }; +}; From 16eb4e02a631b06a12b3170c8ec3f64a03b9d3ce Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:11:59 -0700 Subject: [PATCH 7/8] riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs Add Kconfig option ARCH_TENSTORRENT to enable support for SoCs like the Blackhole. Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- arch/riscv/Kconfig.socs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 848e7149e443..0b4d408aebfa 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -63,6 +63,14 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_TENSTORRENT + bool "Tenstorrent SoCs" + help + This enables support for Tenstorrent SoC platforms. + Current support is for Blackhole P100 and P150 PCIe cards. + The Blackhole SoC contains four RISC-V CPU tiles each + consisting of 4x SiFive X280 cores. + config ARCH_THEAD bool "T-HEAD RISC-V SoCs" depends on MMU && !XIP_KERNEL From a71e6e8eea8ae2d624f097911f43357bba06d2a5 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 13 Oct 2025 20:12:00 -0700 Subject: [PATCH 8/8] riscv: defconfig: Enable Tenstorrent SoCs Enable support for Tenstorrent SoCs in the default configuration. Reviewed-by: Joel Stanley Signed-off-by: Drew Fustini --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc2725cbca18..95d5230c0027 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -29,6 +29,7 @@ CONFIG_ARCH_SOPHGO=y CONFIG_ARCH_SPACEMIT=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_TENSTORRENT=y CONFIG_ARCH_THEAD=y CONFIG_ARCH_VIRT=y CONFIG_ARCH_CANAAN=y