[SCSI] qla2xxx: Add ISP24xx definitions.
Add ISP24xx definitions. Add requisite structure definitions and #define's for ISP24xx support. Also drop volatile modifiers from device_reg_* register layouts as the members are never really accessed, only their offsets within the layout are used during reads and writes. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This commit is contained in:
Andrew Vasquez
committed by
James Bottomley
James Bottomley
parent
ac96202ba0
commit
3d71644cf9
@@ -75,9 +75,28 @@
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#define IS_QLA6322(ha) 0
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#endif
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#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
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#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
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#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
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#else
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#define IS_QLA2422(ha) 0
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#define IS_QLA2432(ha) 0
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#endif
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#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
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#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
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#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
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#else
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#define IS_QLA2512(ha) 0
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#define IS_QLA2522(ha) 0
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#endif
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#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
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IS_QLA6312(ha) || IS_QLA6322(ha))
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#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
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#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
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/*
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* Only non-ISP2[12]00 have extended addressing support in the firmware.
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*/
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@@ -191,10 +210,18 @@
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#define MANAGEMENT_SERVER 0xfe
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#define BROADCAST 0xff
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#define RESERVED_LOOP_ID(x) ((x > LAST_LOCAL_LOOP_ID && \
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x < SNS_FIRST_LOOP_ID) || \
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x == MANAGEMENT_SERVER || \
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x == BROADCAST)
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/*
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* There is no correspondence between an N-PORT id and an AL_PA. Therefore the
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* valid range of an N-PORT id is 0 through 0x7ef.
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*/
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#define NPH_LAST_HANDLE 0x7ef
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#define NPH_SNS 0x7fc /* FFFFFC */
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#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
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#define NPH_F_PORT 0x7fe /* FFFFFE */
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#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
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#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
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#include "qla_fw.h"
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/*
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* Timeout timer counts in seconds
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@@ -211,6 +238,7 @@
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#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
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#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
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#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
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#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
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#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
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#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
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@@ -279,24 +307,24 @@ typedef struct srb {
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/*
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* ISP I/O Register Set structure definitions.
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*/
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typedef volatile struct {
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volatile uint16_t flash_address; /* Flash BIOS address */
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volatile uint16_t flash_data; /* Flash BIOS data */
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struct device_reg_2xxx {
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uint16_t flash_address; /* Flash BIOS address */
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uint16_t flash_data; /* Flash BIOS data */
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uint16_t unused_1[1]; /* Gap */
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volatile uint16_t ctrl_status; /* Control/Status */
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uint16_t ctrl_status; /* Control/Status */
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#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
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#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
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#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
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volatile uint16_t ictrl; /* Interrupt control */
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uint16_t ictrl; /* Interrupt control */
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#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
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#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
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volatile uint16_t istatus; /* Interrupt status */
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uint16_t istatus; /* Interrupt status */
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#define ISR_RISC_INT BIT_3 /* RISC interrupt */
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volatile uint16_t semaphore; /* Semaphore */
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volatile uint16_t nvram; /* NVRAM register. */
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uint16_t semaphore; /* Semaphore */
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uint16_t nvram; /* NVRAM register. */
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#define NVR_DESELECT 0
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#define NVR_BUSY BIT_15
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#define NVR_WRT_ENABLE BIT_14 /* Write enable */
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@@ -308,78 +336,78 @@ typedef volatile struct {
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union {
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struct {
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volatile uint16_t mailbox0;
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volatile uint16_t mailbox1;
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volatile uint16_t mailbox2;
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volatile uint16_t mailbox3;
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volatile uint16_t mailbox4;
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volatile uint16_t mailbox5;
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volatile uint16_t mailbox6;
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volatile uint16_t mailbox7;
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uint16_t unused_2[59]; /* Gap */
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uint16_t mailbox0;
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uint16_t mailbox1;
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uint16_t mailbox2;
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uint16_t mailbox3;
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uint16_t mailbox4;
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uint16_t mailbox5;
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uint16_t mailbox6;
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uint16_t mailbox7;
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uint16_t unused_2[59]; /* Gap */
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} __attribute__((packed)) isp2100;
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struct {
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/* Request Queue */
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volatile uint16_t req_q_in; /* In-Pointer */
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volatile uint16_t req_q_out; /* Out-Pointer */
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/* Response Queue */
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volatile uint16_t rsp_q_in; /* In-Pointer */
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volatile uint16_t rsp_q_out; /* Out-Pointer */
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/* Request Queue */
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uint16_t req_q_in; /* In-Pointer */
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uint16_t req_q_out; /* Out-Pointer */
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/* Response Queue */
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uint16_t rsp_q_in; /* In-Pointer */
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uint16_t rsp_q_out; /* Out-Pointer */
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/* RISC to Host Status */
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volatile uint32_t host_status;
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uint32_t host_status;
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#define HSR_RISC_INT BIT_15 /* RISC interrupt */
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#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
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/* Host to Host Semaphore */
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volatile uint16_t host_semaphore;
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uint16_t unused_3[17]; /* Gap */
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volatile uint16_t mailbox0;
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volatile uint16_t mailbox1;
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volatile uint16_t mailbox2;
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volatile uint16_t mailbox3;
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volatile uint16_t mailbox4;
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volatile uint16_t mailbox5;
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volatile uint16_t mailbox6;
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volatile uint16_t mailbox7;
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volatile uint16_t mailbox8;
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volatile uint16_t mailbox9;
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volatile uint16_t mailbox10;
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volatile uint16_t mailbox11;
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volatile uint16_t mailbox12;
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volatile uint16_t mailbox13;
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volatile uint16_t mailbox14;
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volatile uint16_t mailbox15;
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volatile uint16_t mailbox16;
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volatile uint16_t mailbox17;
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volatile uint16_t mailbox18;
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volatile uint16_t mailbox19;
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volatile uint16_t mailbox20;
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volatile uint16_t mailbox21;
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volatile uint16_t mailbox22;
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volatile uint16_t mailbox23;
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volatile uint16_t mailbox24;
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volatile uint16_t mailbox25;
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volatile uint16_t mailbox26;
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volatile uint16_t mailbox27;
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volatile uint16_t mailbox28;
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volatile uint16_t mailbox29;
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volatile uint16_t mailbox30;
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volatile uint16_t mailbox31;
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volatile uint16_t fb_cmd;
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uint16_t unused_4[10]; /* Gap */
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uint16_t host_semaphore;
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uint16_t unused_3[17]; /* Gap */
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uint16_t mailbox0;
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uint16_t mailbox1;
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uint16_t mailbox2;
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uint16_t mailbox3;
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uint16_t mailbox4;
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uint16_t mailbox5;
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uint16_t mailbox6;
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uint16_t mailbox7;
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uint16_t mailbox8;
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uint16_t mailbox9;
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uint16_t mailbox10;
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uint16_t mailbox11;
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uint16_t mailbox12;
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uint16_t mailbox13;
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uint16_t mailbox14;
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uint16_t mailbox15;
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uint16_t mailbox16;
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uint16_t mailbox17;
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uint16_t mailbox18;
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uint16_t mailbox19;
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uint16_t mailbox20;
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uint16_t mailbox21;
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uint16_t mailbox22;
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uint16_t mailbox23;
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uint16_t mailbox24;
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uint16_t mailbox25;
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uint16_t mailbox26;
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uint16_t mailbox27;
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uint16_t mailbox28;
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uint16_t mailbox29;
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uint16_t mailbox30;
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uint16_t mailbox31;
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uint16_t fb_cmd;
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uint16_t unused_4[10]; /* Gap */
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} __attribute__((packed)) isp2300;
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} u;
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volatile uint16_t fpm_diag_config;
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uint16_t fpm_diag_config;
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uint16_t unused_5[0x6]; /* Gap */
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volatile uint16_t pcr; /* Processor Control Register. */
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uint16_t pcr; /* Processor Control Register. */
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uint16_t unused_6[0x5]; /* Gap */
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volatile uint16_t mctr; /* Memory Configuration and Timing. */
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uint16_t mctr; /* Memory Configuration and Timing. */
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uint16_t unused_7[0x3]; /* Gap */
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volatile uint16_t fb_cmd_2100; /* Unused on 23XX */
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uint16_t fb_cmd_2100; /* Unused on 23XX */
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uint16_t unused_8[0x3]; /* Gap */
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volatile uint16_t hccr; /* Host command & control register. */
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uint16_t hccr; /* Host command & control register. */
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#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
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#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
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/* HCCR commands */
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@@ -393,8 +421,8 @@ typedef volatile struct {
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#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
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uint16_t unused_9[5]; /* Gap */
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volatile uint16_t gpiod; /* GPIO Data register. */
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volatile uint16_t gpioe; /* GPIO Enable register. */
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uint16_t gpiod; /* GPIO Data register. */
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uint16_t gpioe; /* GPIO Enable register. */
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#define GPIO_LED_MASK 0x00C0
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#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
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#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
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@@ -403,25 +431,32 @@ typedef volatile struct {
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union {
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struct {
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uint16_t unused_10[8]; /* Gap */
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volatile uint16_t mailbox8;
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volatile uint16_t mailbox9;
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volatile uint16_t mailbox10;
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volatile uint16_t mailbox11;
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volatile uint16_t mailbox12;
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volatile uint16_t mailbox13;
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volatile uint16_t mailbox14;
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volatile uint16_t mailbox15;
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volatile uint16_t mailbox16;
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volatile uint16_t mailbox17;
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volatile uint16_t mailbox18;
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volatile uint16_t mailbox19;
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volatile uint16_t mailbox20;
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volatile uint16_t mailbox21;
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volatile uint16_t mailbox22;
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volatile uint16_t mailbox23; /* Also probe reg. */
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uint16_t unused_10[8]; /* Gap */
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uint16_t mailbox8;
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uint16_t mailbox9;
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uint16_t mailbox10;
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uint16_t mailbox11;
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uint16_t mailbox12;
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uint16_t mailbox13;
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uint16_t mailbox14;
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uint16_t mailbox15;
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uint16_t mailbox16;
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uint16_t mailbox17;
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uint16_t mailbox18;
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uint16_t mailbox19;
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uint16_t mailbox20;
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uint16_t mailbox21;
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uint16_t mailbox22;
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uint16_t mailbox23; /* Also probe reg. */
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} __attribute__((packed)) isp2200;
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} u_end;
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};
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typedef struct {
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union {
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struct device_reg_2xxx isp;
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struct device_reg_24xx isp24;
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};
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} device_reg_t;
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#define ISP_REQ_Q_IN(ha, reg) \
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@@ -504,6 +539,8 @@ typedef struct {
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#define MBS_LOOP_ID_USED 0x4008
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#define MBS_ALL_IDS_IN_USE 0x4009
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#define MBS_NOT_LOGGED_IN 0x400A
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#define MBS_LINK_DOWN_ERROR 0x400B
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#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
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/*
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* ISP mailbox asynchronous event status codes
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@@ -555,7 +592,7 @@ typedef struct {
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#define FO1_CTIO_RETRY BIT_3
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#define FO1_DISABLE_LIP_F7_SW BIT_4
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#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
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#define FO1_DISABLE_GPIO6_7 BIT_6
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#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
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#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
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#define FO1_SET_EMPHASIS_SWING BIT_8
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#define FO1_AE_AUTO_BYPASS BIT_9
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@@ -570,6 +607,15 @@ typedef struct {
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#define FO3_ENABLE_EMERG_IOCB BIT_0
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#define FO3_AE_RND_ERROR BIT_1
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/* 24XX additional firmware options */
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#define ADD_FO_COUNT 3
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#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
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#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
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#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
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#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
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/*
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* ISP mailbox commands
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*/
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@@ -638,6 +684,22 @@ typedef struct {
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#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
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#define MBC_LUN_RESET 0x7E /* Send LUN reset */
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/*
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* ISP24xx mailbox commands
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*/
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#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
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#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
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#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
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#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
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#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
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#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
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#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
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#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
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#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
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#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
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#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
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#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
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/* Firmware return data sizes */
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#define FCAL_MAP_SIZE 128
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@@ -867,6 +929,9 @@ typedef struct {
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/*
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* Get Link Status mailbox command return buffer.
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*/
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#define GLSO_SEND_RPS BIT_0
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#define GLSO_USE_DID BIT_3
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typedef struct {
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uint32_t link_fail_cnt;
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uint32_t loss_sync_cnt;
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@@ -1161,7 +1226,6 @@ do { \
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* ISP queue - command entry structure definition.
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*/
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#define COMMAND_TYPE 0x11 /* Command entry */
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#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
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typedef struct {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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@@ -1284,11 +1348,16 @@ typedef struct {
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/*
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* Status entry entry status
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*/
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#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
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#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
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#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
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#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
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#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
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#define RF_BUSY BIT_1 /* Busy */
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#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
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RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
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#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
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RF_INV_E_TYPE)
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/*
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* Status entry SCSI status bit definitions.
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@@ -1503,9 +1572,6 @@ typedef struct {
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port_id_t d_id;
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uint8_t node_name[WWN_SIZE];
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uint8_t port_name[WWN_SIZE];
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uint32_t type;
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#define SW_TYPE_IP BIT_1
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#define SW_TYPE_SCSI BIT_0
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} sw_info_t;
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/*
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@@ -1520,6 +1586,8 @@ typedef struct {
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union {
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cmd_a64_entry_t cmd;
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sts_entry_t rsp;
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struct cmd_type_7 cmd24;
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struct sts_entry_24xx rsp24;
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} p;
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uint8_t inq[INQ_DATA_SIZE];
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} inq_cmd_rsp_t;
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@@ -1555,10 +1623,13 @@ typedef struct {
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union {
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cmd_a64_entry_t cmd;
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sts_entry_t rsp;
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struct cmd_type_7 cmd24;
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struct sts_entry_24xx rsp24;
|
||||
} p;
|
||||
rpt_lun_lst_t list;
|
||||
} rpt_lun_cmd_rsp_t;
|
||||
|
||||
|
||||
/*
|
||||
* Fibre channel port type.
|
||||
*/
|
||||
@@ -1646,6 +1717,7 @@ typedef struct fc_port {
|
||||
#define FCF_FAILOVER_DISABLE BIT_22
|
||||
#define FCF_DSXXX_DEVICE BIT_23
|
||||
#define FCF_AA_EVA_DEVICE BIT_24
|
||||
#define FCF_AA_MSA_DEVICE BIT_25
|
||||
|
||||
/* No loop ID flag. */
|
||||
#define FC_NO_LOOP_ID 0x1000
|
||||
@@ -1917,6 +1989,7 @@ struct qla_board_info {
|
||||
|
||||
char isp_name[8];
|
||||
struct qla_fw_info *fw_info;
|
||||
char *fw_fname;;
|
||||
};
|
||||
|
||||
/* Return data from MBC_GET_ID_LIST call. */
|
||||
@@ -1926,6 +1999,7 @@ struct gid_list_info {
|
||||
uint8_t domain;
|
||||
uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
|
||||
uint16_t loop_id; /* ISP23XX -- 6 bytes. */
|
||||
uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
|
||||
};
|
||||
#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
|
||||
|
||||
@@ -2000,6 +2074,8 @@ typedef struct scsi_qla_host {
|
||||
uint32_t enable_lip_full_login :1;
|
||||
uint32_t enable_target_reset :1;
|
||||
uint32_t enable_led_scheme :1;
|
||||
uint32_t msi_enabled :1;
|
||||
uint32_t msix_enabled :1;
|
||||
} flags;
|
||||
|
||||
atomic_t loop_state;
|
||||
@@ -2036,6 +2112,7 @@ typedef struct scsi_qla_host {
|
||||
#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
|
||||
#define IOCTL_ERROR_RECOVERY 23
|
||||
#define LOOP_RESET_NEEDED 24
|
||||
#define BEACON_BLINK_NEEDED 25
|
||||
|
||||
uint32_t device_flags;
|
||||
#define DFLG_LOCAL_DEVICES BIT_0
|
||||
@@ -2119,6 +2196,7 @@ typedef struct scsi_qla_host {
|
||||
uint8_t serial2;
|
||||
|
||||
/* NVRAM configuration data */
|
||||
uint16_t nvram_size;
|
||||
uint16_t nvram_base;
|
||||
|
||||
uint16_t loop_reset_delay;
|
||||
@@ -2179,7 +2257,8 @@ typedef struct scsi_qla_host {
|
||||
struct dma_pool *s_dma_pool;
|
||||
|
||||
dma_addr_t init_cb_dma;
|
||||
init_cb_t *init_cb;
|
||||
init_cb_t *init_cb;
|
||||
int init_cb_size;
|
||||
|
||||
dma_addr_t iodesc_pd_dma;
|
||||
port_database_t *iodesc_pd;
|
||||
@@ -2220,6 +2299,7 @@ typedef struct scsi_qla_host {
|
||||
|
||||
uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
|
||||
uint8_t fw_seriallink_options[4];
|
||||
uint16_t fw_seriallink_options24[4];
|
||||
|
||||
/* Firmware dump information. */
|
||||
void *fw_dump;
|
||||
@@ -2228,8 +2308,12 @@ typedef struct scsi_qla_host {
|
||||
char *fw_dump_buffer;
|
||||
int fw_dump_buffer_len;
|
||||
|
||||
int fw_dumped;
|
||||
void *fw_dump24;
|
||||
int fw_dump24_len;
|
||||
|
||||
uint8_t host_str[16];
|
||||
uint16_t pci_attr;
|
||||
uint32_t pci_attr;
|
||||
|
||||
uint16_t product_id[4];
|
||||
|
||||
@@ -2237,8 +2321,8 @@ typedef struct scsi_qla_host {
|
||||
#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
|
||||
char *model_desc;
|
||||
|
||||
uint8_t node_name[WWN_SIZE];
|
||||
uint8_t nvram_version;
|
||||
uint8_t *node_name;
|
||||
uint8_t *port_name;
|
||||
uint32_t isp_abort_cnt;
|
||||
|
||||
/* Needed for BEACON */
|
||||
|
||||
Reference in New Issue
Block a user