[SCSI] 3ware 9000: Add support for 9550SX controllers
Signed-off-by: Adam Radford <linuxraid@amcc.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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committed by
James Bottomley
parent
68ce1eb540
commit
49bfd8db4a
@@ -267,7 +267,6 @@ static twa_message_type twa_error_table[] = {
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#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
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#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
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#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
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#define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008
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/* Status register bit definitions */
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#define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
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@@ -285,9 +284,8 @@ static twa_message_type twa_error_table[] = {
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#define TW_STATUS_MICROCONTROLLER_READY 0x00002000
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#define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
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#define TW_STATUS_EXPECTED_BITS 0x00002000
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#define TW_STATUS_UNEXPECTED_BITS 0x00F00008
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#define TW_STATUS_SBUF_WRITE_ERROR 0x00000008
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#define TW_STATUS_VALID_INTERRUPT 0x00DF0008
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#define TW_STATUS_UNEXPECTED_BITS 0x00F00000
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#define TW_STATUS_VALID_INTERRUPT 0x00DF0000
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/* RESPONSE QUEUE BIT DEFINITIONS */
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#define TW_RESPONSE_ID_MASK 0x00000FF0
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@@ -324,9 +322,9 @@ static twa_message_type twa_error_table[] = {
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/* Compatibility defines */
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#define TW_9000_ARCH_ID 0x5
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#define TW_CURRENT_DRIVER_SRL 28
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#define TW_CURRENT_DRIVER_BUILD 9
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#define TW_CURRENT_DRIVER_BRANCH 4
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#define TW_CURRENT_DRIVER_SRL 30
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#define TW_CURRENT_DRIVER_BUILD 80
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#define TW_CURRENT_DRIVER_BRANCH 0
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/* Phase defines */
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#define TW_PHASE_INITIAL 0
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@@ -334,6 +332,7 @@ static twa_message_type twa_error_table[] = {
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#define TW_PHASE_SGLIST 2
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/* Misc defines */
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#define TW_9550SX_DRAIN_COMPLETED 0xFFFF
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#define TW_SECTOR_SIZE 512
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#define TW_ALIGNMENT_9000 4 /* 4 bytes */
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#define TW_ALIGNMENT_9000_SGL 0x3
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@@ -417,6 +416,9 @@ static twa_message_type twa_error_table[] = {
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#ifndef PCI_DEVICE_ID_3WARE_9000
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#define PCI_DEVICE_ID_3WARE_9000 0x1002
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#endif
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#ifndef PCI_DEVICE_ID_3WARE_9550SX
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#define PCI_DEVICE_ID_3WARE_9550SX 0x1003
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#endif
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/* Bitmask macros to eliminate bitfields */
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@@ -443,6 +445,7 @@ static twa_message_type twa_error_table[] = {
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#define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4)
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#define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8))
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#define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC)
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#define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30)
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#define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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#define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
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