From 75b310b770d631bea4bd00f9b8d3a8c902342fe2 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 12 Feb 2018 18:13:20 +1030 Subject: [PATCH 01/13] ARM: dts: aspeed: Add IPMI BT node The IPMI BT device part of the LPC interface and is used for communication with the host processor. Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 7 +++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index b0d8431a3700..8b18176dca59 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -247,6 +247,13 @@ compatible = "aspeed,ast2400-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + + ibt: ibt@c0 { + compatible = "aspeed,ast2400-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 40de3b66c33f..18185484a224 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -298,6 +298,13 @@ compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + + ibt: ibt@c0 { + compatible = "aspeed,ast2500-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <8>; + status = "disabled"; + }; }; }; From 347328110eabec0b76a9b76d4a43fbae62930bc0 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 12 Feb 2018 18:13:21 +1030 Subject: [PATCH 02/13] ARM: dts: aspeed: Enable IPMI BT node on OpenPower machines These BMC systems require this device to communicate with the host. Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 4 ++++ arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 4 ++++ arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 4 ++++ arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index 4379d09a261f..5115247e5e59 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -111,3 +111,7 @@ &vuart { status = "okay"; }; + +&ibt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 623b6ab42021..d41be52c2393 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -257,3 +257,7 @@ aspeed,fan-tach-ch = /bits/ 8 <0x0e>; }; }; + +&ibt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 5f9049d2c4c3..7056231cbee6 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -546,3 +546,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdtrst1_default>; }; + +&ibt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index c881484a85cf..ebe726a0d311 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -424,3 +424,7 @@ aspeed,fan-tach-ch = /bits/ 8 <0x03>; }; }; + +&ibt { + status = "okay"; +}; From 542d2f4588ae651c4c1c59a5ca9ac731fe06c881 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 12 Feb 2018 18:13:22 +1030 Subject: [PATCH 03/13] ARM: dts: aspeed-g5: Update LPC node This addresses some differences between the G5 and G4 LPC nodes that make them hard to compare. There is no functional change. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 18185484a224..e0b6803f6845 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -264,7 +264,7 @@ #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x1e789000 0x1000>; + ranges = <0x0 0x1e789000 0x1000>; lpc_bmc: lpc-bmc@0 { compatible = "aspeed,ast2500-lpc-bmc"; @@ -274,12 +274,11 @@ lpc_host: lpc-host@80 { compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; reg = <0x80 0x1e0>; + reg-io-width = <4>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x80 0x1e0>; - - reg-io-width = <4>; + ranges = <0x0 0x80 0x1e0>; lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2500-lpc-ctrl"; From 7674bf96b82e22950c00151d4a9f45e0bc988698 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 12 Feb 2018 18:13:23 +1030 Subject: [PATCH 04/13] ARM: dts: aspeed: Add LPC clock phandles The LPC device uses LCLK. Tested-by: Lei YU Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 1 + arch/arm/boot/dts/aspeed-g5.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 8b18176dca59..48c28a71ae7e 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -233,6 +233,7 @@ lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2400-lpc-ctrl"; reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index e0b6803f6845..8eac57c33880 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -283,6 +283,7 @@ lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2500-lpc-ctrl"; reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; }; From 65a33f05384274de27754b7e230f8b314c231f06 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 12 Feb 2018 18:13:24 +1030 Subject: [PATCH 05/13] ARM: dts: palmetto: Add LEDs and GPIO keys These describe the front panel LEDs that are present on a Palmetto chassis, and the checkstop GPIO that comes from the Power8 CPU to indicate a host error. Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index 5115247e5e59..2a4a355a779d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -2,6 +2,7 @@ /dts-v1/; #include "aspeed-g4.dtsi" +#include / { model = "Palmetto BMC"; @@ -26,6 +27,32 @@ reg = <0x5f000000 0x01000000>; /* 16M */ }; }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>; + }; + + power { + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + }; + + identify { + gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; &fmc { From f4c37354565d347575254d3775ae1aaccb05dbbe Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 12 Feb 2018 18:13:25 +1030 Subject: [PATCH 06/13] ARM: dts: aspeed: Add Palmetto GPIO hogs These hogs are for parts of the system that need to be in this state, but do not yet have a driver associated with them but they must be configured in order to successfully boot the host. There are also some pinmux hogs, where the default mode of the IP block is configured. Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 157 ++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index 2a4a355a779d..bbddfe1d1cc8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -74,6 +74,14 @@ }; }; +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default + + &pinctrl_vgahs_default &pinctrl_vgavs_default + &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; +}; + &uart5 { status = "okay"; }; @@ -142,3 +150,152 @@ &ibt { status = "okay"; }; + +&gpio { + pin_func_mode0 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode0"; + }; + + pin_func_mode1 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode1"; + }; + + pin_func_mode2 { + gpio-hog; + gpios = ; + output-low; + line-name = "func_mode2"; + }; + + pin_gpio_a0 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_FAN_RESERVED_N"; + }; + + pin_gpio_a1 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_WDT_N"; + }; + + pin_gpio_b1 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_BOOT_MODE"; + }; + + pin_gpio_b2 { + gpio-hog; + gpios = ; + output-high; + line-name = "APSS_RESET_N"; + }; + + pin_gpio_b7 { + gpio-hog; + gpios = ; + output-high; + line-name = "SPIVID_STBY_RESET_N"; + }; + + pin_gpio_d1 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_POWER_UP"; + }; + + pin_gpio_f1 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_BATTERY_TEST"; + }; + + pin_gpio_f4 { + gpio-hog; + gpios = ; + input; + line-name = "AST_HW_FAULT_N"; + }; + + pin_gpio_f5 { + gpio-hog; + gpios = ; + input; + line-name = "AST_SYS_FAULT_N"; + }; + + pin_gpio_f7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_FULL_SPEED_N"; + }; + + pin_gpio_g3 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_FAN_ERROR_N"; + }; + + pin_gpio_g4 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_WDT_RST1_P"; + }; + + pin_gpio_g5 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_WDT_RST2_P"; + }; + + pin_gpio_h0 { + gpio-hog; + gpios = ; + input; + line-name = "PE_SLOT_TEST_EN_N"; + }; + + pin_gpio_h1 { + gpio-hog; + gpios = ; + input; + line-name = "BMC_RTCRST_N"; + }; + + pin_gpio_h2 { + gpio-hog; + gpios = ; + output-high; + line-name = "SYS_PWROK_BMC"; + }; + + pin_gpio_h6 { + gpio-hog; + gpios = ; + output-high; + line-name = "SCM1_FSI0_DATA_EN"; + }; + + pin_gpio_h7 { + gpio-hog; + gpios = ; + output-high; + line-name = "BMC_TPM_INT_N"; + }; +}; From fd2de0a7317875fecec18b6755b1b171f17490c0 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 19 Feb 2018 18:05:40 +1030 Subject: [PATCH 07/13] ARM: dts: aspeed: Add LPC reset controller node On both the ast2400 and ast2500 SoCs, the LPC reset controller is required to bring the UARTs out of reset without waiting for the LPC reset to be deasserted. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 10 ++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 48c28a71ae7e..36ae23aa3b48 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -162,6 +162,7 @@ reg-shift = <2>; interrupts = <9>; clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; no-loopback-test; status = "disabled"; }; @@ -249,6 +250,12 @@ reg = <0x20 0x24 0x48 0x8>; }; + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2400-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + ibt: ibt@c0 { compatible = "aspeed,ast2400-ibt-bmc"; reg = <0xc0 0x18>; @@ -264,6 +271,7 @@ reg-shift = <2>; interrupts = <32>; clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; no-loopback-test; status = "disabled"; }; @@ -274,6 +282,7 @@ reg-shift = <2>; interrupts = <33>; clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; no-loopback-test; status = "disabled"; }; @@ -284,6 +293,7 @@ reg-shift = <2>; interrupts = <34>; clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; no-loopback-test; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 8eac57c33880..17ee0fa33a14 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -205,6 +205,7 @@ reg-shift = <2>; interrupts = <9>; clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; no-loopback-test; status = "disabled"; }; @@ -299,6 +300,12 @@ reg = <0x20 0x24 0x48 0x8>; }; + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + ibt: ibt@c0 { compatible = "aspeed,ast2500-ibt-bmc"; reg = <0xc0 0x18>; @@ -314,6 +321,7 @@ reg-shift = <2>; interrupts = <32>; clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; no-loopback-test; status = "disabled"; }; @@ -324,6 +332,7 @@ reg-shift = <2>; interrupts = <33>; clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; no-loopback-test; status = "disabled"; }; @@ -334,6 +343,7 @@ reg-shift = <2>; interrupts = <34>; clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; no-loopback-test; status = "disabled"; }; From 3b47622a36825e0a107222f76408dff46354342f Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 22 Feb 2018 14:32:39 +1030 Subject: [PATCH 08/13] ARM: dts: palmetto: Enable rear UART The Palmetto BMC has a UART connected to a RS-232 transceiver designed to be used as a serial console for the host processor. It appears as a D-sub connector on the back of the chassis. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index bbddfe1d1cc8..b7d3d1825b93 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -82,6 +82,21 @@ &pinctrl_ddcclk_default &pinctrl_ddcdat_default>; }; +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + &uart5 { status = "okay"; }; From 720ed06c0906212cbd585cf80602035d576f207d Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 7 Nov 2017 18:00:32 +1030 Subject: [PATCH 09/13] ARM: dts: palmetto: Request mux as per strapping configuration Prevents the error: aspeed-smc 1e630000.spi: Error applying setting, reverse things back The pinmux driver is only capable of modifying selected strapping bits that make sense to change at runtime. The SPI strapping is not currently defined modifiable, so "request" the mux as per how the board is physically strapped. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index b7d3d1825b93..c7084a819dc6 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -67,6 +67,9 @@ &spi { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1debug_default>; + flash@0 { status = "okay"; m25p,fast-read; From 9739ae8459831aa97ce67a1208397ea56d81826e Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 18 Jan 2018 14:10:25 -0600 Subject: [PATCH 10/13] ARM: dts: romulus: Remove MAX31785 device Romulus uses ASPEED's fan tach instead of max31785: * Pass1's max31785 is always reset by CPLD * Pass2's max31785 is not connected Signed-off-by: Lei YU Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index d41be52c2393..676739d02ca0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -183,11 +183,6 @@ &i2c12 { status = "okay"; - - max31785@52 { - compatible = "maxim,max31785"; - reg = <0x52>; - }; }; &gpio { From 00569f7ec490a15456122379f7686a0d659a3601 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Thu, 28 Dec 2017 16:38:06 +0800 Subject: [PATCH 11/13] ARM: dts: aspeed: romulus: hog GPIOS7 GPIOS7 shall be pulled low for CPLD to continue the power up sequence. With this hogged as pull-low, the CPLD workaround can be removed in OpenBMC. Signed-off-by: Lei YU Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 676739d02ca0..558b1c70dfc5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -198,6 +198,12 @@ output-low; line-name = "nic_func_mode1"; }; + seq_cont { + gpio-hog; + gpios = ; + output-low; + line-name = "seq_cont"; + }; }; &vuart { From 0765a1d2d3737ac111da93115908cbcbd284034e Mon Sep 17 00:00:00 2001 From: Lei YU Date: Wed, 17 Jan 2018 13:56:56 +0800 Subject: [PATCH 12/13] ARM: dts: aspeed: romulus: Add w83773g temp sensor Signed-off-by: Lei YU Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 558b1c70dfc5..51bc6a2e9dd5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -183,6 +183,11 @@ &i2c12 { status = "okay"; + + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; }; &gpio { From 3719a1b130566cf91c3b3ec4707e1ed61bff6d54 Mon Sep 17 00:00:00 2001 From: Ken Chen Date: Wed, 21 Feb 2018 15:17:26 +0800 Subject: [PATCH 13/13] ARM: dts: aspeed: Add Qualcomm Centriq 2400 REP BMC The Qualcomm Centriq 2400 REP (Reference Evaluation Platform) is an aarch64 Armv8 server platform with an ast2520 BMC. Signed-off-by: Ken Chen Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../dts/aspeed-bmc-arm-centriq2400-rep.dts | 225 ++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ade7a38543dc..06838cd69ac5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1129,6 +1129,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ + aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ aspeed-bmc-opp-witherspoon.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts new file mode 100644 index 000000000000..df1227613d48 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Qualcomm Centriq 2400 REP AST2520"; + compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; + + leds { + compatible = "gpio-leds"; + + uid_led { + label = "UID_LED"; + gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + }; + + ras_error_led { + label = "RAS_ERROR_LED"; + gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + }; + + system_fault { + label = "System_fault"; + gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2ck_default + &pinctrl_spi2miso_default + &pinctrl_spi2mosi_default + &pinctrl_spi2cs0_default>; +}; + +&uart3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; + current-speed = <115200>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp421@1e { + compatible = "ti,tmp421"; + reg = <0x1e>; + }; + tmp421@2a { + compatible = "ti,tmp421"; + reg = <0x2a>; + }; + tmp421@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + tmp421@1c { + compatible = "ti,tmp421"; + reg = <0x1c>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + tmp421@1d { + compatible = "ti,tmp421"; + reg = <0x1d>; + }; + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + tmp421@4d { + compatible = "ti,tmp421"; + reg = <0x4d>; + }; + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + nvt210@4c { + compatible = "nvt210"; + reg = <0x4c>; + }; + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <128>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + pca9641@70 { + compatible = "nxp,pca9641"; + reg = <0x70>; + i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + tmp421@1d { + compatible = "tmp421"; + reg = <0x1d>; + }; + adm1278@12 { + compatible = "adi,adm1278"; + reg = <0x12>; + Rsense = <500>; + }; + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + ds1100@58 { + compatible = "ds1100"; + reg = <0x58>; + }; + }; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&gpio { + pin_gpio_c7 { + gpio-hog; + gpios = ; + output; + line-name = "BIOS_SPI_MUX_S"; + }; +};