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[SCSI] Merge up to linux-2.6 head

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Conflicts:

	drivers/scsi/jazz_esp.c

Same changes made by both SCSI and SPARC trees: problem with UTF-8
conversion in the copyright.

Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This commit is contained in:
James Bottomley
2007-05-30 23:57:05 -05:00
parent 6edae708bf 3f0a6766e0
commit 5bc65793cb
1042 changed files with 45302 additions and 7344 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
include/acpi/acpi_numa.h
View File

@@ -11,11 +11,8 @@
#define MAX_PXM_DOMAINS (256) /* Old pxm spec is defined 8 bit */
#endif
extern int __cpuinitdata pxm_to_node_map[MAX_PXM_DOMAINS];
extern int __cpuinitdata node_to_pxm_map[MAX_NUMNODES];
extern int __cpuinit pxm_to_node(int);
extern int __cpuinit node_to_pxm(int);
extern int pxm_to_node(int);
extern int node_to_pxm(int);
extern int __cpuinit acpi_map_pxm_to_node(int);
extern void __cpuinit acpi_unmap_pxm_to_node(int);

50
include/asm-alpha/bitops.h
View File

@@ -313,32 +313,29 @@ static inline int ffs(int word)
* fls: find last bit set.
*/
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
static inline int fls(int word)
static inline int fls64(unsigned long word)
{
return 64 - __kernel_ctlz(word & 0xffffffff);
return 64 - __kernel_ctlz(word);
}
#else
#include <asm-generic/bitops/fls.h>
#endif
#include <asm-generic/bitops/fls64.h>
extern const unsigned char __flsm1_tab[256];
/* Compute powers of two for the given integer. */
static inline long floor_log2(unsigned long word)
static inline int fls64(unsigned long x)
{
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
return 63 - __kernel_ctlz(word);
#else
long bit;
for (bit = -1; word ; bit++)
word >>= 1;
return bit;
#endif
unsigned long t, a, r;
t = __kernel_cmpbge (x, 0x0101010101010101);
a = __flsm1_tab[t];
t = __kernel_extbl (x, a);
r = a*8 + __flsm1_tab[t] + (x != 0);
return r;
}
#endif
static inline long ceil_log2(unsigned long word)
static inline int fls(int x)
{
long bit = floor_log2(word);
return bit + (word > (1UL << bit));
return fls64((unsigned int) x);
}
/*
@@ -353,9 +350,20 @@ static inline unsigned long hweight64(unsigned long w)
return __kernel_ctpop(w);
}
#define hweight32(x) (unsigned int) hweight64((x) & 0xfffffffful)
#define hweight16(x) (unsigned int) hweight64((x) & 0xfffful)
#define hweight8(x) (unsigned int) hweight64((x) & 0xfful)
static inline unsigned int hweight32(unsigned int w)
{
return hweight64(w);
}
static inline unsigned int hweight16(unsigned int w)
{
return hweight64(w & 0xffff);
}
static inline unsigned int hweight8(unsigned int w)
{
return hweight64(w & 0xff);
}
#else
#include <asm-generic/bitops/hweight.h>
#endif

2
include/asm-alpha/thread_info.h
View File

@@ -76,12 +76,14 @@ register struct thread_info *__current_thread_info __asm__("$8");
#define TIF_UAC_NOFIX 7
#define TIF_UAC_SIGBUS 8
#define TIF_MEMDIE 9
#define TIF_RESTORE_SIGMASK 10 /* restore signal mask in do_signal */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
/* Work to do on interrupt/exception return. */
#define _TIF_WORK_MASK (_TIF_NOTIFY_RESUME \

48
include/asm-alpha/unistd.h
View File

@@ -233,6 +233,20 @@
#define __NR_osf_memcntl 260 /* not implemented */
#define __NR_osf_fdatasync 261 /* not implemented */
/*
* Ignore legacy syscalls that we don't use.
*/
#define __IGNORE_alarm
#define __IGNORE_creat
#define __IGNORE_getegid
#define __IGNORE_geteuid
#define __IGNORE_getgid
#define __IGNORE_getpid
#define __IGNORE_getppid
#define __IGNORE_getuid
#define __IGNORE_pause
#define __IGNORE_time
#define __IGNORE_utime
/*
* Linux-specific system calls begin at 300
@@ -387,10 +401,42 @@
#define __NR_inotify_init 444
#define __NR_inotify_add_watch 445
#define __NR_inotify_rm_watch 446
#define __NR_fdatasync 447
#define __NR_kexec_load 448
#define __NR_migrate_pages 449
#define __NR_openat 450
#define __NR_mkdirat 451
#define __NR_mknodat 452
#define __NR_fchownat 453
#define __NR_futimesat 454
#define __NR_fstatat64 455
#define __NR_unlinkat 456
#define __NR_renameat 457
#define __NR_linkat 458
#define __NR_symlinkat 459
#define __NR_readlinkat 460
#define __NR_fchmodat 461
#define __NR_faccessat 462
#define __NR_pselect6 463
#define __NR_ppoll 464
#define __NR_unshare 465
#define __NR_set_robust_list 466
#define __NR_get_robust_list 467
#define __NR_splice 468
#define __NR_sync_file_range 469
#define __NR_tee 470
#define __NR_vmsplice 471
#define __NR_move_pages 472
#define __NR_getcpu 473
#define __NR_epoll_pwait 474
#define __NR_utimensat 475
#define __NR_signalfd 476
#define __NR_timerfd 477
#define __NR_eventfd 478
#ifdef __KERNEL__
#define NR_SYSCALLS 447
#define NR_SYSCALLS 479
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR

2
include/asm-arm/arch-at91/at91_adc.h
View File

@@ -55,7 +55,7 @@
#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */
#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
#define AT91_ADC_DATA (0x3ff)
#endif

18
include/asm-arm/arch-integrator/smp.h
View File

@@ -1,18 +0,0 @@
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <asm/hardware.h>
#include <asm/io.h>
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
extern void secondary_scan_irqs(void);
#endif

28
include/asm-arm/arch-ixp4xx/nas100d.h
View File

@@ -10,7 +10,7 @@
* based on ixdp425.h:
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
@@ -36,31 +36,11 @@
#define NAS100D_PCI_INTD_PIN 8
#define NAS100D_PCI_INTE_PIN 7
/* GPIO */
#define NAS100D_GPIO0 0
#define NAS100D_GPIO1 1
#define NAS100D_GPIO2 2
#define NAS100D_GPIO3 3
#define NAS100D_GPIO4 4
#define NAS100D_GPIO5 5
#define NAS100D_GPIO6 6
#define NAS100D_GPIO7 7
#define NAS100D_GPIO8 8
#define NAS100D_GPIO9 9
#define NAS100D_GPIO10 10
#define NAS100D_GPIO11 11
#define NAS100D_GPIO12 12
#define NAS100D_GPIO13 13
#define NAS100D_GPIO14 14
#define NAS100D_GPIO15 15
/* Buttons */
#define NAS100D_PB_GPIO NAS100D_GPIO14
#define NAS100D_RB_GPIO NAS100D_GPIO4
#define NAS100D_PO_GPIO NAS100D_GPIO12 /* power off */
#define NAS100D_PB_GPIO 14
#define NAS100D_RB_GPIO 4
#define NAS100D_PO_GPIO 12 /* power off */
#define NAS100D_PB_IRQ IRQ_IXP4XX_GPIO14
#define NAS100D_RB_IRQ IRQ_IXP4XX_GPIO4

46
include/asm-arm/arch-ixp4xx/nslu2.h
View File

@@ -9,7 +9,7 @@
* based on ixdp425.h:
* Copyright 2004 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
@@ -34,36 +34,14 @@
#define NSLU2_PCI_INTC_PIN 9
#define NSLU2_PCI_INTD_PIN 8
/* NSLU2 Timer */
#define NSLU2_FREQ 66000000
#define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
#define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
/* GPIO */
#define NSLU2_GPIO0 0
#define NSLU2_GPIO1 1
#define NSLU2_GPIO2 2
#define NSLU2_GPIO3 3
#define NSLU2_GPIO4 4
#define NSLU2_GPIO5 5
#define NSLU2_GPIO6 6
#define NSLU2_GPIO7 7
#define NSLU2_GPIO8 8
#define NSLU2_GPIO9 9
#define NSLU2_GPIO10 10
#define NSLU2_GPIO11 11
#define NSLU2_GPIO12 12
#define NSLU2_GPIO13 13
#define NSLU2_GPIO14 14
#define NSLU2_GPIO15 15
/* Buttons */
#define NSLU2_PB_GPIO NSLU2_GPIO5
#define NSLU2_PO_GPIO NSLU2_GPIO8 /* power off */
#define NSLU2_RB_GPIO NSLU2_GPIO12
#define NSLU2_PB_GPIO 5
#define NSLU2_PO_GPIO 8 /* power off */
#define NSLU2_RB_GPIO 12
#define NSLU2_PB_IRQ IRQ_IXP4XX_GPIO5
#define NSLU2_RB_IRQ IRQ_IXP4XX_GPIO12
@@ -79,16 +57,16 @@
/* LEDs */
#define NSLU2_LED_RED NSLU2_GPIO0
#define NSLU2_LED_GRN NSLU2_GPIO1
#define NSLU2_LED_RED_GPIO 0
#define NSLU2_LED_GRN_GPIO 1
#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED)
#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN)
#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED_GPIO)
#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN_GPIO)
#define NSLU2_LED_DISK1 NSLU2_GPIO3
#define NSLU2_LED_DISK2 NSLU2_GPIO2
#define NSLU2_LED_DISK1_GPIO 3
#define NSLU2_LED_DISK2_GPIO 2
#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2)
#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3)
#define NSLU2_LED_DISK1_BM (1L << NSLU2_LED_DISK1_GPIO)
#define NSLU2_LED_DISK2_BM (1L << NSLU2_LED_DISK2_GPIO)

1
include/asm-arm/arch-ixp4xx/platform.h
View File

@@ -113,6 +113,7 @@ extern unsigned long ixp4xx_timer_freq;
extern void ixp4xx_map_io(void);
extern void ixp4xx_init_irq(void);
extern void ixp4xx_sys_init(void);
extern void ixp4xx_timer_init(void);
extern struct sys_timer ixp4xx_timer;
extern void ixp4xx_pci_preinit(void);
struct pci_sys_data;

2
include/asm-arm/arch-s3c2410/irqs.h
View File

@@ -124,7 +124,7 @@
#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
#define IRQ_S3C2443_SDI1 S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)

4
include/asm-arm/arch-s3c2410/map.h
View File

@@ -153,6 +153,10 @@
#define S3C2440_PA_AC97 (0x5B000000)
#define S3C2440_SZ_AC97 SZ_1M
/* S3C2443 High-speed SD/MMC */
#define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2443_SZ_HSMMC (256)
/* ISA style IO, for each machine to sort out mappings for, if it
* implements it. We reserve two 16M regions for ISA.
*/

4
include/asm-arm/arch-s3c2410/regs-gpioj.h
View File

@@ -98,5 +98,9 @@
#define S3C2440_GPJ12_OUTP (0x01 << 24)
#define S3C2440_GPJ12_CAMRESET (0x02 << 24)
#define S3C2443_GPJ13 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
#define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
#define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
#endif /* __ASM_ARCH_REGS_GPIOJ_H */

21
include/asm-arm/arch-s3c2410/regs-s3c2412.h Normal file
View File

@@ -0,0 +1,21 @@
/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412.h
*
* Copyright 2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2412 specific register definitions
*/
#ifndef __ASM_ARCH_REGS_S3C2412_H
#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
#define S3C2412_SWRST_RESET (0x533C2412)
#endif /* __ASM_ARCH_REGS_S3C2412_H */

2
include/asm-arm/arch-s3c2410/regs-spi.h
View File

@@ -12,6 +12,8 @@
#ifndef __ASM_ARCH_REGS_SPI_H
#define __ASM_ARCH_REGS_SPI_H
#define S3C2410_SPI1 (0x20)
#define S3C2412_SPI1 (0x100)
#define S3C2410_SPCON (0x00)

2
include/asm-arm/io.h
View File

@@ -259,9 +259,11 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
#define BIOVEC_MERGEABLE(vec1, vec2) \
((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
#ifdef CONFIG_MMU
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(unsigned long addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
#endif
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem

4
include/asm-arm/ioctls.h
View File

@@ -46,6 +46,10 @@
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define TIOCGSID 0x5429 /* Return the session ID of FD */
#define TCGETS2 _IOR('T',0x2A, struct termios2)
#define TCSETS2 _IOW('T',0x2B, struct termios2)
#define TCSETSW2 _IOW('T',0x2C, struct termios2)
#define TCSETSF2 _IOW('T',0x2D, struct termios2)
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */

2
include/asm-arm/mach/arch.h
View File

@@ -49,7 +49,7 @@ struct machine_desc {
*/
#define MACHINE_START(_type,_name) \
static const struct machine_desc __mach_desc_##_type \
__attribute_used__ \
__used \
__attribute__((__section__(".arch.info.init"))) = { \
.nr = MACH_TYPE_##_type, \
.name = _name,

4
include/asm-arm/mmu.h
View File

@@ -4,13 +4,13 @@
#ifdef CONFIG_MMU
typedef struct {
#if __LINUX_ARM_ARCH__ >= 6
#ifdef CONFIG_CPU_HAS_ASID
unsigned int id;
#endif
unsigned int kvm_seq;
} mm_context_t;
#if __LINUX_ARM_ARCH__ >= 6
#ifdef CONFIG_CPU_HAS_ASID
#define ASID(mm) ((mm)->context.id & 255)
#else
#define ASID(mm) (0)

2
include/asm-arm/mmu_context.h
View File

@@ -20,7 +20,7 @@
void __check_kvm_seq(struct mm_struct *mm);
#if __LINUX_ARM_ARCH__ >= 6
#ifdef CONFIG_CPU_HAS_ASID
/*
* On ARMv6, we have the following structure in the Context ID:

1
include/asm-arm/plat-s3c24xx/devs.h
View File

@@ -29,6 +29,7 @@ extern struct platform_device s3c_device_iis;
extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi;
extern struct platform_device s3c_device_hsmmc;
extern struct platform_device s3c_device_spi0;
extern struct platform_device s3c_device_spi1;

4
include/asm-arm/setup.h
View File

@@ -185,7 +185,7 @@ struct tagtable {
#ifdef __KERNEL__
#define __tag __attribute_used__ __attribute__((__section__(".taglist.init")))
#define __tag __used __attribute__((__section__(".taglist.init")))
#define __tagtable(tag, fn) \
static struct tagtable __tagtable_##fn __tag = { tag, fn }
@@ -218,7 +218,7 @@ struct early_params {
};
#define __early_param(name,fn) \
static struct early_params __early_##fn __attribute_used__ \
static struct early_params __early_##fn __used \
__attribute__((__section__(".early_param.init"))) = { name, fn }
#endif /* __KERNEL__ */

16
include/asm-arm/termbits.h
View File

@@ -15,6 +15,17 @@ struct termios {
cc_t c_cc[NCCS]; /* control characters */
};
struct termios2 {
tcflag_t c_iflag; /* input mode flags */
tcflag_t c_oflag; /* output mode flags */
tcflag_t c_cflag; /* control mode flags */
tcflag_t c_lflag; /* local mode flags */
cc_t c_line; /* line discipline */
cc_t c_cc[NCCS]; /* control characters */
speed_t c_ispeed; /* input speed */
speed_t c_ospeed; /* output speed */
};
struct ktermios {
tcflag_t c_iflag; /* input mode flags */
tcflag_t c_oflag; /* output mode flags */
@@ -128,6 +139,7 @@ struct ktermios {
#define HUPCL 0002000
#define CLOCAL 0004000
#define CBAUDEX 0010000
#define BOTHER 0010000
#define B57600 0010001
#define B115200 0010002
#define B230400 0010003
@@ -143,10 +155,12 @@ struct ktermios {
#define B3000000 0010015
#define B3500000 0010016
#define B4000000 0010017
#define CIBAUD 002003600000 /* input baud rate (not used) */
#define CIBAUD 002003600000 /* input baud rate */
#define CMSPAR 010000000000 /* mark or space (stick) parity */
#define CRTSCTS 020000000000 /* flow control */
#define IBSHIFT 16
/* c_lflag bits */
#define ISIG 0000001
#define ICANON 0000002

6
include/asm-arm/termios.h
View File

@@ -82,8 +82,10 @@ struct termio {
copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
})
#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
#endif /* __KERNEL__ */

15
include/asm-arm/tlbflush.h
View File

@@ -138,12 +138,27 @@
# define v6wbi_always_flags (-1UL)
#endif
#ifdef CONFIG_CPU_TLB_V7
# define v7wbi_possible_flags v6wbi_tlb_flags
# define v7wbi_always_flags v6wbi_tlb_flags
# ifdef _TLB
# define MULTI_TLB 1
# else
# define _TLB v7wbi
# endif
#else
# define v7wbi_possible_flags 0
# define v7wbi_always_flags (-1UL)
#endif
#ifndef _TLB
#error Unknown TLB model
#endif
#ifndef __ASSEMBLY__
#include <linux/sched.h>
struct cpu_tlb_fns {
void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
void (*flush_kern_range)(unsigned long, unsigned long);

10
include/asm-arm/unistd.h
View File

@@ -373,6 +373,10 @@
#define __NR_getcpu (__NR_SYSCALL_BASE+345)
/* 346 for epoll_pwait */
#define __NR_kexec_load (__NR_SYSCALL_BASE+347)
#define __NR_utimensat (__NR_SYSCALL_BASE+348)
#define __NR_signalfd (__NR_SYSCALL_BASE+349)
#define __NR_timerfd (__NR_SYSCALL_BASE+350)
#define __NR_eventfd (__NR_SYSCALL_BASE+351)
/*
* The following SWIs are ARM private.
@@ -433,5 +437,11 @@
*/
#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
/*
* Unimplemented (or alternatively implemented) syscalls
*/
#define __IGNORE_sync_file_range 1
#define __IGNORE_fadvise64_64 1
#endif /* __KERNEL__ */
#endif /* __ASM_ARM_UNISTD_H */

2
include/asm-arm26/setup.h
View File

@@ -173,7 +173,7 @@ struct tagtable {
int (*parse)(const struct tag *);
};
#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
#define __tag __used __attribute__((__section__(".taglist")))
#define __tagtable(tag, fn) \
static struct tagtable __tagtable_##fn __tag = { tag, fn }

8
include/asm-avr32/arch-at32ap/board.h
View File

@@ -30,11 +30,9 @@ struct spi_board_info;
struct platform_device *
at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
struct lcdc_platform_data {
unsigned long fbmem_start;
unsigned long fbmem_size;
};
struct atmel_lcdfb_info;
struct platform_device *
at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data);
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
unsigned long fbmem_start, unsigned long fbmem_len);
#endif /* __ASM_ARCH_BOARD_H */

17
include/asm-avr32/kdebug.h
View File

@@ -5,13 +5,22 @@
/* Grossly misnamed. */
enum die_val {
DIE_FAULT,
DIE_BREAKPOINT,
DIE_SSTEP,
DIE_PAGE_FAULT,
};
int register_page_fault_notifier(struct notifier_block *nb);
int unregister_page_fault_notifier(struct notifier_block *nb);
/*
* These are only here because kprobes.c wants them to implement a
* blatant layering violation. Will hopefully go away soon once all
* architectures are updated.
*/
static inline int register_page_fault_notifier(struct notifier_block *nb)
{
return 0;
}
static inline int unregister_page_fault_notifier(struct notifier_block *nb)
{
return 0;
}
#endif /* __ASM_AVR32_KDEBUG_H */

1
include/asm-avr32/kprobes.h
View File

@@ -26,6 +26,7 @@ struct arch_specific_insn {
kprobe_opcode_t insn[MAX_INSN_SIZE];
};
extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
extern int kprobe_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data);

5
include/asm-avr32/unistd.h
View File

@@ -296,9 +296,12 @@
#define __NR_shmctl 277
#define __NR_utimensat 278
#define __NR_signalfd 279
#define __NR_timerfd 280
#define __NR_eventfd 281
#ifdef __KERNEL__
#define NR_syscalls 279
#define NR_syscalls 282
#define __ARCH_WANT_IPC_PARSE_VERSION

1
include/asm-blackfin/bfin-global.h
View File

@@ -104,6 +104,7 @@ extern unsigned long dpdt_swapcount_table[];
extern unsigned long table_start, table_end;
extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
extern struct file_operations dpmc_fops;
extern char _start;
extern unsigned long _ramstart, _ramend, _rambase;

14
include/asm-blackfin/gpio.h
View File

@@ -148,10 +148,6 @@
#ifdef BF537_FAMILY
#define MAX_BLACKFIN_GPIOS 48
#define PORT_F 0
#define PORT_G 1
#define PORT_H 2
#define PORT_J 3
#define GPIO_PF0 0
#define GPIO_PF1 1
@@ -202,13 +198,17 @@
#define GPIO_PH14 46
#define GPIO_PH15 47
#define PORT_F GPIO_PF0
#define PORT_G GPIO_PG0
#define PORT_H GPIO_PH0
#endif
#ifdef BF561_FAMILY
#define MAX_BLACKFIN_GPIOS 48
#define PORT_FIO0 0
#define PORT_FIO1 1
#define PORT_FIO2 2
#define PORT_FIO0 GPIO_0
#define PORT_FIO1 GPIO_16
#define PORT_FIO2 GPIO_32
#endif
#ifndef __ASSEMBLY__

20
include/asm-blackfin/io.h
View File

@@ -115,13 +115,21 @@ static inline unsigned int readl(void __iomem *addr)
#ifndef __ASSEMBLY__
extern void outsb(void __iomem *port, const void *addr, unsigned long count);
extern void outsw(void __iomem *port, const void *addr, unsigned long count);
extern void outsl(void __iomem *port, const void *addr, unsigned long count);
extern void outsb(void __iomem *port, const void *addr, unsigned short count);
extern void outsw(void __iomem *port, const void *addr, unsigned short count);
extern void outsl(void __iomem *port, const void *addr, unsigned short count);
extern void insb(const void __iomem *port, void *addr, unsigned long count);
extern void insw(const void __iomem *port, void *addr, unsigned long count);
extern void insl(const void __iomem *port, void *addr, unsigned long count);
extern void insb(const void __iomem *port, void *addr, unsigned short count);
extern void insw(const void __iomem *port, void *addr, unsigned short count);
extern void insl(const void __iomem *port, void *addr, unsigned short count);
extern void dma_outsb(void __iomem *port, const void *addr, unsigned short count);
extern void dma_outsw(void __iomem *port, const void *addr, unsigned short count);
extern void dma_outsl(void __iomem *port, const void *addr, unsigned short count);
extern void dma_insb(const void __iomem *port, void *addr, unsigned short count);
extern void dma_insw(const void __iomem *port, void *addr, unsigned short count);
extern void dma_insl(const void __iomem *port, void *addr, unsigned short count);
/*
* Map some physical address range into the kernel address space.

46
include/asm-blackfin/mach-bf527/cdefBF522.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* File: include/asm-blackfin/mach-bf527/cdefbf522.h
* Based on:
* Author:
*
* Created:
* Description: system mmr register map
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CDEF_BF522_H
#define _CDEF_BF522_H
/* include all Core registers and bit definitions */
#include "defBF522.h"
/* include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include "cdefBF52x_base.h"
#endif /* _CDEF_BF522_H */

461
include/asm-blackfin/mach-bf527/cdefBF525.h Normal file
View File

@@ -0,0 +1,461 @@
/*
* File: include/asm-blackfin/mach-bf527/cdefbf525.h
* Based on:
* Author:
*
* Created:
* Description: system mmr register map
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CDEF_BF525_H
#define _CDEF_BF525_H
/* include all Core registers and bit definitions */
#include "defBF525.h"
/* include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include "cdefBF52x_base.h"
/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
/* USB Control Registers */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
/* USB Packet Control Registers */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
/* USB Endpoint FIFO Registers */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
/* USB OTG Control Registers */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
/* USB Phy Control Registers */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
/* (APHY_CNTRL is for ADI usage only) */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
/* (APHY_CALIB is for ADI usage only) */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
/* (PHY_TEST is for ADI usage only) */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
/* USB Endpoint 0 Control Registers */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
/* USB Endpoint 1 Control Registers */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
/* USB Endpoint 2 Control Registers */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
/* USB Endpoint 3 Control Registers */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
/* USB Endpoint 4 Control Registers */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
/* USB Endpoint 5 Control Registers */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
/* USB Endpoint 6 Control Registers */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
/* USB Endpoint 7 Control Registers */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
/* USB Channel 0 Config Registers */
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
/* USB Channel 1 Config Registers */
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
/* USB Channel 2 Config Registers */
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
/* USB Channel 3 Config Registers */
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
/* USB Channel 4 Config Registers */
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
/* USB Channel 5 Config Registers */
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
/* USB Channel 6 Config Registers */
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
/* USB Channel 7 Config Registers */
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
#endif /* _CDEF_BF525_H */

626
include/asm-blackfin/mach-bf527/cdefBF527.h Normal file
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@@ -0,0 +1,626 @@
/*
* File: include/asm-blackfin/mach-bf527/cdefbf527.h
* Based on:
* Author:
*
* Created:
* Description: system mmr register map
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CDEF_BF527_H
#define _CDEF_BF527_H
/* include all Core registers and bit definitions */
#include "defBF527.h"
/* include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include "cdefBF52x_base.h"
/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
/* USB Control Registers */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
/* USB Packet Control Registers */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
/* USB Endpoint FIFO Registers */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
/* USB OTG Control Registers */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
/* USB Phy Control Registers */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
/* (APHY_CNTRL is for ADI usage only) */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
/* (APHY_CALIB is for ADI usage only) */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
/* (PHY_TEST is for ADI usage only) */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
/* USB Endpoint 0 Control Registers */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
/* USB Endpoint 1 Control Registers */
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
/* USB Endpoint 2 Control Registers */
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
/* USB Endpoint 3 Control Registers */
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
/* USB Endpoint 4 Control Registers */
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
/* USB Endpoint 5 Control Registers */
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
/* USB Endpoint 6 Control Registers */
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
/* USB Endpoint 7 Control Registers */
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
/* USB Channel 0 Config Registers */
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
/* USB Channel 1 Config Registers */
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
/* USB Channel 2 Config Registers */
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
/* USB Channel 3 Config Registers */
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
/* USB Channel 4 Config Registers */
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
/* USB Channel 5 Config Registers */
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
/* USB Channel 6 Config Registers */
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
/* USB Channel 7 Config Registers */
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
#endif /* _CDEF_BF527_H */

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include/asm-blackfin/mach-bf527/cdefBF52x_base.h Normal file
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include/asm-blackfin/mach-bf527/defBF522.h Normal file
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@@ -0,0 +1,42 @@
/*
* File: include/asm-blackfin/mach-bf527/defBF522.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _DEF_BF522_H
#define _DEF_BF522_H
/* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include "defBF52x_base.h"
#endif /* _DEF_BF522_H */

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include/asm-blackfin/mach-bf527/defBF525.h Normal file
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/*
* File: include/asm-blackfin/mach-bf527/defBF525.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _DEF_BF525_H
#define _DEF_BF525_H
/* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include "defBF52x_base.h"
/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
/* USB Control Registers */
#define USB_FADDR 0xffc03800 /* Function address register */
#define USB_POWER 0xffc03804 /* Power management register */
#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
#define USB_FRAME 0xffc03820 /* USB frame number */
#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
/* USB Packet Control Registers */
#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* USB Endpoint FIFO Registers */
#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
/* USB OTG Control Registers */
#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
/* USB Phy Control Registers */
#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
/* (APHY_CNTRL is for ADI usage only) */
#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
/* (APHY_CALIB is for ADI usage only) */
#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
/* (PHY_TEST is for ADI usage only) */
#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
/* USB Endpoint 0 Control Registers */
#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
/* USB Endpoint 1 Control Registers */
#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
/* USB Endpoint 2 Control Registers */
#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
/* USB Endpoint 3 Control Registers */
#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
/* USB Endpoint 4 Control Registers */
#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
/* USB Endpoint 5 Control Registers */
#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
/* USB Endpoint 6 Control Registers */
#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
/* USB Endpoint 7 Control Registers */
#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
/* USB Channel 0 Config Registers */
#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
/* USB Channel 1 Config Registers */
#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
/* USB Channel 2 Config Registers */
#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
/* USB Channel 3 Config Registers */
#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
/* USB Channel 4 Config Registers */
#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
/* USB Channel 5 Config Registers */
#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
/* USB Channel 6 Config Registers */
#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
/* USB Channel 7 Config Registers */
#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
/* Bit masks for USB_FADDR */
#define FUNCTION_ADDRESS 0x7f /* Function address */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */
#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */
#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */
#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */
#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */
#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */
#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */
#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */
#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */
#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */
#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */
#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */
#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */
#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */
#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */
#define FRAME_NUMBER 0x7ff /* Frame number */
/* Bit masks for USB_INDEX */
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */
#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */
#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */
#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */
#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */
#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */
#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */
#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */
#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */
#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */
#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */
#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
/* Bit masks for USB_NAKLIMIT0 */
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
/* Bit masks for USB_TX_MAX_PACKET */
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_RX_MAX_PACKET */
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */
#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */
#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */
#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */
#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
/* Bit masks for USB_TXTYPE */
#define TARGET_EP_NO_T 0xf /* EP number */
#define PROTOCOL_T 0xc /* transfer type */
/* Bit masks for USB_TXINTERVAL */
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
/* Bit masks for USB_RXTYPE */
#define TARGET_EP_NO_R 0xf /* EP number */
#define PROTOCOL_R 0xc /* transfer type */
/* Bit masks for USB_RXINTERVAL */
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */
#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */
#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */
#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxADDRLOW */
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxCOUNTHIGH */
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for USB_DMAxCOUNTLOW */
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
#endif /* _DEF_BF525_H */

1089
include/asm-blackfin/mach-bf527/defBF527.h Normal file
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2009
include/asm-blackfin/mach-bf527/defBF52x_base.h Normal file
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36
include/asm-blackfin/mach-bf533/cdefBF532.h
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@@ -51,10 +51,6 @@
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -63,12 +59,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
bfin_write16(VR_CTL, val);
__builtin_bfin_ssync();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
__builtin_bfin_ssync();
local_irq_save(flags);
asm("IDLE;");
local_irq_restore(flags);
@@ -76,6 +74,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
}
/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
@@ -115,6 +117,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
/* DMA Traffic controls */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
@@ -151,16 +165,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
/* DMA Traffic controls */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
/* DMA Controller */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)

207
include/asm-blackfin/mach-bf533/defBF532.h
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@@ -46,11 +46,7 @@
#ifndef _DEF_BF532_H
#define _DEF_BF532_H
/*
#if !defined(__ADSPLPBLACKFIN__)
#warning defBF532.h should only be included for 532 compatible chips
#endif
*/
/* include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h>
@@ -65,10 +61,10 @@
#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
#define CHIPID 0xFFC00014 /* Chip ID Register */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration registe */
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration registe */
#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
@@ -218,11 +214,13 @@
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
/* DMA Traffic controls */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -407,14 +405,25 @@
/* ********************* PLL AND RESET MASKS ************************ */
/* PLL_CTL Masks */
#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
#define STOPCK_OFF 0x00000008 /* Core clock off */
#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
#define BYPASS 0x00000100 /* Bypass the PLL */
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
#define STOPCK_OFF 0x0008 /* Core clock off */
#define STOPCK 0x0008 /* Core Clock Off */
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
#if !defined(__ADSPBF538__)
/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
#endif
#define BYPASS 0x0100 /* Bypass the PLL */
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
@@ -422,6 +431,8 @@
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
@@ -429,13 +440,47 @@
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5 */
#define GAIN_10 0x0004 /* GAIN = 10 */
#define GAIN_20 0x0008 /* GAIN = 20 */
#define GAIN_50 0x000C /* GAIN = 50 */
#define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
/* CHIPID Masks */
#define CHIPID_VERSION 0xF0000000
#define CHIPID_FAMILY 0x0FFFF000
#define CHIPID_MANUFACTURE 0x00000FFE
/* SWRST Mask */
#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* SYSCR Masks */
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
@@ -483,23 +528,6 @@
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
/* ********* WATCHDOG TIMER MASKS ********************8 */
/* Watchdog Timer WDOG_CTL Register */
#define ICTL(x) ((x<<1) & 0x0006)
#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
#define TMR_EN 0x0000
#define TMR_DIS 0x0AD0
#define TRO 0x8000
#define ICTL_P0 0x01
#define ICTL_P1 0x02
#define TRO_P 0x0F
/* ***************************** UART CONTROLLER MASKS ********************** */
/* UART_LCR Register */
@@ -583,6 +611,9 @@
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define DTYPE_NORM 0x0000 /* Data Format Normal */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
@@ -592,7 +623,12 @@
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#define SLEN 0x001F /*TX Word Length */
#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__)
# define SLEN 0x001F /*TX Word Length */
#else
# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
#endif
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
@@ -601,8 +637,9 @@
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define RULAW 0x0008 /* u-Law enable */
#define RALAW 0x000C /* A-Law enable */
#define DTYPE_NORM 0x0000 /* no companding */
#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
@@ -611,7 +648,7 @@
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN 0x001F /*RX Word Length */
/* SLEN defined above */
#define RXSE 0x0100 /*RX Secondary Enable */
#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /*Right-First Data Order */
@@ -628,14 +665,37 @@
/*SPORTx_MCMC1 Masks */
#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
/* SPORTx_MCMC1 Macros */
#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
/*SPORTx_MCMC2 Masks */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
#define MFD 0x0000F000 /*Multichannel Frame Delay */
#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
@@ -660,6 +720,8 @@
#define DLEN_16 0x3800 /* Data Length = 16 Bits */
#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
#define POL 0x0000C000 /* PPI Signal Polarities */
#define POLC 0x4000 /* PPI Clock Polarity */
#define POLS 0x8000 /* PPI Frame Sync Polarity */
/* PPI_STATUS Masks */
#define FLD 0x00000400 /* Field Indicator */
@@ -729,6 +791,15 @@
#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
#define PMAP 0x00007000 /* DMA Peripheral Map Field */
#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
/* PWM Timer bit definitions */
@@ -755,9 +826,9 @@
#define TIMIL0 0x0001
#define TIMIL1 0x0002
#define TIMIL2 0x0004
#define TOVL_ERR0 0x0010
#define TOVL_ERR1 0x0020
#define TOVL_ERR2 0x0040
#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
#define TRUN0 0x1000
#define TRUN1 0x2000
#define TRUN2 0x4000
@@ -765,13 +836,21 @@
#define TIMIL0_P 0x00
#define TIMIL1_P 0x01
#define TIMIL2_P 0x02
#define TOVL_ERR0_P 0x04
#define TOVL_ERR1_P 0x05
#define TOVL_ERR2_P 0x06
#define TOVF_ERR0_P 0x04
#define TOVF_ERR1_P 0x05
#define TOVF_ERR2_P 0x06
#define TRUN0_P 0x0C
#define TRUN1_P 0x0D
#define TRUN2_P 0x0E
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#define TOVL_ERR0 TOVF_ERR0
#define TOVL_ERR1 TOVF_ERR1
#define TOVL_ERR2 TOVF_ERR2
#define TOVL_ERR0_P TOVF_ERR0_P
#define TOVL_ERR1_P TOVF_ERR1_P
#define TOVL_ERR2_P TOVF_ERR2_P
/* TIMERx_CONFIG Registers */
#define PWM_OUT 0x0001
#define WDTH_CAP 0x0002
@@ -841,6 +920,10 @@
/* SPI_CTL Masks */
#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
@@ -894,10 +977,20 @@
#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
/* SPIx_FLG Masks */
#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
/* AMGCTL Masks */
#define AMCKEN 0x00000001 /* Enable CLKOUT */
#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
@@ -1097,6 +1190,9 @@
#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
#define PFE 0x00000010 /* Enable SDRAM prefetch */
#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
@@ -1158,18 +1254,5 @@
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
#define BGSTAT 0x00000020 /* Bus granted */
/*VR_CTL Masks*/
#define WAKE 0x100
#define VLEV_6 0x60
#define VLEV_7 0x70
#define VLEV_8 0x80
#define VLEV_9 0x90
#define VLEV_10 0xA0
#define VLEV_11 0xB0
#define VLEV_12 0xC0
#define VLEV_13 0xD0
#define VLEV_14 0xE0
#define VLEV_15 0xF0
#define FREQ_3 0x03
#endif /* _DEF_BF532_H */

17
include/asm-blackfin/mach-bf537/cdefBF534.h
View File

@@ -51,12 +51,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
bfin_write16(VR_CTL, val);
__builtin_bfin_ssync();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
bfin_write32(SIC_IWR, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
__builtin_bfin_ssync();
local_irq_save(flags);
asm("IDLE;");
local_irq_restore(flags);
@@ -73,7 +75,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
@@ -398,10 +399,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
/* DMA Traffic Control Registers */
#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
@@ -1076,8 +1081,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
#define bfin_read_CAN_SFCMVER2() bfin_read16(CAN_SFCMVER2)
#define bfin_write_CAN_SFCMVER2(val) bfin_write16(CAN_SFCMVER2,val)
/* Mailbox Acceptance Masks */
#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)

3
include/asm-blackfin/mach-bf537/cdefBF537.h
View File

@@ -40,7 +40,6 @@
/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
@@ -80,7 +79,6 @@
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
@@ -147,7 +145,6 @@
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)

90
include/asm-blackfin/mach-bf537/defBF534.h
View File

@@ -216,8 +216,12 @@
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
/* DMA Traffic Control Registers */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -563,7 +567,7 @@
#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */
#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
@@ -1026,10 +1030,11 @@
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define PHYWE 0x0200 /* Enable PHY Wakeup From Hibernate */
#define CANWE 0x0400 /* Enable CAN Wakeup From Hibernate */
#define PHYCLKOE 0x4000 /* PHY Clock Output Enable */
#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
@@ -1050,7 +1055,7 @@
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* SYSCR Masks */
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
@@ -1107,19 +1112,9 @@
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
/* *************** WATCHDOG TIMER MASKS *******************************************/
/* WDOG_CTL Masks */
#define WDOG_RESET 0x0000 /* Generate Reset Event */
#define WDOG_NMI 0x0002 /* Generate Non-Maskable Interrupt (NMI) Event */
#define WDOG_GPI 0x0004 /* Generate General Purpose (GP) Interrupt */
#define WDOG_NONE 0x0006 /* Disable Watchdog Timer Interrupts */
#define TMR_EN 0x0FF0 /* Watchdog Counter Enable */
#define TMR_DIS 0x0AD0 /* Watchdog Counter Disable */
#define TRO 0x8000 /* Watchdog Expired */
/* ************** UART CONTROLLER MASKS *************************/
/* UARTx_LCR Masks */
#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
#define STB 0x04 /* Stop Bits */
#define PEN 0x08 /* Parity Enable */
#define EPS 0x10 /* Even Parity Select */
@@ -1128,8 +1123,8 @@
#define DLAB 0x80 /* Divisor Latch Access */
/* UARTx_MCR Mask */
#define LOOP 0x10 /* Loopback Mode Enable */
#define LOOP_ENA 0x10 /* Loopback Mode Enable */
#define LOOP_ENA_P 0x04
/* UARTx_LSR Masks */
#define DR 0x01 /* Data Ready */
#define OE 0x02 /* Overrun Error */
@@ -1229,10 +1224,10 @@
#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
#define TOVL_ERR0 0x00000010 /* Timer 0 Counter Overflow */
#define TOVL_ERR1 0x00000020 /* Timer 1 Counter Overflow */
#define TOVL_ERR2 0x00000040 /* Timer 2 Counter Overflow */
#define TOVL_ERR3 0x00000080 /* Timer 3 Counter Overflow */
#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
@@ -1241,15 +1236,24 @@
#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
#define TOVL_ERR4 0x00100000 /* Timer 4 Counter Overflow */
#define TOVL_ERR5 0x00200000 /* Timer 5 Counter Overflow */
#define TOVL_ERR6 0x00400000 /* Timer 6 Counter Overflow */
#define TOVL_ERR7 0x00800000 /* Timer 7 Counter Overflow */
#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#define TOVL_ERR0 TOVF_ERR0
#define TOVL_ERR1 TOVF_ERR1
#define TOVL_ERR2 TOVF_ERR2
#define TOVL_ERR3 TOVF_ERR3
#define TOVL_ERR4 TOVF_ERR4
#define TOVL_ERR5 TOVF_ERR5
#define TOVL_ERR6 TOVF_ERR6
#define TOVL_ERR7 TOVF_ERR7
/* TIMERx_CONFIG Masks */
#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
@@ -1647,6 +1651,8 @@
#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
@@ -1859,8 +1865,10 @@
#define TXECNT 0xFF00 /* Transmit Error Counter */
/* CAN_INTR Masks */
#define MBRIF 0x0001 /* Mailbox Receive Interrupt */
#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */
#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
#define MBRIF MBRIRQ /* legacy */
#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
#define MBTIF MBTIRQ /* legacy */
#define GIRQ 0x0004 /* Global Interrupt */
#define SMACK 0x0008 /* Sleep Mode Acknowledge */
#define CANTX 0x0040 /* CAN TX Bus Value */
@@ -2445,8 +2453,8 @@
#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
#define PFDE 0x0008 /* Port F DMA Request Enable */
#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */
#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */
#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
#define PFTE 0x0010 /* Port F Timer Enable */
#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
@@ -2498,4 +2506,20 @@
#define OI 0x4000 /* Overflow Interrupt Generated */
#define BDI 0x8000 /* Block Done Interrupt Generated */
/* entry addresses of the user-callable Boot ROM functions */
#define _BOOTROM_RESET 0xEF000000
#define _BOOTROM_FINAL_INIT 0xEF000002
#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#define PGDE_UART PFDE_UART
#define PGDE_DMA PFDE_DMA
#define CKELOW SCKELOW
#endif /* _DEF_BF534_H */

8
include/asm-blackfin/mach-bf537/defBF537.h
View File

@@ -32,12 +32,12 @@
#ifndef _DEF_BF537_H
#define _DEF_BF537_H
/*include all Core registers and bit definitions*/
#include "defBF537.h"
/*include core specific register pointer definitions*/
/* Include all Core registers and bit definitions*/
#include <asm/mach-common/cdef_LPBlackfin.h>
/* Include all MMR and bit defines common to BF534 */
#include "defBF534.h"
/************************************************************************************
** Define EMAC Section Unique to BF536/BF537
*************************************************************************************/

590
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/*
* File: include/asm-blackfin/mach-bf548/cdefBF542.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CDEF_BF542_H
#define _CDEF_BF542_H
/* include all Core registers and bit definitions */
#include "defBF542.h"
/* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
#include "cdefBF54x_base.h"
/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
/* ATAPI Registers */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
/* SDH Registers */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
#define bfin_read_SDH_DATA_CNT() fin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
#define bfin_read_SDH_STATUS_CLR() fin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) fin_write16(SDH_STATUS_CLR, val)
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
/* USB Control Registers */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
#define bfin_read_USB_TESTMODE() fin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) fin_write16(USB_TESTMODE, val)
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
/* USB Packet Control Registers */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
/* USB Endbfin_read_()oint FIFO Registers */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
/* USB OTG Control Registers */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) fin_write16(USB_OTG_VBUS_IRQ, val)
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
/* USB Phy Control Registers */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
/* (APHY_CNTRL is for ADI usage only) */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
/* (APHY_CALIB is for ADI usage only) */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
/* (PHY_TEST is for ADI usage only) */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
/* USB Endbfin_read_()oint 0 Control Registers */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
/* USB Endbfin_read_()oint 1 Control Registers */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
/* USB Endbfin_read_()oint 2 Control Registers */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
/* USB Endbfin_read_()oint 3 Control Registers */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
/* USB Endbfin_read_()oint 4 Control Registers */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
/* USB Endbfin_read_()oint 5 Control Registers */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
/* USB Endbfin_read_()oint 6 Control Registers */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
/* USB Endbfin_read_()oint 7 Control Registers */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
/* USB Channel 0 Config Registers */
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
/* USB Channel 1 Config Registers */
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
/* USB Channel 2 Config Registers */
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
/* USB Channel 3 Config Registers */
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
/* USB Channel 4 Config Registers */
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
/* USB Channel 5 Config Registers */
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
/* USB Channel 6 Config Registers */
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
/* USB Channel 7 Config Registers */
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
/* Keybfin_read_()ad Registers */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
#endif /* _CDEF_BF542_H */

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include/asm-blackfin/mach-bf548/cdefBF544.h Normal file
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/*
* File: include/asm-blackfin/mach-bf548/cdefBF544.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CDEF_BF544_H
#define _CDEF_BF544_H
/* include all Core registers and bit definitions */
#include "defBF544.h"
/* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
#include "cdefBF54x_base.h"
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
/* Timer Registers */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
/* Timer Groubfin_read_() of 3 */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
/* EPPI0 Registers */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
/* Two Wire Interface Registers (TWI1) */
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
/* CAN Controller 1 Config 1 Registers */
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
/* CAN Controller 1 Config 2 Registers */
#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
/* CAN Controller 1 Mailbox Data Registers */
#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
/* CAN Controller 1 Mailbox Data Registers */
#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
/* HOST Port Registers */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
/* Pixel Combfin_read_()ositor (PIXC) Registers */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
/* Handshake MDMA 0 Registers */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
/* Handshake MDMA 1 Registers */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
#endif /* _CDEF_BF544_H */

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/*
* File: include/asm-blackfin/mach-bf548/defBF544.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _DEF_BF544_H
#define _DEF_BF544_H
/* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include "defBF54x_base.h"
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
/* Timer Registers */
#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
/* Timer Group of 3 Registers */
#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
/* EPPI0 Registers */
#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
/* Two Wire Interface Registers (TWI1) */
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
/* CAN Controller 1 Config 1 Registers */
#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
/* CAN Controller 1 Config 2 Registers */
#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
/* CAN Controller 1 Mailbox Data Registers */
#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
/* CAN Controller 1 Mailbox Data Registers */
#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
/* HOST Port Registers */
#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
/* Pixel Compositor (PIXC) Registers */
#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
/* Handshake MDMA 0 Registers */
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
/* Handshake MDMA 1 Registers */
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
/* ********************************************************** */
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
/* and MULTI BIT READ MACROS */
/* ********************************************************** */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
#define nPIXC_EN 0x0
#define OVR_A_EN 0x2 /* Overlay A Enable */
#define nOVR_A_EN 0x0
#define OVR_B_EN 0x4 /* Overlay B Enable */
#define nOVR_B_EN 0x0
#define IMG_FORM 0x8 /* Image Data Format */
#define nIMG_FORM 0x0
#define OVR_FORM 0x10 /* Overlay Data Format */
#define nOVR_FORM 0x0
#define OUT_FORM 0x20 /* Output Data Format */
#define nOUT_FORM 0x0
#define UDS_MOD 0x40 /* Resampling Mode */
#define nUDS_MOD 0x0
#define TC_EN 0x80 /* Transparent Color Enable */
#define nTC_EN 0x0
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_AHSTART */
#define A_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_AHEND */
#define A_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_AVSTART */
#define A_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_AVEND */
#define A_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_ATRANSP */
#define A_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_BHSTART */
#define B_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_BHEND */
#define B_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_BVSTART */
#define B_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_BVEND */
#define B_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_BTRANSP */
#define B_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
#define nOVR_INT_EN 0x0
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
#define nFRM_INT_EN 0x0
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
#define nOVR_INT_STAT 0x0
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
#define nFRM_INT_STAT 0x0
/* Bit masks for PIXC_RYCON */
#define A11 0x3ff /* A11 in the Coefficient Matrix */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
#define nRY_MULT4 0x0
/* Bit masks for PIXC_GUCON */
#define A21 0x3ff /* A21 in the Coefficient Matrix */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
#define nGU_MULT4 0x0
/* Bit masks for PIXC_BVCON */
#define A31 0x3ff /* A31 in the Coefficient Matrix */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
#define nBV_MULT4 0x0
/* Bit masks for PIXC_CCBIAS */
#define A14 0x3ff /* A14 in the Bias Vector */
#define A24 0xffc00 /* A24 in the Bias Vector */
#define A34 0x3ff00000 /* A34 in the Bias Vector */
/* Bit masks for PIXC_TC */
#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
#define nHOST_EN 0x0
#define HOST_END 0x2 /* Host Endianess */
#define nHOST_END 0x0
#define DATA_SIZE 0x4 /* Data Size */
#define nDATA_SIZE 0x0
#define HOST_RST 0x8 /* Host Reset */
#define nHOST_RST 0x0
#define HRDY_OVR 0x20 /* Host Ready Override */
#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */
#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */
#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */
#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */
#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */
#define nBDR 0x0
/* Bit masks for HOST_STATUS */
#define READY 0x1 /* DMA Ready */
#define nREADY 0x0
#define FIFOFULL 0x2 /* FIFO Full */
#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define nFIFOEMPTY 0x0
#define COMPLETE 0x8 /* DMA Complete */
#define nCOMPLETE 0x0
#define HSHK 0x10 /* Host Handshake */
#define nHSHK 0x0
#define TIMEOUT 0x20 /* Host Timeout */
#define nTIMEOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */
#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */
#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */
#define nBTE 0x0
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
#define nTIMEN8 0x0
#define TIMEN9 0x2 /* Timer 9 Enable */
#define nTIMEN9 0x0
#define TIMEN10 0x4 /* Timer 10 Enable */
#define nTIMEN10 0x0
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
#define nTIMDIS8 0x0
#define TIMDIS9 0x2 /* Timer 9 Disable */
#define nTIMDIS9 0x0
#define TIMDIS10 0x4 /* Timer 10 Disable */
#define nTIMDIS10 0x0
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
#define nTIMIL8 0x0
#define TIMIL9 0x2 /* Timer 9 Interrupt */
#define nTIMIL9 0x0
#define TIMIL10 0x4 /* Timer 10 Interrupt */
#define nTIMIL10 0x0
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
#define nTOVF_ERR8 0x0
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
#define nTOVF_ERR9 0x0
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
#define nTOVF_ERR10 0x0
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
#define nTRUN8 0x0
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
#define nTRUN9 0x0
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
#define nTRUN10 0x0
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
#define nHMDMAEN 0x0
#define REP 0x2 /* Handshake MDMA Request Polarity */
#define nREP 0x0
#define UTE 0x8 /* Urgency Threshold Enable */
#define nUTE 0x0
#define OIE 0x10 /* Overflow Interrupt Enable */
#define nOIE 0x0
#define BDIE 0x20 /* Block Done Interrupt Enable */
#define nBDIE 0x0
#define MBDI 0x40 /* Mask Block Done Interrupt */
#define nMBDI 0x0
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
#define nRBC 0x0
#define PS 0x2000 /* Pin Status */
#define nPS 0x0
#define OI 0x4000 /* Overflow Interrupt Generated */
#define nOI 0x0
#define BDI 0x8000 /* Block Done Interrupt Generated */
#define nBDI 0x0
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
#endif /* _DEF_BF544_H */

1966
include/asm-blackfin/mach-bf548/defBF548.h Normal file
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3472
include/asm-blackfin/mach-bf548/defBF549.h Normal file
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4902
include/asm-blackfin/mach-bf548/defBF54x_base.h Normal file
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6
include/asm-blackfin/mach-bf561/cdefBF561.h
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@@ -59,12 +59,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
bfin_write16(VR_CTL, val);
__builtin_bfin_ssync();
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SICA_IWR0);
/* Only allow PPL Wakeup) */
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
bfin_write16(VR_CTL, val);
__builtin_bfin_ssync();
local_irq_save(flags);
asm("IDLE;");
local_irq_restore(flags);

105
include/asm-blackfin/mach-bf561/defBF561.h
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@@ -904,23 +904,6 @@
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
/* ********* WATCHDOG TIMER MASKS ********************8 */
/* Watchdog Timer WDOG_CTL Register */
#define ICTL(x) ((x<<1) & 0x0006)
#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
#define TMR_EN 0x0000
#define TMR_DIS 0x0AD0
#define TRO 0x8000
#define ICTL_P0 0x01
#define ICTL_P1 0x02
#define TRO_P 0x0F
/* ***************************** UART CONTROLLER MASKS ********************** */
/* UART_LCR Register */
@@ -1214,18 +1197,18 @@
#define TIMIL9 0x0002
#define TIMIL10 0x0004
#define TIMIL11 0x0008
#define TOVL_ERR0 0x00000010
#define TOVL_ERR1 0x00000020
#define TOVL_ERR2 0x00000040
#define TOVL_ERR3 0x00000080
#define TOVL_ERR4 0x00100000
#define TOVL_ERR5 0x00200000
#define TOVL_ERR6 0x00400000
#define TOVL_ERR7 0x00800000
#define TOVL_ERR8 0x0010
#define TOVL_ERR9 0x0020
#define TOVL_ERR10 0x0040
#define TOVL_ERR11 0x0080
#define TOVF_ERR0 0x00000010
#define TOVF_ERR1 0x00000020
#define TOVF_ERR2 0x00000040
#define TOVF_ERR3 0x00000080
#define TOVF_ERR4 0x00100000
#define TOVF_ERR5 0x00200000
#define TOVF_ERR6 0x00400000
#define TOVF_ERR7 0x00800000
#define TOVF_ERR8 0x0010
#define TOVF_ERR9 0x0020
#define TOVF_ERR10 0x0040
#define TOVF_ERR11 0x0080
#define TRUN0 0x00001000
#define TRUN1 0x00002000
#define TRUN2 0x00004000
@@ -1251,18 +1234,18 @@
#define TIMIL9_P 0x01
#define TIMIL10_P 0x02
#define TIMIL11_P 0x03
#define TOVL_ERR0_P 0x04
#define TOVL_ERR1_P 0x05
#define TOVL_ERR2_P 0x06
#define TOVL_ERR3_P 0x07
#define TOVL_ERR4_P 0x14
#define TOVL_ERR5_P 0x15
#define TOVL_ERR6_P 0x16
#define TOVL_ERR7_P 0x17
#define TOVL_ERR8_P 0x04
#define TOVL_ERR9_P 0x05
#define TOVL_ERR10_P 0x06
#define TOVL_ERR11_P 0x07
#define TOVF_ERR0_P 0x04
#define TOVF_ERR1_P 0x05
#define TOVF_ERR2_P 0x06
#define TOVF_ERR3_P 0x07
#define TOVF_ERR4_P 0x14
#define TOVF_ERR5_P 0x15
#define TOVF_ERR6_P 0x16
#define TOVF_ERR7_P 0x17
#define TOVF_ERR8_P 0x04
#define TOVF_ERR9_P 0x05
#define TOVF_ERR10_P 0x06
#define TOVF_ERR11_P 0x07
#define TRUN0_P 0x0C
#define TRUN1_P 0x0D
#define TRUN2_P 0x0E
@@ -1276,6 +1259,32 @@
#define TRUN10_P 0x0E
#define TRUN11_P 0x0F
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#define TOVL_ERR0 TOVF_ERR0
#define TOVL_ERR1 TOVF_ERR1
#define TOVL_ERR2 TOVF_ERR2
#define TOVL_ERR3 TOVF_ERR3
#define TOVL_ERR4 TOVF_ERR4
#define TOVL_ERR5 TOVF_ERR5
#define TOVL_ERR6 TOVF_ERR6
#define TOVL_ERR7 TOVF_ERR7
#define TOVL_ERR8 TOVF_ERR8
#define TOVL_ERR9 TOVF_ERR9
#define TOVL_ERR10 TOVF_ERR10
#define TOVL_ERR11 TOVF_ERR11
#define TOVL_ERR0_P TOVF_ERR0_P
#define TOVL_ERR1_P TOVF_ERR1_P
#define TOVL_ERR2_P TOVF_ERR2_P
#define TOVL_ERR3_P TOVF_ERR3_P
#define TOVL_ERR4_P TOVF_ERR4_P
#define TOVL_ERR5_P TOVF_ERR5_P
#define TOVL_ERR6_P TOVF_ERR6_P
#define TOVL_ERR7_P TOVF_ERR7_P
#define TOVL_ERR8_P TOVF_ERR8_P
#define TOVL_ERR9_P TOVF_ERR9_P
#define TOVL_ERR10_P TOVF_ERR10_P
#define TOVL_ERR11_P TOVF_ERR11_P
/* TIMERx_CONFIG Registers */
#define PWM_OUT 0x0001
#define WDTH_CAP 0x0002
@@ -1700,18 +1709,4 @@
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
#define BGSTAT 0x00000020 /* Bus granted */
/*VR_CTL Masks*/
#define WAKE 0x100
#define VLEV_6 0x60
#define VLEV_7 0x70
#define VLEV_8 0x80
#define VLEV_9 0x90
#define VLEV_10 0xA0
#define VLEV_11 0xB0
#define VLEV_12 0xC0
#define VLEV_13 0xD0
#define VLEV_14 0xE0
#define VLEV_15 0xF0
#define FREQ_3 0x03
#endif /* _DEF_BF561_H */

143
include/asm-blackfin/mach-common/cdef_LPBlackfin.h
View File

@@ -36,417 +36,288 @@
#include <asm/mach-common/def_LPBlackfin.h>
/*Cache & SRAM Memory*/
#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
/*
#define MMR_TIMEOUT 0xFFE00010
*/
#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
/*
#define DTEST_INDEX 0xFFE00304
*/
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
/*
#define DTEST_DATA2 0xFFE00408
#define DTEST_DATA3 0xFFE0040C
*/
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
#if 0
#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
#endif
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
/* Event/Interrupt Registers*/
#define pEVT0 ((volatile void **)EVT0)
#define bfin_read_EVT0() bfin_read32(EVT0)
#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
#define pEVT1 ((volatile void **)EVT1)
#define bfin_read_EVT1() bfin_read32(EVT1)
#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
#define pEVT2 ((volatile void **)EVT2)
#define bfin_read_EVT2() bfin_read32(EVT2)
#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
#define pEVT3 ((volatile void **)EVT3)
#define bfin_read_EVT3() bfin_read32(EVT3)
#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
#define pEVT4 ((volatile void **)EVT4)
#define bfin_read_EVT4() bfin_read32(EVT4)
#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
#define pEVT5 ((volatile void **)EVT5)
#define bfin_read_EVT5() bfin_read32(EVT5)
#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
#define pEVT6 ((volatile void **)EVT6)
#define bfin_read_EVT6() bfin_read32(EVT6)
#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
#define pEVT7 ((volatile void **)EVT7)
#define bfin_read_EVT7() bfin_read32(EVT7)
#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
#define pEVT8 ((volatile void **)EVT8)
#define bfin_read_EVT8() bfin_read32(EVT8)
#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
#define pEVT9 ((volatile void **)EVT9)
#define bfin_read_EVT9() bfin_read32(EVT9)
#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
#define pEVT10 ((volatile void **)EVT10)
#define bfin_read_EVT10() bfin_read32(EVT10)
#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
#define pEVT11 ((volatile void **)EVT11)
#define bfin_read_EVT11() bfin_read32(EVT11)
#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
#define pEVT12 ((volatile void **)EVT12)
#define bfin_read_EVT12() bfin_read32(EVT12)
#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
#define pEVT13 ((volatile void **)EVT13)
#define bfin_read_EVT13() bfin_read32(EVT13)
#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
#define pEVT14 ((volatile void **)EVT14)
#define bfin_read_EVT14() bfin_read32(EVT14)
#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
#define pEVT15 ((volatile void **)EVT15)
#define bfin_read_EVT15() bfin_read32(EVT15)
#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
#define pIMASK ((volatile unsigned long *)IMASK)
#define bfin_read_IMASK() bfin_read32(IMASK)
#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
#define pIPEND ((volatile unsigned long *)IPEND)
#define bfin_read_IPEND() bfin_read32(IPEND)
#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
#define pILAT ((volatile unsigned long *)ILAT)
#define bfin_read_ILAT() bfin_read32(ILAT)
#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
/*Core Timer Registers*/
#define pTCNTL ((volatile unsigned long *)TCNTL)
#define bfin_read_TCNTL() bfin_read32(TCNTL)
#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
#define pTSCALE ((volatile unsigned long *)TSCALE)
#define bfin_read_TSCALE() bfin_read32(TSCALE)
#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
/*Debug/MP/Emulation Registers*/
#define pDSPID ((volatile unsigned long *)DSPID)
#define bfin_read_DSPID() bfin_read32(DSPID)
#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
/*Trace Buffer Registers*/
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
#define pTBUF ((volatile void **)TBUF)
#define bfin_read_TBUF() bfin_read32(TBUF)
#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
/*Watch Point Control Registers*/
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
#define pWPIA0 ((volatile void **)WPIA0)
#define bfin_read_WPIA0() bfin_read32(WPIA0)
#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
#define pWPIA1 ((volatile void **)WPIA1)
#define bfin_read_WPIA1() bfin_read32(WPIA1)
#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
#define pWPIA2 ((volatile void **)WPIA2)
#define bfin_read_WPIA2() bfin_read32(WPIA2)
#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
#define pWPIA3 ((volatile void **)WPIA3)
#define bfin_read_WPIA3() bfin_read32(WPIA3)
#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
#define pWPIA4 ((volatile void **)WPIA4)
#define bfin_read_WPIA4() bfin_read32(WPIA4)
#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
#define pWPIA5 ((volatile void **)WPIA5)
#define bfin_read_WPIA5() bfin_read32(WPIA5)
#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
#define pWPDACTL ((volatile unsigned long *)WPDACTL)
#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
#define pWPDA0 ((volatile void **)WPDA0)
#define bfin_read_WPDA0() bfin_read32(WPDA0)
#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
#define pWPDA1 ((volatile void **)WPDA1)
#define bfin_read_WPDA1() bfin_read32(WPDA1)
#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
/*Performance Monitor Registers*/
#define pPFCTL ((volatile unsigned long *)PFCTL)
#define bfin_read_PFCTL() bfin_read32(PFCTL)
#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
@@ -454,18 +325,4 @@
#define IPRIO 0xFFE02110
*/
#if defined(CONFIG_BFIN_ALIVE_LED)
#define pCONFIG_BFIN_ALIVE_LED_DPORT \
(volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_DPORT
#define pCONFIG_BFIN_ALIVE_LED_PORT \
(volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_PORT
#endif
#if defined(CONFIG_BFIN_IDLE_LED)
#define pCONFIG_BFIN_IDLE_LED_DPORT \
(volatile unsigned short *)CONFIG_BFIN_IDLE_LED_DPORT
#define pCONFIG_BFIN_IDLE_LED_PORT \
(volatile unsigned short *)CONFIG_BFIN_IDLE_LED_PORT
#endif
#endif /* _CDEF_LPBLACKFIN_H */

4
include/asm-blackfin/processor.h
View File

@@ -104,13 +104,13 @@ unsigned long get_wchan(struct task_struct *p);
#define cpu_relax() barrier()
/* Get the Silicon Revision of the chip */
static inline uint32_t bfin_revid(void)
static inline __attribute_pure__ uint32_t bfin_revid(void)
{
/* stored in the upper 4 bits */
return bfin_read_CHIPID() >> 28;
}
static inline uint32_t bfin_compiled_revid(void)
static inline __attribute_pure__ uint32_t bfin_compiled_revid(void)
{
#if defined(CONFIG_BF_REV_0_0)
return 0;

4
include/asm-blackfin/uaccess.h
View File

@@ -14,7 +14,7 @@
#include <linux/string.h>
#include <asm/segment.h>
#ifndef CONFIG_NO_ACCESS_CHECK
#ifdef CONFIG_ACCESS_CHECK
# include <asm/bfin-global.h>
#endif
@@ -56,7 +56,7 @@ static inline int is_in_rom(unsigned long addr)
* get_fs() == KERNEL_DS, checking is bypassed.
*/
#ifdef CONFIG_NO_ACCESS_CHECK
#ifndef CONFIG_ACCESS_CHECK
static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
#else
#ifdef CONFIG_ACCESS_OK_L1

2
include/asm-generic/bug.h
View File

@@ -35,7 +35,7 @@ struct bug_entry {
#define WARN_ON(condition) ({ \
typeof(condition) __ret_warn_on = (condition); \
if (unlikely(__ret_warn_on)) { \
printk("BUG: at %s:%d %s()\n", __FILE__, \
printk("WARNING: at %s:%d %s()\n", __FILE__, \
__LINE__, __FUNCTION__); \
dump_stack(); \
} \

12
include/asm-generic/vmlinux.lds.h
View File

@@ -9,6 +9,11 @@
/* Align . to a 8 byte boundary equals to maximum function alignment. */
#define ALIGN_FUNCTION() . = ALIGN(8)
/* .data section */
#define DATA_DATA \
*(.data) \
*(.data.init.refok)
#define RODATA \
. = ALIGN(4096); \
.rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \
@@ -139,6 +144,13 @@
VMLINUX_SYMBOL(__security_initcall_end) = .; \
}
/* .text section. Map to function alignment to avoid address changes
* during second ld run in second ld pass when generating System.map */
#define TEXT_TEXT \
ALIGN_FUNCTION(); \
*(.text) \
*(.text.init.refok)
/* sched.text is aling to function alignment to secure we have same
* address even at second ld pass when generating System.map */
#define SCHED_TEXT \

2
include/asm-i386/atomic.h
View File

@@ -182,7 +182,7 @@ static __inline__ int atomic_add_return(int i, atomic_t *v)
int __i;
#ifdef CONFIG_M386
unsigned long flags;
if(unlikely(boot_cpu_data.x86==3))
if(unlikely(boot_cpu_data.x86 <= 3))
goto no_xadd;
#endif
/* Modern 486+ processor */

2
include/asm-i386/local.h
View File

@@ -135,7 +135,7 @@ static __inline__ long local_add_return(long i, local_t *l)
long __i;
#ifdef CONFIG_M386
unsigned long flags;
if(unlikely(boot_cpu_data.x86==3))
if(unlikely(boot_cpu_data.x86 <= 3))
goto no_xadd;
#endif
/* Modern 486+ processor */

2
include/asm-i386/tlbflush.h
View File

@@ -90,6 +90,8 @@
#ifndef CONFIG_SMP
#include <linux/sched.h>
#define flush_tlb() __flush_tlb()
#define flush_tlb_all() __flush_tlb_all()
#define local_flush_tlb() __flush_tlb()

7
include/asm-ia64/acpi.h
View File

@@ -30,6 +30,8 @@
#ifdef __KERNEL__
#include <acpi/pdc_intel.h>
#include <linux/init.h>
#include <linux/numa.h>
#include <asm/system.h>
@@ -119,11 +121,6 @@ extern int __devinitdata pxm_to_nid_map[MAX_PXM_DOMAINS];
extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
#endif
/*
* Refer Intel ACPI _PDC support document for bit definitions
*/
#define ACPI_PDC_EST_CAPABILITY_SMP 0x8
#endif /*__KERNEL__*/
#endif /*_ASM_ACPI_H*/

16
include/asm-ia64/kdebug.h
View File

@@ -28,14 +28,24 @@
*/
#include <linux/notifier.h>
extern int register_page_fault_notifier(struct notifier_block *);
extern int unregister_page_fault_notifier(struct notifier_block *);
/*
* These are only here because kprobes.c wants them to implement a
* blatant layering violation. Will hopefully go away soon once all
* architectures are updated.
*/
static inline int register_page_fault_notifier(struct notifier_block *nb)
{
return 0;
}
static inline int unregister_page_fault_notifier(struct notifier_block *nb)
{
return 0;
}
enum die_val {
DIE_BREAK = 1,
DIE_FAULT,
DIE_OOPS,
DIE_PAGE_FAULT,
DIE_MACHINE_HALT,
DIE_MACHINE_RESTART,
DIE_MCA_MONARCH_ENTER,

1
include/asm-ia64/kprobes.h
View File

@@ -120,6 +120,7 @@ struct arch_specific_insn {
unsigned short slot;
};
extern int kprobes_fault_handler(struct pt_regs *regs, int trapnr);
extern int kprobe_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data);

18
include/asm-ia64/unistd.h
View File

@@ -296,11 +296,27 @@
#define __NR_getcpu 1304
#define __NR_epoll_pwait 1305
#define __NR_utimensat 1306
#define __NR_signalfd 1307
#define __NR_timerfd 1308
#define __NR_eventfd 1309
#ifdef __KERNEL__
#define NR_syscalls 283 /* length of syscall table */
#define NR_syscalls 286 /* length of syscall table */
/*
* The following defines stop scripts/checksyscalls.sh from complaining about
* unimplemented system calls. Glibc provides for each of these by using
* more modern equivalent system calls.
*/
#define __IGNORE_fork /* clone() */
#define __IGNORE_time /* gettimeofday() */
#define __IGNORE_alarm /* setitimer(ITIMER_REAL, ... */
#define __IGNORE_pause /* rt_sigprocmask(), rt_sigsuspend() */
#define __IGNORE_utime /* utimes() */
#define __IGNORE_getpgrp /* getpgid() */
#define __IGNORE_vfork /* clone() */
#define __ARCH_WANT_SYS_RT_SIGACTION
#define __ARCH_WANT_SYS_RT_SIGSUSPEND

1
include/asm-mips/pgalloc.h
View File

@@ -11,6 +11,7 @@
#include <linux/highmem.h>
#include <linux/mm.h>
#include <linux/sched.h>
static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
pte_t *pte)

1
include/asm-parisc/mmu_context.h
View File

@@ -2,6 +2,7 @@
#define __PARISC_MMU_CONTEXT_H
#include <linux/mm.h>
#include <linux/sched.h>
#include <asm/atomic.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>

1
include/asm-parisc/tlbflush.h
View File

@@ -4,6 +4,7 @@
/* TLB flushing routines.... */
#include <linux/mm.h>
#include <linux/sched.h>
#include <asm/mmu_context.h>

6
include/asm-powerpc/cputable.h
View File

@@ -302,6 +302,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7448 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
CPU_FTR_PPC_LE)
#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \

2
include/asm-powerpc/mmu-44x.h
View File

@@ -55,8 +55,6 @@
typedef unsigned long long phys_addr_t;
extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
typedef struct {
unsigned long id;
unsigned long vdso_base;

1
include/asm-powerpc/mmu_context.h
View File

@@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <asm/mmu.h>
#include <asm/cputable.h>
#include <asm-generic/mm_hooks.h>

6
include/asm-powerpc/mpc8260.h
View File

@@ -5,8 +5,8 @@
* this one and the configuration switching is done here.
*/
#ifdef __KERNEL__
#ifndef __ASM_PPC_MPC8260_H__
#define __ASM_PPC_MPC8260_H__
#ifndef __ASM_POWERPC_MPC8260_H__
#define __ASM_POWERPC_MPC8260_H__
#ifdef CONFIG_8260
@@ -20,5 +20,5 @@
#endif
#endif /* CONFIG_8260 */
#endif /* !__ASM_PPC_MPC8260_H__ */
#endif /* !__ASM_POWERPC_MPC8260_H__ */
#endif /* __KERNEL__ */

15
include/asm-powerpc/pgtable-ppc32.h
View File

@@ -782,23 +782,8 @@ extern void kernel_set_cachemode (unsigned long address, unsigned long size,
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define kern_addr_valid(addr) (1)
#ifdef CONFIG_PHYS_64BIT
extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
unsigned long paddr, unsigned long size, pgprot_t prot);
static inline int io_remap_pfn_range(struct vm_area_struct *vma,
unsigned long vaddr,
unsigned long pfn,
unsigned long size,
pgprot_t prot)
{
phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
}
#else
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
remap_pfn_range(vma, vaddr, pfn, size, prot)
#endif
/*
* No page table caches to initialise

6
include/asm-powerpc/pmac_feature.h
View File

@@ -28,8 +28,8 @@
*/
#ifdef __KERNEL__
#ifndef __PPC_ASM_PMAC_FEATURE_H
#define __PPC_ASM_PMAC_FEATURE_H
#ifndef __ASM_POWERPC_PMAC_FEATURE_H
#define __ASM_POWERPC_PMAC_FEATURE_H
#include <asm/macio.h>
#include <asm/machdep.h>
@@ -393,5 +393,5 @@ extern u32 __iomem *uninorth_base;
#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
#endif /* __PPC_ASM_PMAC_FEATURE_H */
#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
#endif /* __KERNEL__ */

3
include/asm-powerpc/systbl.h
View File

@@ -308,3 +308,6 @@ COMPAT_SYS_SPU(move_pages)
SYSCALL_SPU(getcpu)
COMPAT_SYS(epoll_pwait)
COMPAT_SYS_SPU(utimensat)
COMPAT_SYS_SPU(signalfd)
COMPAT_SYS_SPU(timerfd)
SYSCALL_SPU(eventfd)

6
include/asm-powerpc/tsi108_irq.h
View File

@@ -26,8 +26,8 @@
* demultiplexing on TSI108EMU/SVB boards.
*/
#ifndef _ASM_PPC_TSI108_IRQ_H
#define _ASM_PPC_TSI108_IRQ_H
#ifndef _ASM_POWERPC_TSI108_IRQ_H
#define _ASM_POWERPC_TSI108_IRQ_H
/*
* Tsi108 interrupts
@@ -121,4 +121,4 @@ typedef enum {
TSI108_IRQ_DIRECTED,
TSI108_IRQ_DISTRIBUTED,
} TSI108_IRQ_MODE;
#endif /* _ASM_PPC_TSI108_IRQ_H */
#endif /* _ASM_POWERPC_TSI108_IRQ_H */

6
include/asm-powerpc/tsi108_pci.h
View File

@@ -18,8 +18,8 @@
* MA 02111-1307 USA
*/
#ifndef _ASM_PPC_TSI108_PCI_H
#define _ASM_PPC_TSI108_PCI_H
#ifndef _ASM_POWERPC_TSI108_PCI_H
#define _ASM_POWERPC_TSI108_PCI_H
#include <asm/tsi108.h>
@@ -42,4 +42,4 @@ extern void tsi108_pci_int_init(struct device_node *node);
extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
extern void tsi108_clear_pci_cfg_error(void);
#endif /* _ASM_PPC_TSI108_PCI_H */
#endif /* _ASM_POWERPC_TSI108_PCI_H */

11
include/asm-powerpc/unistd.h
View File

@@ -1,5 +1,5 @@
#ifndef _ASM_PPC_UNISTD_H_
#define _ASM_PPC_UNISTD_H_
#ifndef _ASM_POWERPC_UNISTD_H_
#define _ASM_POWERPC_UNISTD_H_
/*
* This file contains the system call numbers.
@@ -327,10 +327,13 @@
#define __NR_getcpu 302
#define __NR_epoll_pwait 303
#define __NR_utimensat 304
#define __NR_signalfd 305
#define __NR_timerfd 306
#define __NR_eventfd 307
#ifdef __KERNEL__
#define __NR_syscalls 305
#define __NR_syscalls 308
#define __NR__exit __NR_exit
#define NR_syscalls __NR_syscalls
@@ -381,4 +384,4 @@
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_PPC_UNISTD_H_ */
#endif /* _ASM_POWERPC_UNISTD_H_ */

21
include/asm-s390/unistd.h
View File

@@ -251,8 +251,12 @@
#define __NR_getcpu 311
#define __NR_epoll_pwait 312
#define __NR_utimes 313
#define NR_syscalls 314
/* Number 314 is reserved for new sys_fallocate */
#define __NR_utimensat 315
#define __NR_signalfd 316
#define __NR_timerfd 317
#define __NR_eventfd 318
#define NR_syscalls 319
/*
* There are some system calls that are not present on 64 bit, some
@@ -346,6 +350,19 @@
#ifdef __KERNEL__
#ifndef CONFIG_64BIT
#define __IGNORE_select
#else
#define __IGNORE_time
#endif
/* Ignore NUMA system calls. Not wired up on s390. */
#define __IGNORE_mbind
#define __IGNORE_get_mempolicy
#define __IGNORE_set_mempolicy
#define __IGNORE_migrate_pages
#define __IGNORE_move_pages
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_SYS_ALARM

2
include/asm-sh/dreamcast/sysasic.h
View File

@@ -23,7 +23,7 @@
takes.
*/
#define HW_EVENT_IRQ_BASE OFFCHIP_IRQ_BASE /* 48 */
#define HW_EVENT_IRQ_BASE 48
/* IRQ 13 */
#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */

4
include/asm-sh/kdebug.h
View File

@@ -6,10 +6,6 @@
/* Grossly misnamed. */
enum die_val {
DIE_TRAP,
DIE_PAGE_FAULT,
};
int register_page_fault_notifier(struct notifier_block *nb);
int unregister_page_fault_notifier(struct notifier_block *nb);
#endif /* __ASM_SH_KDEBUG_H */

10
include/asm-sh/landisk/gio.h
View File

@@ -29,16 +29,8 @@
#define GIODRV_IOCGGIODATA4 _IOR(GIODRV_IOC_MAGIC, 6, unsigned long *)
#define GIODRV_IOCSGIOSETADDR _IOW(GIODRV_IOC_MAGIC, 7, unsigned long *)
#define GIODRV_IOCHARDRESET _IO(GIODRV_IOC_MAGIC, 8) /* debugging tool */
#define GIODRV_IOCSGIO_LED _IOW(GIODRV_IOC_MAGIC, 9, unsigned long *)
#define GIODRV_IOCGGIO_LED _IOR(GIODRV_IOC_MAGIC, 10, unsigned long *)
#define GIODRV_IOCSGIO_BUZZER _IOW(GIODRV_IOC_MAGIC, 11, unsigned long *)
#define GIODRV_IOCGGIO_LANDISK _IOR(GIODRV_IOC_MAGIC, 14, unsigned long *)
#define GIODRV_IOCGGIO_BTN _IOR(GIODRV_IOC_MAGIC, 22, unsigned long *)
#define GIODRV_IOCSGIO_BTNPID _IOW(GIODRV_IOC_MAGIC, 23, unsigned long *)
#define GIODRV_IOCGGIO_BTNPID _IOR(GIODRV_IOC_MAGIC, 24, unsigned long *)
#define GIODRV_IOC_MAXNR 8
#define GIO_READ 0x00000000
#define GIO_WRITE 0x00000001

37
include/asm-sh/landisk/iodata_landisk.h
View File

@@ -22,16 +22,6 @@
/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */
#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */
#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */
#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */
#define PA_LCD_DSPCTL 0x00 /* LCD Display ON/OFF Control Offset */
#define PA_LCD_FUNC 0x00 /* LCD Function Set Offset */
#define PA_LCD_CGRAM 0x00 /* LCD Set CGRAM Address Offset */
#define PA_LCD_DDRAM 0x00 /* LCD Set DDRAM Address Offset */
#define PA_LCD_RDFLAG 0x01 /* LCD Read Busy Flag Offset */
#define PA_LCD_WTDATA 0x02 /* LCD Write Datat to RAM Offset */
#define PA_LCD_RDDATA 0x03 /* LCD Read Data from RAM Offset */
#define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
#define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
@@ -45,33 +35,6 @@
#define IRQ_BUTTON 12 /* USL-5P Button IRQ */
#define IRQ_FAULT 13 /* USL-5P Fault IRQ */
#define SHUTDOWN_BTN_MAJOR 99 /* Shutdown button device major no. */
#define SHUTDOWN_LOOP_CNT 5 /* Shutdown button Detection loop */
#define SHUTDOWN_DELAY 200 /* Shutdown button delay value(ms) */
/* added by kogiidena */
/*
* landisk_ledparam
*
* led ------10 -6543210 -6543210 -6543210
* |000000..|0.......|0.......|U.......|
* | HARD |fastblik| blink | on |
*
* led0: power U:update flag
* led1: error
* led2: usb1
* led3: usb2
* led4: usb3
* led5: usb4
* led6: usb5
*
*/
extern int landisk_ledparam; /* from setup.c */
extern int landisk_buzzerparam; /* from setup.c */
extern int landisk_arch; /* from setup.c */
#define __IO_PREFIX landisk
#include <asm/io_generic.h>

5
include/asm-sh/unistd.h
View File

@@ -329,8 +329,11 @@
#define __NR_getcpu 318
#define __NR_epoll_pwait 319
#define __NR_utimensat 320
#define __NR_signalfd 321
#define __NR_timerfd 322
#define __NR_eventfd 323
#define NR_syscalls 321
#define NR_syscalls 324
#ifdef __KERNEL__

38
include/asm-sparc/atomic.h
View File

@@ -2,6 +2,7 @@
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
* Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)
*
* Additions by Keith M Wesolowski (wesolows@foobazco.org) based
* on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
@@ -10,11 +11,48 @@
#ifndef __ARCH_SPARC_ATOMIC__
#define __ARCH_SPARC_ATOMIC__
#include <linux/types.h>
typedef struct { volatile int counter; } atomic_t;
#ifdef __KERNEL__
/* Emulate cmpxchg() the same way we emulate atomics,
* by hashing the object address and indexing into an array
* of spinlocks to get a bit of performance...
*
* See arch/sparc/lib/atomic32.c for implementation.
*
* Cribbed from <asm-parisc/atomic.h>
*/
#define __HAVE_ARCH_CMPXCHG 1
/* bug catcher for when unsupported size is used - won't link */
extern void __cmpxchg_called_with_bad_pointer(void);
/* we only need to support cmpxchg of a u32 on sparc */
extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
/* don't worry...optimizer will get rid of most of this */
static __inline__ unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
{
switch(size) {
case 4:
return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
default:
__cmpxchg_called_with_bad_pointer();
break;
}
return old;
}
#define cmpxchg(ptr,o,n) ({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
(unsigned long)_n_, sizeof(*(ptr))); \
})
#define ATOMIC_INIT(i) { (i) }
extern int __atomic_add_return(int, atomic_t *);

8
include/asm-sparc64/bugs.h
View File

@@ -1,9 +1,8 @@
/* $Id: bugs.h,v 1.1 1996/12/26 13:25:20 davem Exp $
* include/asm-sparc64/bugs.h: Sparc probes for various bugs.
/* bugs.h: Sparc64 probes for various bugs.
*
* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
*/
#include <asm/sstate.h>
extern unsigned long loops_per_jiffy;
@@ -12,4 +11,5 @@ static void __init check_bugs(void)
#ifndef CONFIG_SMP
cpu_data(0).udelay_val = loops_per_jiffy;
#endif
sstate_running();
}

24
include/asm-sparc64/cpudata.h
View File

@@ -17,11 +17,11 @@
typedef struct {
/* Dcache line 1 */
unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
unsigned int __pad0_1;
unsigned int __pad0_2;
unsigned int __pad1;
unsigned int __pad0;
unsigned long clock_tick; /* %tick's per second */
unsigned long udelay_val;
unsigned int __pad1;
unsigned int __pad2;
/* Dcache line 2, rarely used */
unsigned int dcache_size;
@@ -30,8 +30,8 @@ typedef struct {
unsigned int icache_line_size;
unsigned int ecache_size;
unsigned int ecache_line_size;
int core_id;
unsigned int __pad3;
unsigned int __pad4;
} cpuinfo_sparc;
DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
@@ -76,12 +76,18 @@ struct trap_per_cpu {
/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
unsigned int irq_worklist;
unsigned int __pad1;
unsigned long __pad2[3];
unsigned int cpu_mondo_qmask;
unsigned int dev_mondo_qmask;
unsigned int resum_qmask;
unsigned int nonresum_qmask;
unsigned int __pad2[3];
} __attribute__((aligned(64)));
extern struct trap_per_cpu trap_block[NR_CPUS];
extern void init_cur_cpu_trap(struct thread_info *);
extern void setup_tba(void);
extern int ncpus_probed;
extern unsigned long real_hard_smp_processor_id(void);
struct cpuid_patch_entry {
unsigned int addr;
@@ -122,6 +128,10 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
#define TRAP_PER_CPU_TSB_HUGE 0xd0
#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
#define TRAP_PER_CPU_IRQ_WORKLIST 0xe0
#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe4
#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xe8
#define TRAP_PER_CPU_RESUM_QMASK 0xec
#define TRAP_PER_CPU_NONRESUM_QMASK 0xf0
#define TRAP_BLOCK_SZ_SHIFT 8
@@ -192,7 +202,7 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
* the calculations done by the macro mid-stream.
*/
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
ldub [THR + TI_CPU], REG1; \
lduh [THR + TI_CPU], REG1; \
sethi %hi(__per_cpu_shift), REG3; \
sethi %hi(__per_cpu_base), REG2; \
ldx [REG3 + %lo(__per_cpu_shift)], REG3; \

730
include/asm-sparc64/hypervisor.h
View File

@@ -73,6 +73,8 @@
#define HV_ENOTSUPPORTED 13 /* Function not supported */
#define HV_ENOMAP 14 /* No mapping found */
#define HV_ETOOMANY 15 /* Too many items specified */
#define HV_ECHANNEL 16 /* Invalid LDC channel */
#define HV_EBUSY 17 /* Resource busy */
/* mach_exit()
* TRAP: HV_FAST_TRAP
@@ -95,6 +97,10 @@
*/
#define HV_FAST_MACH_EXIT 0x00
#ifndef __ASSEMBLY__
extern void sun4v_mach_exit(unsigned long exit_core);
#endif
/* Domain services. */
/* mach_desc()
@@ -120,7 +126,13 @@
*/
#define HV_FAST_MACH_DESC 0x01
/* mach_exit()
#ifndef __ASSEMBLY__
extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
unsigned long buf_len,
unsigned long *real_buf_len);
#endif
/* mach_sir()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_MACH_SIR
* ERRORS: This service does not return.
@@ -135,53 +147,66 @@
*/
#define HV_FAST_MACH_SIR 0x02
/* mach_set_soft_state()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
* ARG0: software state
* ARG1: software state description pointer
* RET0: status
* ERRORS: EINVAL software state not valid or software state
* description is not NULL terminated
* ENORADDR software state description pointer is not a
* valid real address
* EBADALIGNED software state description is not correctly
* aligned
*
* This allows the guest to report it's soft state to the hypervisor. There
* are two primary components to this state. The first part states whether
* the guest software is running or not. The second containts optional
* details specific to the software.
*
* The software state argument is defined below in HV_SOFT_STATE_*, and
* indicates whether the guest is operating normally or in a transitional
* state.
*
* The software state description argument is a real address of a data buffer
* of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
* terminated 7-bit ASCII string of up to 31 characters not including the
* NULL termination.
*/
#define HV_FAST_MACH_SET_SOFT_STATE 0x03
#define HV_SOFT_STATE_NORMAL 0x01
#define HV_SOFT_STATE_TRANSITION 0x02
#ifndef __ASSEMBLY__
extern void sun4v_mach_sir(void);
#endif
/* mach_get_soft_state()
/* mach_set_watchdog()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
* ARG0: software state description pointer
* FUNCTION: HV_FAST_MACH_SET_WATCHDOG
* ARG0: timeout in milliseconds
* RET0: status
* RET1: software state
* ERRORS: ENORADDR software state description pointer is not a
* valid real address
* EBADALIGNED software state description is not correctly
* aligned
* RET1: time remaining in milliseconds
*
* Retrieve the current value of the guest's software state. The rules
* for the software state pointer are the same as for mach_set_soft_state()
* above.
* A guest uses this API to set a watchdog timer. Once the gues has set
* the timer, it must call the timer service again either to disable or
* postpone the expiration. If the timer expires before being reset or
* disabled, then the hypervisor take a platform specific action leading
* to guest termination within a bounded time period. The platform action
* may include recovery actions such as reporting the expiration to a
* Service Processor, and/or automatically restarting the gues.
*
* The 'timeout' parameter is specified in milliseconds, however the
* implementated granularity is given by the 'watchdog-resolution'
* property in the 'platform' node of the guest's machine description.
* The largest allowed timeout value is specified by the
* 'watchdog-max-timeout' property of the 'platform' node.
*
* If the 'timeout' argument is not zero, the watchdog timer is set to
* expire after a minimum of 'timeout' milliseconds.
*
* If the 'timeout' argument is zero, the watchdog timer is disabled.
*
* If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
* property, the hypervisor leaves the watchdog timer state unchanged,
* and returns a status of EINVAL.
*
* The 'time remaining' return value is valid regardless of whether the
* return status is EOK or EINVAL. A non-zero return value indicates the
* number of milliseconds that were remaining until the timer was to expire.
* If less than one millisecond remains, the return value is '1'. If the
* watchdog timer was disabled at the time of the call, the return value is
* zero.
*
* If the hypervisor cannot support the exact timeout value requested, but
* can support a larger timeout value, the hypervisor may round the actual
* timeout to a value larger than the requested timeout, consequently the
* 'time remaining' return value may be larger than the previously requested
* timeout value.
*
* Any guest OS debugger should be aware that the watchdog service may be in
* use. Consequently, it is recommended that the watchdog service is
* disabled upon debugger entry (e.g. reaching a breakpoint), and then
* re-enabled upon returning to normal execution. The API has been designed
* with this in mind, and the 'time remaining' result of the disable call may
* be used directly as the timeout argument of the re-enable call.
*/
#define HV_FAST_MACH_GET_SOFT_STATE 0x04
#define HV_FAST_MACH_SET_WATCHDOG 0x05
#ifndef __ASSEMBLY__
extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
unsigned long *orig_timeout);
#endif
/* CPU services.
*
@@ -206,8 +231,8 @@
* FUNCTION: HV_FAST_CPU_START
* ARG0: CPU ID
* ARG1: PC
* ARG1: RTBA
* ARG1: target ARG0
* ARG2: RTBA
* ARG3: target ARG0
* RET0: status
* ERRORS: ENOCPU Invalid CPU ID
* EINVAL Target CPU ID is not in the stopped state
@@ -224,6 +249,13 @@
*/
#define HV_FAST_CPU_START 0x10
#ifndef __ASSEMBLY__
extern unsigned long sun4v_cpu_start(unsigned long cpuid,
unsigned long pc,
unsigned long rtba,
unsigned long arg0);
#endif
/* cpu_stop()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_CPU_STOP
@@ -245,6 +277,10 @@
*/
#define HV_FAST_CPU_STOP 0x11
#ifndef __ASSEMBLY__
extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
#endif
/* cpu_yield()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_CPU_YIELD
@@ -588,6 +624,11 @@ struct hv_fault_status {
*/
#define HV_FAST_MMU_TSB_CTX0 0x20
#ifndef __ASSEMBLY__
extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
unsigned long tsb_desc_ra);
#endif
/* mmu_tsb_ctxnon0()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_MMU_TSB_CTXNON0
@@ -694,6 +735,13 @@ struct hv_fault_status {
*/
#define HV_FAST_MMU_MAP_PERM_ADDR 0x25
#ifndef __ASSEMBLY__
extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
unsigned long set_to_zero,
unsigned long tte,
unsigned long flags);
#endif
/* mmu_fault_area_conf()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
@@ -892,6 +940,10 @@ struct hv_fault_status {
*/
#define HV_FAST_TOD_GET 0x50
#ifndef __ASSEMBLY__
extern unsigned long sun4v_tod_get(unsigned long *time);
#endif
/* tod_set()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_TOD_SET
@@ -905,6 +957,10 @@ struct hv_fault_status {
*/
#define HV_FAST_TOD_SET 0x51
#ifndef __ASSEMBLY__
extern unsigned long sun4v_tod_set(unsigned long time);
#endif
/* Console services */
/* con_getchar()
@@ -940,6 +996,107 @@ struct hv_fault_status {
*/
#define HV_FAST_CONS_PUTCHAR 0x61
/* con_read()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_CONS_READ
* ARG0: buffer real address
* ARG1: buffer size in bytes
* RET0: status
* RET1: bytes read or BREAK or HUP
* ERRORS: EWOULDBLOCK No character available.
*
* Reads characters into a buffer from the console device. If no
* character is available then an EWOULDBLOCK error is returned.
* If a character is available, then the returned status is EOK
* and the number of bytes read into the given buffer is provided
* in RET1.
*
* A virtual BREAK is represented by the 64-bit RET1 value -1.
*
* A virtual HUP signal is represented by the 64-bit RET1 value -2.
*
* If BREAK or HUP are indicated, no bytes were read into buffer.
*/
#define HV_FAST_CONS_READ 0x62
/* con_write()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_CONS_WRITE
* ARG0: buffer real address
* ARG1: buffer size in bytes
* RET0: status
* RET1: bytes written
* ERRORS: EWOULDBLOCK Output buffer currently full, would block
*
* Send a characters in buffer to the console device. Breaks must be
* sent using con_putchar().
*/
#define HV_FAST_CONS_WRITE 0x63
#ifndef __ASSEMBLY__
extern long sun4v_con_getchar(long *status);
extern long sun4v_con_putchar(long c);
extern long sun4v_con_read(unsigned long buffer,
unsigned long size,
unsigned long *bytes_read);
extern unsigned long sun4v_con_write(unsigned long buffer,
unsigned long size,
unsigned long *bytes_written);
#endif
/* mach_set_soft_state()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
* ARG0: software state
* ARG1: software state description pointer
* RET0: status
* ERRORS: EINVAL software state not valid or software state
* description is not NULL terminated
* ENORADDR software state description pointer is not a
* valid real address
* EBADALIGNED software state description is not correctly
* aligned
*
* This allows the guest to report it's soft state to the hypervisor. There
* are two primary components to this state. The first part states whether
* the guest software is running or not. The second containts optional
* details specific to the software.
*
* The software state argument is defined below in HV_SOFT_STATE_*, and
* indicates whether the guest is operating normally or in a transitional
* state.
*
* The software state description argument is a real address of a data buffer
* of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
* terminated 7-bit ASCII string of up to 31 characters not including the
* NULL termination.
*/
#define HV_FAST_MACH_SET_SOFT_STATE 0x70
#define HV_SOFT_STATE_NORMAL 0x01
#define HV_SOFT_STATE_TRANSITION 0x02
#ifndef __ASSEMBLY__
extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
unsigned long msg_string_ra);
#endif
/* mach_get_soft_state()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
* ARG0: software state description pointer
* RET0: status
* RET1: software state
* ERRORS: ENORADDR software state description pointer is not a
* valid real address
* EBADALIGNED software state description is not correctly
* aligned
*
* Retrieve the current value of the guest's software state. The rules
* for the software state pointer are the same as for mach_set_soft_state()
* above.
*/
#define HV_FAST_MACH_GET_SOFT_STATE 0x71
/* Trap trace services.
*
* The hypervisor provides a trap tracing capability for privileged
@@ -1331,6 +1488,113 @@ extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
#endif
/* vintr_get_cookie()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_GET_COOKIE
* ARG0: device handle
* ARG1: device ino
* RET0: status
* RET1: cookie
*/
#define HV_FAST_VINTR_GET_COOKIE 0xa7
/* vintr_set_cookie()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_SET_COOKIE
* ARG0: device handle
* ARG1: device ino
* ARG2: cookie
* RET0: status
*/
#define HV_FAST_VINTR_SET_COOKIE 0xa8
/* vintr_get_valid()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_GET_VALID
* ARG0: device handle
* ARG1: device ino
* RET0: status
* RET1: valid state
*/
#define HV_FAST_VINTR_GET_VALID 0xa9
/* vintr_set_valid()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_SET_VALID
* ARG0: device handle
* ARG1: device ino
* ARG2: valid state
* RET0: status
*/
#define HV_FAST_VINTR_SET_VALID 0xaa
/* vintr_get_state()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_GET_STATE
* ARG0: device handle
* ARG1: device ino
* RET0: status
* RET1: state
*/
#define HV_FAST_VINTR_GET_STATE 0xab
/* vintr_set_state()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_SET_STATE
* ARG0: device handle
* ARG1: device ino
* ARG2: state
* RET0: status
*/
#define HV_FAST_VINTR_SET_STATE 0xac
/* vintr_get_target()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_GET_TARGET
* ARG0: device handle
* ARG1: device ino
* RET0: status
* RET1: cpuid
*/
#define HV_FAST_VINTR_GET_TARGET 0xad
/* vintr_set_target()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_VINTR_SET_TARGET
* ARG0: device handle
* ARG1: device ino
* ARG2: cpuid
* RET0: status
*/
#define HV_FAST_VINTR_SET_TARGET 0xae
#ifndef __ASSEMBLY__
extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long *cookie);
extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long cookie);
extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long *valid);
extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long valid);
extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long *state);
extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long state);
extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long *cpuid);
extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long cpuid);
#endif
/* PCI IO services.
*
* See the terminology descriptions in the device interrupt services
@@ -1989,6 +2253,346 @@ extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cp
*/
#define HV_FAST_PCI_MSG_SETVALID 0xd3
/* Logical Domain Channel services. */
#define LDC_CHANNEL_DOWN 0
#define LDC_CHANNEL_UP 1
#define LDC_CHANNEL_RESETTING 2
/* ldc_tx_qconf()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_TX_QCONF
* ARG0: channel ID
* ARG1: real address base of queue
* ARG2: num entries in queue
* RET0: status
*
* Configure transmit queue for the LDC endpoint specified by the
* given channel ID, to be placed at the given real address, and
* be of the given num entries. Num entries must be a power of two.
* The real address base of the queue must be aligned on the queue
* size. Each queue entry is 64-bytes, so for example, a 32 entry
* queue must be aligned on a 2048 byte real address boundary.
*
* Upon configuration of a valid transmit queue the head and tail
* pointers are set to a hypervisor specific identical value indicating
* that the queue initially is empty.
*
* The endpoint's transmit queue is un-configured if num entries is zero.
*
* The maximum number of entries for each queue for a specific cpu may be
* determined from the machine description. A transmit queue may be
* specified even in the event that the LDC is down (peer endpoint has no
* receive queue specified). Transmission will begin as soon as the peer
* endpoint defines a receive queue.
*
* It is recommended that a guest wait for a transmit queue to empty prior
* to reconfiguring it, or un-configuring it. Re or un-configuring of a
* non-empty transmit queue behaves exactly as defined above, however it
* is undefined as to how many of the pending entries in the original queue
* will be delivered prior to the re-configuration taking effect.
* Furthermore, as the queue configuration causes a reset of the head and
* tail pointers there is no way for a guest to determine how many entries
* have been sent after the configuration operation.
*/
#define HV_FAST_LDC_TX_QCONF 0xe0
/* ldc_tx_qinfo()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_TX_QINFO
* ARG0: channel ID
* RET0: status
* RET1: real address base of queue
* RET2: num entries in queue
*
* Return the configuration info for the transmit queue of LDC endpoint
* defined by the given channel ID. The real address is the currently
* defined real address base of the defined queue, and num entries is the
* size of the queue in terms of number of entries.
*
* If the specified channel ID is a valid endpoint number, but no transmit
* queue has been defined this service will return success, but with num
* entries set to zero and the real address will have an undefined value.
*/
#define HV_FAST_LDC_TX_QINFO 0xe1
/* ldc_tx_get_state()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_TX_GET_STATE
* ARG0: channel ID
* RET0: status
* RET1: head offset
* RET2: tail offset
* RET3: channel state
*
* Return the transmit state, and the head and tail queue pointers, for
* the transmit queue of the LDC endpoint defined by the given channel ID.
* The head and tail values are the byte offset of the head and tail
* positions of the transmit queue for the specified endpoint.
*/
#define HV_FAST_LDC_TX_GET_STATE 0xe2
/* ldc_tx_set_qtail()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_TX_SET_QTAIL
* ARG0: channel ID
* ARG1: tail offset
* RET0: status
*
* Update the tail pointer for the transmit queue associated with the LDC
* endpoint defined by the given channel ID. The tail offset specified
* must be aligned on a 64 byte boundary, and calculated so as to increase
* the number of pending entries on the transmit queue. Any attempt to
* decrease the number of pending transmit queue entires is considered
* an invalid tail offset and will result in an EINVAL error.
*
* Since the tail of the transmit queue may not be moved backwards, the
* transmit queue may be flushed by configuring a new transmit queue,
* whereupon the hypervisor will configure the initial transmit head and
* tail pointers to be equal.
*/
#define HV_FAST_LDC_TX_SET_QTAIL 0xe3
/* ldc_rx_qconf()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_RX_QCONF
* ARG0: channel ID
* ARG1: real address base of queue
* ARG2: num entries in queue
* RET0: status
*
* Configure receive queue for the LDC endpoint specified by the
* given channel ID, to be placed at the given real address, and
* be of the given num entries. Num entries must be a power of two.
* The real address base of the queue must be aligned on the queue
* size. Each queue entry is 64-bytes, so for example, a 32 entry
* queue must be aligned on a 2048 byte real address boundary.
*
* The endpoint's transmit queue is un-configured if num entries is zero.
*
* If a valid receive queue is specified for a local endpoint the LDC is
* in the up state for the purpose of transmission to this endpoint.
*
* The maximum number of entries for each queue for a specific cpu may be
* determined from the machine description.
*
* As receive queue configuration causes a reset of the queue's head and
* tail pointers there is no way for a gues to determine how many entries
* have been received between a preceeding ldc_get_rx_state() API call
* and the completion of the configuration operation. It should be noted
* that datagram delivery is not guarenteed via domain channels anyway,
* and therefore any higher protocol should be resilient to datagram
* loss if necessary. However, to overcome this specific race potential
* it is recommended, for example, that a higher level protocol be employed
* to ensure either retransmission, or ensure that no datagrams are pending
* on the peer endpoint's transmit queue prior to the configuration process.
*/
#define HV_FAST_LDC_RX_QCONF 0xe4
/* ldc_rx_qinfo()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_RX_QINFO
* ARG0: channel ID
* RET0: status
* RET1: real address base of queue
* RET2: num entries in queue
*
* Return the configuration info for the receive queue of LDC endpoint
* defined by the given channel ID. The real address is the currently
* defined real address base of the defined queue, and num entries is the
* size of the queue in terms of number of entries.
*
* If the specified channel ID is a valid endpoint number, but no receive
* queue has been defined this service will return success, but with num
* entries set to zero and the real address will have an undefined value.
*/
#define HV_FAST_LDC_RX_QINFO 0xe5
/* ldc_rx_get_state()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_RX_GET_STATE
* ARG0: channel ID
* RET0: status
* RET1: head offset
* RET2: tail offset
* RET3: channel state
*
* Return the receive state, and the head and tail queue pointers, for
* the receive queue of the LDC endpoint defined by the given channel ID.
* The head and tail values are the byte offset of the head and tail
* positions of the receive queue for the specified endpoint.
*/
#define HV_FAST_LDC_RX_GET_STATE 0xe6
/* ldc_rx_set_qhead()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_RX_SET_QHEAD
* ARG0: channel ID
* ARG1: head offset
* RET0: status
*
* Update the head pointer for the receive queue associated with the LDC
* endpoint defined by the given channel ID. The head offset specified
* must be aligned on a 64 byte boundary, and calculated so as to decrease
* the number of pending entries on the receive queue. Any attempt to
* increase the number of pending receive queue entires is considered
* an invalid head offset and will result in an EINVAL error.
*
* The receive queue may be flushed by setting the head offset equal
* to the current tail offset.
*/
#define HV_FAST_LDC_RX_SET_QHEAD 0xe7
/* LDC Map Table Entry. Each slot is defined by a translation table
* entry, as specified by the LDC_MTE_* bits below, and a 64-bit
* hypervisor invalidation cookie.
*/
#define LDC_MTE_PADDR 0x0fffffffffffe000 /* pa[55:13] */
#define LDC_MTE_COPY_W 0x0000000000000400 /* copy write access */
#define LDC_MTE_COPY_R 0x0000000000000200 /* copy read access */
#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access */
#define LDC_MTE_EXEC 0x0000000000000040 /* execute */
#define LDC_MTE_WRITE 0x0000000000000020 /* read */
#define LDC_MTE_READ 0x0000000000000010 /* write */
#define LDC_MTE_SZALL 0x000000000000000f /* page size bits */
#define LDC_MTE_SZ16GB 0x0000000000000007 /* 16GB page */
#define LDC_MTE_SZ2GB 0x0000000000000006 /* 2GB page */
#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page */
#define LDC_MTE_SZ32MB 0x0000000000000004 /* 32MB page */
#define LDC_MTE_SZ4MB 0x0000000000000003 /* 4MB page */
#define LDC_MTE_SZ512K 0x0000000000000002 /* 512K page */
#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
#ifndef __ASSEMBLY__
struct ldc_mtable_entry {
unsigned long mte;
unsigned long cookie;
};
#endif
/* ldc_set_map_table()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_SET_MAP_TABLE
* ARG0: channel ID
* ARG1: table real address
* ARG2: num entries
* RET0: status
*
* Register the MTE table at the given table real address, with the
* specified num entries, for the LDC indicated by the given channel
* ID.
*/
#define HV_FAST_LDC_SET_MAP_TABLE 0xea
/* ldc_get_map_table()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_GET_MAP_TABLE
* ARG0: channel ID
* RET0: status
* RET1: table real address
* RET2: num entries
*
* Return the configuration of the current mapping table registered
* for the given channel ID.
*/
#define HV_FAST_LDC_GET_MAP_TABLE 0xeb
#define LDC_COPY_IN 0
#define LDC_COPY_OUT 1
/* ldc_copy()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_COPY
* ARG0: channel ID
* ARG1: LDC_COPY_* direction code
* ARG2: target real address
* ARG3: local real address
* ARG4: length in bytes
* RET0: status
* RET1: actual length in bytes
*/
#define HV_FAST_LDC_COPY 0xec
#define LDC_MEM_READ 1
#define LDC_MEM_WRITE 2
#define LDC_MEM_EXEC 4
/* ldc_mapin()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_MAPIN
* ARG0: channel ID
* ARG1: cookie
* RET0: status
* RET1: real address
* RET2: LDC_MEM_* permissions
*/
#define HV_FAST_LDC_MAPIN 0xed
/* ldc_unmap()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_UNMAP
* ARG0: real address
* RET0: status
*/
#define HV_FAST_LDC_UNMAP 0xee
/* ldc_revoke()
* TRAP: HV_FAST_TRAP
* FUNCTION: HV_FAST_LDC_REVOKE
* ARG0: cookie
* ARG1: ldc_mtable_entry cookie
* RET0: status
*/
#define HV_FAST_LDC_REVOKE 0xef
#ifndef __ASSEMBLY__
extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
unsigned long ra,
unsigned long num_entries);
extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
unsigned long *ra,
unsigned long *num_entries);
extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
unsigned long *head_off,
unsigned long *tail_off,
unsigned long *chan_state);
extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
unsigned long tail_off);
extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
unsigned long ra,
unsigned long num_entries);
extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
unsigned long *ra,
unsigned long *num_entries);
extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
unsigned long *head_off,
unsigned long *tail_off,
unsigned long *chan_state);
extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
unsigned long head_off);
extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
unsigned long ra,
unsigned long num_entries);
extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
unsigned long *ra,
unsigned long *num_entries);
extern unsigned long sun4v_ldc_copy(unsigned long channel,
unsigned long dir_code,
unsigned long tgt_raddr,
unsigned long lcl_raddr,
unsigned long len,
unsigned long *actual_len);
extern unsigned long sun4v_ldc_mapin(unsigned long channel,
unsigned long cookie,
unsigned long *ra,
unsigned long *perm);
extern unsigned long sun4v_ldc_unmap(unsigned long ra);
extern unsigned long sun4v_ldc_revoke(unsigned long cookie,
unsigned long mte_cookie);
#endif
/* Performance counter services. */
#define HV_PERF_JBUS_PERF_CTRL_REG 0x00
@@ -2121,8 +2725,42 @@ struct hv_mmu_statistics {
#define HV_FAST_MMUSTAT_INFO 0x103
/* Function numbers for HV_CORE_TRAP. */
#define HV_CORE_VER 0x00
#define HV_CORE_SET_VER 0x00
#define HV_CORE_PUTCHAR 0x01
#define HV_CORE_EXIT 0x02
#define HV_CORE_GET_VER 0x03
/* Hypervisor API groups for use with HV_CORE_SET_VER and
* HV_CORE_GET_VER.
*/
#define HV_GRP_SUN4V 0x0000
#define HV_GRP_CORE 0x0001
#define HV_GRP_INTR 0x0002
#define HV_GRP_SOFT_STATE 0x0003
#define HV_GRP_PCI 0x0100
#define HV_GRP_LDOM 0x0101
#define HV_GRP_SVC_CHAN 0x0102
#define HV_GRP_NCS 0x0103
#define HV_GRP_NIAG_PERF 0x0200
#define HV_GRP_FIRE_PERF 0x0201
#define HV_GRP_DIAG 0x0300
#ifndef __ASSEMBLY__
extern unsigned long sun4v_get_version(unsigned long group,
unsigned long *major,
unsigned long *minor);
extern unsigned long sun4v_set_version(unsigned long group,
unsigned long major,
unsigned long minor,
unsigned long *actual_minor);
extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
unsigned long *minor);
extern void sun4v_hvapi_unregister(unsigned long group);
extern int sun4v_hvapi_get(unsigned long group,
unsigned long *major,
unsigned long *minor);
extern void sun4v_hvapi_init(void);
#endif
#endif /* !(_SPARC64_HYPERVISOR_H) */

1
include/asm-sparc64/kdebug.h
View File

@@ -32,7 +32,6 @@ enum die_val {
DIE_TRAP,
DIE_TRAP_TL1,
DIE_CALL,
DIE_PAGE_FAULT,
};
#endif

39
include/asm-sparc64/mdesc.h Normal file
View File

@@ -0,0 +1,39 @@
#ifndef _SPARC64_MDESC_H
#define _SPARC64_MDESC_H
#include <linux/types.h>
#include <asm/prom.h>
struct mdesc_node;
struct mdesc_arc {
const char *name;
struct mdesc_node *arc;
};
struct mdesc_node {
const char *name;
u64 node;
unsigned int unique_id;
unsigned int num_arcs;
struct property *properties;
struct mdesc_node *hash_next;
struct mdesc_node *allnodes_next;
struct mdesc_arc arcs[0];
};
extern struct mdesc_node *md_find_node_by_name(struct mdesc_node *from,
const char *name);
#define md_for_each_node_by_name(__mn, __name) \
for (__mn = md_find_node_by_name(NULL, __name); __mn; \
__mn = md_find_node_by_name(__mn, __name))
extern struct property *md_find_property(const struct mdesc_node *mp,
const char *name,
int *lenp);
extern const void *md_get_property(const struct mdesc_node *mp,
const char *name,
int *lenp);
extern void sun4v_mdesc_init(void);
#endif

7
include/asm-sparc64/oplib.h
View File

@@ -316,11 +316,8 @@ extern int prom_setprop(int node, const char *prop_name, char *prop_value,
extern int prom_pathtoinode(const char *path);
extern int prom_inst2pkg(int);
/* CPU probing helpers. */
struct device_node;
int cpu_find_by_instance(int instance, struct device_node **dev_node, int *mid);
int cpu_find_by_mid(int mid, struct device_node **prom_node);
extern int prom_service_exists(const char *service_name);
extern void prom_sun4v_guest_soft_state(void);
/* Client interface level routines. */
extern void prom_set_trap_table(unsigned long tba);

4
include/asm-sparc64/percpu.h
View File

@@ -5,7 +5,8 @@
#ifdef CONFIG_SMP
extern void setup_per_cpu_areas(void);
#define setup_per_cpu_areas() do { } while (0)
extern void real_setup_per_cpu_areas(void);
extern unsigned long __per_cpu_base;
extern unsigned long __per_cpu_shift;
@@ -34,6 +35,7 @@ do { \
} while (0)
#else /* ! SMP */
#define real_setup_per_cpu_areas() do { } while (0)
#define DEFINE_PER_CPU(type, name) \
__typeof__(type) per_cpu__##name

1
include/asm-sparc64/prom.h
View File

@@ -90,6 +90,7 @@ extern struct device_node *of_find_compatible_node(struct device_node *from,
const char *type, const char *compat);
extern struct device_node *of_find_node_by_path(const char *path);
extern struct device_node *of_find_node_by_phandle(phandle handle);
extern struct device_node *of_find_node_by_cpuid(int cpuid);
extern struct device_node *of_get_parent(const struct device_node *node);
extern struct device_node *of_get_next_child(const struct device_node *node,
struct device_node *prev);

4
include/asm-sparc64/smp.h
View File

@@ -41,7 +41,7 @@ extern cpumask_t cpu_sibling_map[NR_CPUS];
extern int hard_smp_processor_id(void);
#define raw_smp_processor_id() (current_thread_info()->cpu)
extern void smp_setup_cpu_possible_map(void);
extern void smp_fill_in_sib_core_maps(void);
extern unsigned char boot_cpu_id;
#endif /* !(__ASSEMBLY__) */
@@ -49,7 +49,7 @@ extern unsigned char boot_cpu_id;
#else
#define hard_smp_processor_id() 0
#define smp_setup_cpu_possible_map() do { } while (0)
#define smp_fill_in_sib_core_maps() do { } while (0)
#define boot_cpu_id (0)
#endif /* !(CONFIG_SMP) */

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