Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver specific changes from Arnd Bergmann: - Updates to the ux500 cpufreq code - Moving the u300 DMA controller driver to drivers/dma - Moving versatile express drivers out of arch/arm for sharing with arch/arm64 - Device tree bindings for the OMAP General Purpose Memory Controller * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits) ARM: OMAP2+: gpmc: Add device tree documentation for elm handle ARM: OMAP2+: gpmc: add DT bindings for OneNAND ARM: OMAP2+: gpmc-onenand: drop __init annotation mtd: omap-onenand: pass device_node in platform data ARM: OMAP2+: Prevent potential crash if GPMC probe fails ARM: OMAP2+: gpmc: Remove unneeded of_node_put() arm: Move sp810.h to include/linux/amba/ ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs ARM: OMAP: gpmc-nand: drop __init annotation mtd: omap-nand: pass device_node in platform data ARM: OMAP: gpmc: don't create devices from initcall on DT dma: coh901318: cut down on platform data abstraction dma: coh901318: merge header files dma: coh901318: push definitions into driver dma: coh901318: push header down into the DMA subsystem dma: coh901318: skip hard-coded addresses dma: coh901318: remove hardcoded target addresses dma: coh901318: push platform data into driver dma: coh901318: create a proper platform data file ...
This commit is contained in:
Linus Torvalds
@@ -1,64 +0,0 @@
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/*
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* arch/arm/include/asm/hardware/sp810.h
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*
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* ARM PrimeXsys System Controller SP810 header file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_SP810_H
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#define __ASM_ARM_SP810_H
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#include <linux/io.h>
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/* sysctl registers offset */
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#define SCCTRL 0x000
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#define SCSYSSTAT 0x004
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#define SCIMCTRL 0x008
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#define SCIMSTAT 0x00C
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#define SCXTALCTRL 0x010
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#define SCPLLCTRL 0x014
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#define SCPLLFCTRL 0x018
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#define SCPERCTRL0 0x01C
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#define SCPERCTRL1 0x020
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#define SCPEREN 0x024
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#define SCPERDIS 0x028
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#define SCPERCLKEN 0x02C
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#define SCPERSTAT 0x030
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#define SCSYSID0 0xEE0
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#define SCSYSID1 0xEE4
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#define SCSYSID2 0xEE8
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#define SCSYSID3 0xEEC
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#define SCITCR 0xF00
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#define SCITIR0 0xF04
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#define SCITIR1 0xF08
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#define SCITOR 0xF0C
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#define SCCNTCTRL 0xF10
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#define SCCNTDATA 0xF14
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#define SCCNTSTEP 0xF18
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#define SCPERIPHID0 0xFE0
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#define SCPERIPHID1 0xFE4
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#define SCPERIPHID2 0xFE8
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#define SCPERIPHID3 0xFEC
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#define SCPCELLID0 0xFF0
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#define SCPCELLID1 0xFF4
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#define SCPCELLID2 0xFF8
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#define SCPCELLID3 0xFFC
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#define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2))
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static inline void sysctl_soft_reset(void __iomem *base)
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{
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/* switch to slow mode */
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writel(0x2, base + SCCTRL);
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/* writing any value to SCSYSSTAT reg will reset system */
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writel(0, base + SCSYSSTAT);
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}
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#endif /* __ASM_ARM_SP810_H */
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@@ -89,20 +89,21 @@ static int omap2_nand_gpmc_retime(
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return 0;
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}
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static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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{
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/* support only OMAP3 class */
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if (!cpu_is_omap34xx()) {
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if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
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pr_err("BCH ecc is not supported on this CPU\n");
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return 0;
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}
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/*
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* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
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* Other chips may be added if confirmed to work.
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* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
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* and AM33xx derivates. Other chips may be added if confirmed to work.
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*/
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if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
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(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
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(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
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(!soc_is_am33xx())) {
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pr_err("BCH 4-bit mode is not supported on this CPU\n");
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return 0;
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}
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@@ -110,8 +111,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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return 1;
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}
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int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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struct gpmc_timings *gpmc_t)
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int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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struct gpmc_timings *gpmc_t)
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{
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int err = 0;
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struct device *dev = &gpmc_nand_device.dev;
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@@ -356,7 +356,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
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return ret;
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}
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void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
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void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
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{
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int err;
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@@ -25,6 +25,10 @@
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_mtd.h>
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#include <linux/of_device.h>
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#include <linux/mtd/nand.h>
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#include <linux/platform_data/mtd-nand-omap2.h>
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@@ -34,6 +38,8 @@
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#include "common.h"
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#include "omap_device.h"
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#include "gpmc.h"
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#include "gpmc-nand.h"
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#include "gpmc-onenand.h"
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#define DEVICE_NAME "omap-gpmc"
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@@ -145,7 +151,8 @@ static unsigned gpmc_irq_start;
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static struct resource gpmc_mem_root;
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static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
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static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
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/* Define chip-selects as reserved by default until probe completes */
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static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
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static struct device *gpmc_dev;
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static int gpmc_irq;
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static resource_size_t phys_base, mem_size;
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@@ -1118,9 +1125,216 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
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/* TODO: remove, see function definition */
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gpmc_convert_ps_to_ns(gpmc_t);
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/* Now the GPMC is initialised, unreserve the chip-selects */
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gpmc_cs_map = 0;
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return 0;
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}
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#ifdef CONFIG_OF
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static struct of_device_id gpmc_dt_ids[] = {
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{ .compatible = "ti,omap2420-gpmc" },
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{ .compatible = "ti,omap2430-gpmc" },
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{ .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
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{ .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
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{ .compatible = "ti,am3352-gpmc" }, /* am335x devices */
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
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static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
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struct gpmc_timings *gpmc_t)
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{
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u32 val;
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memset(gpmc_t, 0, sizeof(*gpmc_t));
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/* minimum clock period for syncronous mode */
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if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
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gpmc_t->sync_clk = val;
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/* chip select timtings */
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if (!of_property_read_u32(np, "gpmc,cs-on", &val))
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gpmc_t->cs_on = val;
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if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
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gpmc_t->cs_rd_off = val;
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if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
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gpmc_t->cs_wr_off = val;
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/* ADV signal timings */
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if (!of_property_read_u32(np, "gpmc,adv-on", &val))
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gpmc_t->adv_on = val;
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if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
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gpmc_t->adv_rd_off = val;
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if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
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gpmc_t->adv_wr_off = val;
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/* WE signal timings */
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if (!of_property_read_u32(np, "gpmc,we-on", &val))
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gpmc_t->we_on = val;
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if (!of_property_read_u32(np, "gpmc,we-off", &val))
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gpmc_t->we_off = val;
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/* OE signal timings */
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if (!of_property_read_u32(np, "gpmc,oe-on", &val))
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gpmc_t->oe_on = val;
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if (!of_property_read_u32(np, "gpmc,oe-off", &val))
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gpmc_t->oe_off = val;
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/* access and cycle timings */
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if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
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gpmc_t->page_burst_access = val;
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if (!of_property_read_u32(np, "gpmc,access", &val))
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gpmc_t->access = val;
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if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
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gpmc_t->rd_cycle = val;
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if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
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gpmc_t->wr_cycle = val;
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/* only for OMAP3430 */
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if (!of_property_read_u32(np, "gpmc,wr-access", &val))
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gpmc_t->wr_access = val;
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if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
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gpmc_t->wr_data_mux_bus = val;
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}
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#ifdef CONFIG_MTD_NAND
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static const char * const nand_ecc_opts[] = {
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[OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
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[OMAP_ECC_HAMMING_CODE_HW] = "hw",
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[OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
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[OMAP_ECC_BCH4_CODE_HW] = "bch4",
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[OMAP_ECC_BCH8_CODE_HW] = "bch8",
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};
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static int gpmc_probe_nand_child(struct platform_device *pdev,
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struct device_node *child)
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{
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u32 val;
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const char *s;
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struct gpmc_timings gpmc_t;
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struct omap_nand_platform_data *gpmc_nand_data;
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if (of_property_read_u32(child, "reg", &val) < 0) {
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dev_err(&pdev->dev, "%s has no 'reg' property\n",
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child->full_name);
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return -ENODEV;
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}
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gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
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GFP_KERNEL);
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if (!gpmc_nand_data)
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return -ENOMEM;
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gpmc_nand_data->cs = val;
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gpmc_nand_data->of_node = child;
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if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
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for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
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if (!strcasecmp(s, nand_ecc_opts[val])) {
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gpmc_nand_data->ecc_opt = val;
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break;
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}
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val = of_get_nand_bus_width(child);
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if (val == 16)
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gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
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gpmc_read_timings_dt(child, &gpmc_t);
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gpmc_nand_init(gpmc_nand_data, &gpmc_t);
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return 0;
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}
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#else
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static int gpmc_probe_nand_child(struct platform_device *pdev,
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struct device_node *child)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_MTD_ONENAND
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static int gpmc_probe_onenand_child(struct platform_device *pdev,
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struct device_node *child)
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{
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u32 val;
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struct omap_onenand_platform_data *gpmc_onenand_data;
|
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if (of_property_read_u32(child, "reg", &val) < 0) {
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dev_err(&pdev->dev, "%s has no 'reg' property\n",
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child->full_name);
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return -ENODEV;
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}
|
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|
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gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
|
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GFP_KERNEL);
|
||||
if (!gpmc_onenand_data)
|
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return -ENOMEM;
|
||||
|
||||
gpmc_onenand_data->cs = val;
|
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gpmc_onenand_data->of_node = child;
|
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gpmc_onenand_data->dma_channel = -1;
|
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|
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if (!of_property_read_u32(child, "dma-channel", &val))
|
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gpmc_onenand_data->dma_channel = val;
|
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gpmc_onenand_init(gpmc_onenand_data);
|
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|
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return 0;
|
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}
|
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#else
|
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static int gpmc_probe_onenand_child(struct platform_device *pdev,
|
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struct device_node *child)
|
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{
|
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return 0;
|
||||
}
|
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#endif
|
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|
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static int gpmc_probe_dt(struct platform_device *pdev)
|
||||
{
|
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int ret;
|
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struct device_node *child;
|
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const struct of_device_id *of_id =
|
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of_match_device(gpmc_dt_ids, &pdev->dev);
|
||||
|
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if (!of_id)
|
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return 0;
|
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|
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for_each_node_by_name(child, "nand") {
|
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ret = gpmc_probe_nand_child(pdev, child);
|
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if (ret < 0) {
|
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of_node_put(child);
|
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return ret;
|
||||
}
|
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}
|
||||
|
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for_each_node_by_name(child, "onenand") {
|
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ret = gpmc_probe_onenand_child(pdev, child);
|
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if (ret < 0) {
|
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of_node_put(child);
|
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return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#else
|
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static int gpmc_probe_dt(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int gpmc_probe(struct platform_device *pdev)
|
||||
{
|
||||
int rc;
|
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@@ -1172,6 +1386,14 @@ static int gpmc_probe(struct platform_device *pdev)
|
||||
if (IS_ERR_VALUE(gpmc_setup_irq()))
|
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dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
|
||||
|
||||
rc = gpmc_probe_dt(pdev);
|
||||
if (rc < 0) {
|
||||
clk_disable_unprepare(gpmc_l3_clk);
|
||||
clk_put(gpmc_l3_clk);
|
||||
dev_err(gpmc_dev, "failed to probe DT parameters\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1189,6 +1411,7 @@ static struct platform_driver gpmc_driver = {
|
||||
.driver = {
|
||||
.name = DEVICE_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(gpmc_dt_ids),
|
||||
},
|
||||
};
|
||||
|
||||
@@ -1212,6 +1435,13 @@ static int __init omap_gpmc_init(void)
|
||||
struct platform_device *pdev;
|
||||
char *oh_name = "gpmc";
|
||||
|
||||
/*
|
||||
* if the board boots up with a populated DT, do not
|
||||
* manually add the device from this initcall
|
||||
*/
|
||||
if (of_have_populated_dt())
|
||||
return -ENODEV;
|
||||
|
||||
oh = omap_hwmod_lookup(oh_name);
|
||||
if (!oh) {
|
||||
pr_err("Could not look up %s\n", oh_name);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,60 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* arch/arm/mach-u300/include/mach/dma_channels.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2007-2012 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Map file for the U300 dma driver.
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef DMA_CHANNELS_H
|
||||
#define DMA_CHANNELS_H
|
||||
|
||||
#define U300_DMA_MSL_TX_0 0
|
||||
#define U300_DMA_MSL_TX_1 1
|
||||
#define U300_DMA_MSL_TX_2 2
|
||||
#define U300_DMA_MSL_TX_3 3
|
||||
#define U300_DMA_MSL_TX_4 4
|
||||
#define U300_DMA_MSL_TX_5 5
|
||||
#define U300_DMA_MSL_TX_6 6
|
||||
#define U300_DMA_MSL_RX_0 7
|
||||
#define U300_DMA_MSL_RX_1 8
|
||||
#define U300_DMA_MSL_RX_2 9
|
||||
#define U300_DMA_MSL_RX_3 10
|
||||
#define U300_DMA_MSL_RX_4 11
|
||||
#define U300_DMA_MSL_RX_5 12
|
||||
#define U300_DMA_MSL_RX_6 13
|
||||
#define U300_DMA_MMCSD_RX_TX 14
|
||||
#define U300_DMA_MSPRO_TX 15
|
||||
#define U300_DMA_MSPRO_RX 16
|
||||
#define U300_DMA_UART0_TX 17
|
||||
#define U300_DMA_UART0_RX 18
|
||||
#define U300_DMA_APEX_TX 19
|
||||
#define U300_DMA_APEX_RX 20
|
||||
#define U300_DMA_PCM_I2S0_TX 21
|
||||
#define U300_DMA_PCM_I2S0_RX 22
|
||||
#define U300_DMA_PCM_I2S1_TX 23
|
||||
#define U300_DMA_PCM_I2S1_RX 24
|
||||
#define U300_DMA_XGAM_CDI 25
|
||||
#define U300_DMA_XGAM_PDI 26
|
||||
#define U300_DMA_SPI_TX 27
|
||||
#define U300_DMA_SPI_RX 28
|
||||
#define U300_DMA_GENERAL_PURPOSE_0 29
|
||||
#define U300_DMA_GENERAL_PURPOSE_1 30
|
||||
#define U300_DMA_GENERAL_PURPOSE_2 31
|
||||
#define U300_DMA_GENERAL_PURPOSE_3 32
|
||||
#define U300_DMA_GENERAL_PURPOSE_4 33
|
||||
#define U300_DMA_GENERAL_PURPOSE_5 34
|
||||
#define U300_DMA_GENERAL_PURPOSE_6 35
|
||||
#define U300_DMA_GENERAL_PURPOSE_7 36
|
||||
#define U300_DMA_GENERAL_PURPOSE_8 37
|
||||
#define U300_DMA_UART1_TX 38
|
||||
#define U300_DMA_UART1_RX 39
|
||||
|
||||
#define U300_DMA_DEVICE_CHANNELS 32
|
||||
#define U300_DMA_CHANNELS 40
|
||||
|
||||
|
||||
#endif /* DMA_CHANNELS_H */
|
||||
@@ -1,267 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* include/linux/coh901318.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* DMA driver for COH 901 318
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef COH901318_H
|
||||
#define COH901318_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#define MAX_DMA_PACKET_SIZE_SHIFT 11
|
||||
#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
|
||||
|
||||
/**
|
||||
* struct coh901318_lli - linked list item for DMAC
|
||||
* @control: control settings for DMAC
|
||||
* @src_addr: transfer source address
|
||||
* @dst_addr: transfer destination address
|
||||
* @link_addr: physical address to next lli
|
||||
* @virt_link_addr: virtual address of next lli (only used by pool_free)
|
||||
* @phy_this: physical address of current lli (only used by pool_free)
|
||||
*/
|
||||
struct coh901318_lli {
|
||||
u32 control;
|
||||
dma_addr_t src_addr;
|
||||
dma_addr_t dst_addr;
|
||||
dma_addr_t link_addr;
|
||||
|
||||
void *virt_link_addr;
|
||||
dma_addr_t phy_this;
|
||||
};
|
||||
/**
|
||||
* struct coh901318_params - parameters for DMAC configuration
|
||||
* @config: DMA config register
|
||||
* @ctrl_lli_last: DMA control register for the last lli in the list
|
||||
* @ctrl_lli: DMA control register for an lli
|
||||
* @ctrl_lli_chained: DMA control register for a chained lli
|
||||
*/
|
||||
struct coh901318_params {
|
||||
u32 config;
|
||||
u32 ctrl_lli_last;
|
||||
u32 ctrl_lli;
|
||||
u32 ctrl_lli_chained;
|
||||
};
|
||||
/**
|
||||
* struct coh_dma_channel - dma channel base
|
||||
* @name: ascii name of dma channel
|
||||
* @number: channel id number
|
||||
* @desc_nbr_max: number of preallocated descriptors
|
||||
* @priority_high: prio of channel, 0 low otherwise high.
|
||||
* @param: configuration parameters
|
||||
* @dev_addr: physical address of periphal connected to channel
|
||||
*/
|
||||
struct coh_dma_channel {
|
||||
const char name[32];
|
||||
const int number;
|
||||
const int desc_nbr_max;
|
||||
const int priority_high;
|
||||
const struct coh901318_params param;
|
||||
const dma_addr_t dev_addr;
|
||||
};
|
||||
|
||||
/**
|
||||
* dma_access_memory_state_t - register dma for memory access
|
||||
*
|
||||
* @dev: The dma device
|
||||
* @active: 1 means dma intends to access memory
|
||||
* 0 means dma wont access memory
|
||||
*/
|
||||
typedef void (*dma_access_memory_state_t)(struct device *dev,
|
||||
bool active);
|
||||
|
||||
/**
|
||||
* struct powersave - DMA power save structure
|
||||
* @lock: lock protecting data in this struct
|
||||
* @started_channels: bit mask indicating active dma channels
|
||||
*/
|
||||
struct powersave {
|
||||
spinlock_t lock;
|
||||
u64 started_channels;
|
||||
};
|
||||
/**
|
||||
* struct coh901318_platform - platform arch structure
|
||||
* @chans_slave: specifying dma slave channels
|
||||
* @chans_memcpy: specifying dma memcpy channels
|
||||
* @access_memory_state: requesting DMA memory access (on / off)
|
||||
* @chan_conf: dma channel configurations
|
||||
* @max_channels: max number of dma chanenls
|
||||
*/
|
||||
struct coh901318_platform {
|
||||
const int *chans_slave;
|
||||
const int *chans_memcpy;
|
||||
const dma_access_memory_state_t access_memory_state;
|
||||
const struct coh_dma_channel *chan_conf;
|
||||
const int max_channels;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_COH901318
|
||||
/**
|
||||
* coh901318_filter_id() - DMA channel filter function
|
||||
* @chan: dma channel handle
|
||||
* @chan_id: id of dma channel to be filter out
|
||||
*
|
||||
* In dma_request_channel() it specifies what channel id to be requested
|
||||
*/
|
||||
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
|
||||
#else
|
||||
static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* DMA Controller - this access the static mappings of the coh901318 dma.
|
||||
*
|
||||
*/
|
||||
|
||||
#define COH901318_MOD32_MASK (0x1F)
|
||||
#define COH901318_WORD_MASK (0xFFFFFFFF)
|
||||
/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_INT_STATUS1 (0x0000)
|
||||
#define COH901318_INT_STATUS2 (0x0004)
|
||||
/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_TC_INT_STATUS1 (0x0008)
|
||||
#define COH901318_TC_INT_STATUS2 (0x000C)
|
||||
/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
|
||||
#define COH901318_TC_INT_CLEAR1 (0x0010)
|
||||
#define COH901318_TC_INT_CLEAR2 (0x0014)
|
||||
/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
|
||||
#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
|
||||
/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_BE_INT_STATUS1 (0x0020)
|
||||
#define COH901318_BE_INT_STATUS2 (0x0024)
|
||||
/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
|
||||
#define COH901318_BE_INT_CLEAR1 (0x0028)
|
||||
#define COH901318_BE_INT_CLEAR2 (0x002C)
|
||||
/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
|
||||
#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
|
||||
|
||||
/*
|
||||
* CX_CFG - Channel Configuration Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_CFG (0x0100)
|
||||
#define COH901318_CX_CFG_SPACING (0x04)
|
||||
/* Channel enable activates tha dma job */
|
||||
#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
|
||||
#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
|
||||
/* Request Mode */
|
||||
#define COH901318_CX_CFG_RM_MASK (0x00000006)
|
||||
#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
|
||||
#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
|
||||
#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
|
||||
#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
|
||||
#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
|
||||
/* Linked channel request field. RM must == 11 */
|
||||
#define COH901318_CX_CFG_LCRF_SHIFT 3
|
||||
#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
|
||||
#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
|
||||
/* Terminal Counter Interrupt Request Mask */
|
||||
#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
|
||||
#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
|
||||
/* Bus Error interrupt Mask */
|
||||
#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
|
||||
#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
|
||||
|
||||
/*
|
||||
* CX_STAT - Channel Status Registers 32bit (R/-)
|
||||
*/
|
||||
#define COH901318_CX_STAT (0x0200)
|
||||
#define COH901318_CX_STAT_SPACING (0x04)
|
||||
#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
|
||||
#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
|
||||
#define COH901318_CX_STAT_ACTIVE (0x00000002)
|
||||
#define COH901318_CX_STAT_ENABLED (0x00000001)
|
||||
|
||||
/*
|
||||
* CX_CTRL - Channel Control Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_CTRL (0x0400)
|
||||
#define COH901318_CX_CTRL_SPACING (0x10)
|
||||
/* Transfer Count Enable */
|
||||
#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
|
||||
#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
|
||||
/* Transfer Count Value 0 - 4095 */
|
||||
#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
|
||||
/* Burst count */
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
|
||||
/* Source bus size */
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
|
||||
/* Source address increment */
|
||||
#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
|
||||
#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
|
||||
/* Destination Bus Size */
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
|
||||
/* Destination address increment */
|
||||
#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
|
||||
#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
|
||||
/* Master Mode (Master2 is only connected to MSL) */
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
|
||||
/* Terminal Count flag to PER enable */
|
||||
#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
|
||||
#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
|
||||
/* Terminal Count flags to CPU enable */
|
||||
#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
|
||||
#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
|
||||
/* Hand shake to peripheral */
|
||||
#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
|
||||
#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
|
||||
#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
|
||||
#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
|
||||
/* DMA mode */
|
||||
#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
|
||||
#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
|
||||
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
|
||||
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
|
||||
/* Primary Request Data Destination */
|
||||
#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
|
||||
#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
|
||||
#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
|
||||
|
||||
/*
|
||||
* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_SRC_ADDR (0x0404)
|
||||
#define COH901318_CX_SRC_ADDR_SPACING (0x10)
|
||||
|
||||
/*
|
||||
* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
|
||||
*/
|
||||
#define COH901318_CX_DST_ADDR (0x0408)
|
||||
#define COH901318_CX_DST_ADDR_SPACING (0x10)
|
||||
|
||||
/*
|
||||
* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_LNK_ADDR (0x040C)
|
||||
#define COH901318_CX_LNK_ADDR_SPACING (0x10)
|
||||
#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
|
||||
#endif /* COH901318_H */
|
||||
@@ -10,9 +10,8 @@
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/platform_data/dma-coh901318.h>
|
||||
#include <linux/err.h>
|
||||
#include <mach/coh901318.h>
|
||||
#include "dma_channels.h"
|
||||
|
||||
/*
|
||||
* The following is for the actual devices on the SSP/SPI bus
|
||||
|
||||
@@ -11,8 +11,8 @@
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
#include <linux/amba/sp810.h>
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/hardware/sp810.h>
|
||||
#include <mach/spear.h>
|
||||
#include <mach/generic.h>
|
||||
|
||||
|
||||
Reference in New Issue
Block a user