[SCSI] qla2xxx: IDC implementation for ISP83xx.
Signed-off-by: Santosh Vernekar <santosh.vernekar@qlogic.com> Signed-off-by: Saurav Kashyap <saurav.kashyap@qlogic.com> Signed-off-by: Chad Dupuis <chad.dupuis@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Santosh Vernekar
committed by
James Bottomley
James Bottomley
parent
40129a4c6e
commit
7d613ac6ac
@@ -114,6 +114,82 @@
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#define WRT_REG_WORD(addr, data) writew(data,addr)
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#define WRT_REG_DWORD(addr, data) writel(data,addr)
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/*
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* ISP83XX specific remote register addresses
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*/
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#define QLA83XX_LED_PORT0 0x00201320
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#define QLA83XX_LED_PORT1 0x00201328
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#define QLA83XX_IDC_DEV_STATE 0x22102384
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#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
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#define QLA83XX_IDC_MINOR_VERSION 0x22102398
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#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
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#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
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#define QLA83XX_IDC_CONTROL 0x22102390
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#define QLA83XX_IDC_AUDIT 0x22102394
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#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
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#define QLA83XX_DRIVER_LOCKID 0x22102104
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#define QLA83XX_DRIVER_LOCK 0x8111c028
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#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
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#define QLA83XX_FLASH_LOCKID 0x22102100
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#define QLA83XX_FLASH_LOCK 0x8111c010
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#define QLA83XX_FLASH_UNLOCK 0x8111c014
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#define QLA83XX_DEV_PARTINFO1 0x221023e0
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#define QLA83XX_DEV_PARTINFO2 0x221023e4
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#define QLA83XX_FW_HEARTBEAT 0x221020b0
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#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
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#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
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/* 83XX: Macros defining 8200 AEN Reason codes */
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#define IDC_DEVICE_STATE_CHANGE BIT_0
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#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
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#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
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#define IDC_HEARTBEAT_FAILURE BIT_3
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/* 83XX: Macros defining 8200 AEN Error-levels */
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#define ERR_LEVEL_NON_FATAL 0x1
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#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
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#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
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/* 83XX: Macros for IDC Version */
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#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
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#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
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/* 83XX: Macros for scheduling dpc tasks */
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#define QLA83XX_NIC_CORE_RESET 0x1
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#define QLA83XX_IDC_STATE_HANDLER 0x2
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#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
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/* 83XX: Macros for defining IDC-Control bits */
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#define QLA83XX_IDC_RESET_DISABLED BIT_0
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#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
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/* 83XX: Macros for different timeouts */
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#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
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#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
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#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
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/* 83XX: Macros for defining class in DEV-Partition Info register */
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#define QLA83XX_CLASS_TYPE_NONE 0x0
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#define QLA83XX_CLASS_TYPE_NIC 0x1
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#define QLA83XX_CLASS_TYPE_FCOE 0x2
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#define QLA83XX_CLASS_TYPE_ISCSI 0x3
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/* 83XX: Macros for IDC Lock-Recovery stages */
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#define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
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* lock-recovery
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*/
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#define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
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/* 83XX: Macros for IDC Audit type */
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#define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
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* dev-state change to NEED-RESET
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* or NEED-QUIESCENT
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*/
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#define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
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* reset-recovery completion is
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* second
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*/
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/*
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* The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
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* 133Mhz slot.
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@@ -596,6 +672,9 @@ typedef struct {
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#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
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#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
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/* 83XX FCoE specific */
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#define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
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/* ISP mailbox loopback echo diagnostic error code */
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#define MBS_LB_RESET 0x17
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/*
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@@ -2523,11 +2602,12 @@ struct qla_hw_data {
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uint32_t disable_msix_handshake :1;
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uint32_t fcp_prio_enabled :1;
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uint32_t isp82xx_fw_hung:1;
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uint32_t nic_core_hung:1;
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uint32_t quiesce_owner:1;
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uint32_t thermal_supported:1;
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uint32_t isp82xx_reset_hdlr_active:1;
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uint32_t isp82xx_reset_owner:1;
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uint32_t nic_core_reset_hdlr_active:1;
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uint32_t nic_core_reset_owner:1;
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uint32_t isp82xx_no_md_cap:1;
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uint32_t host_shutting_down:1;
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/* 30 bits */
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@@ -2912,8 +2992,8 @@ struct qla_hw_data {
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unsigned long mn_win_crb;
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unsigned long ms_win_crb;
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int qdr_sn_window;
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uint32_t nx_dev_init_timeout;
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uint32_t nx_reset_timeout;
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uint32_t fcoe_dev_init_timeout;
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uint32_t fcoe_reset_timeout;
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rwlock_t hw_lock;
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uint16_t portnum; /* port number */
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int link_width;
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@@ -2935,6 +3015,19 @@ struct qla_hw_data {
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uint32_t md_dump_size;
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void *loop_id_map;
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/* QLA83XX IDC specific fields */
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uint32_t idc_audit_ts;
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/* DPC low-priority workqueue */
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struct workqueue_struct *dpc_lp_wq;
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struct work_struct idc_aen;
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/* DPC high-priority workqueue */
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struct workqueue_struct *dpc_hp_wq;
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struct work_struct nic_core_reset;
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struct work_struct idc_state_handler;
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struct work_struct nic_core_unrecoverable;
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struct qlt_hw_data tgt;
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};
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