From 8b00601547ca28c5c55124dceba203b5f5e2c214 Mon Sep 17 00:00:00 2001 From: Richard Kunze Date: Sun, 14 Dec 2014 20:53:39 +0100 Subject: [PATCH 01/13] ARM: dts: use all remaining MTD space foor rootfs of Iomega ix2-200 The original MTD partition layout for the Iomega ix2-200 leaves most of the available space unused. This patch changes the layout to use all remaining MTD space after the partitions for u-boot/u-boot-env and the kernel uimage as a "rootfs" partition. Signed-off-by: Richard Kunze Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 05291f3990d0..2a5c5a33db0c 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -192,8 +192,8 @@ }; partition@400000 { - label = "uInitrd"; - reg = <0x540000 0x1000000>; + label = "rootfs"; + reg = <0x400000 0x1C00000>; }; }; From 1701308a6e2407e144cb5af729e5b51731a3957d Mon Sep 17 00:00:00 2001 From: Richard Kunze Date: Wed, 10 Dec 2014 19:40:41 +0100 Subject: [PATCH 02/13] ARM: dts: add gpio_poweroff support for Iomega ix2-200 Iomega ix2-200 can be powered off via GPIO 0 pin 17, this patch wires up the gpio-poweroff driver to do it. Signed-off-by: Richard Kunze Acked-by: Andrew Lunn Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 2a5c5a33db0c..8474bffec0ca 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -169,6 +169,10 @@ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; }; &nand { From 9c569b390923f10d5551aa56c9e68f132459e0cc Mon Sep 17 00:00:00 2001 From: Evgeni Dobrev Date: Tue, 16 Dec 2014 19:22:18 +0100 Subject: [PATCH 03/13] ARM: dts: kirkwood: enable phy driver for SATA controller on 88f6192 This patch enables the phy drivers for the SATA controller on Marvell's 88f6192. Without them it is not possible to use SATA drives attached to this processor. Signed-off-by: Evgeni Dobrev Acked-by: Andrew Lunn Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/kirkwood-6192.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index dd81508b919b..9e6e9e2691d5 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -66,6 +66,8 @@ interrupts = <21>; clocks = <&gate_clk 14>, <&gate_clk 15>; clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; status = "disabled"; }; From dd7d2be1d2b8abb3754b19e4ebe72a4293253e4e Mon Sep 17 00:00:00 2001 From: Evgeni Dobrev Date: Sun, 28 Dec 2014 11:46:54 +0100 Subject: [PATCH 04/13] Kirkwood: add support for Seagate BlackArmor NAS220 This patch adds support for Seagate BlackArmor NAS220. The Seagate BlackArmor NAS 220 is a NAS system based on Marvell 88f6192. It has 32MB NAND and 128MB DRAM. It has two SATA slots, one Gigabit Ethernet port, two USB 2.0 ports, two buttons and three LEDs. There is a serial port available on the CN5 connector on the board (1 - TX, 4 - RX, 6 - GND). The only functionality still not implemented is the bi-color led on the front panel (status). Pins mpp22 and mpp23 control this led. Setting mpp22 to high and mpp23 to low results in orange color. Setting mpp22 to low and mpp23 to high results in blue color. The third led is wired to show the SATA activity on the two drives. Signed-off-by: Evgeni Dobrev Acked-by: Sebastian Hesselbarth Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/kirkwood-blackarmor-nas220.dts | 173 ++++++++++++++++++ 2 files changed, 174 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 91bd5bd62857..6dc9c17f9ff5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -112,6 +112,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ k2l-evm.dtb \ k2e-evm.dtb dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ + kirkwood-blackarmor-nas220.dtb \ kirkwood-cloudbox.dtb \ kirkwood-d2net.dtb \ kirkwood-db-88f6281.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts new file mode 100644 index 000000000000..fa02a9aff05e --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts @@ -0,0 +1,173 @@ +/* + * Device Tree file for Seagate Blackarmor NAS220 + * + * Copyright (C) 2014 Evgeni Dobrev + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +#include +#include +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "Seagate Blackarmor NAS220"; + compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", + "marvell,kirkwood"; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button@1{ + label = "Reset"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + + button@2{ + label = "Power"; + linux,code = ; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue-power { + label = "nas220:blue:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; + pinctrl-names = "default"; + + sata0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* + * Serial port routed to connector CN5 + * + * pin 1 - TX (CPU's TX) + * pin 4 - RX (CPU's RX) + * pin 6 - GND + */ +&uart0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-0 = <&pmx_button_reset &pmx_button_power>; + pinctrl-names = "default"; + + pmx_act_sata0: pmx-act-sata0 { + marvell,pins = "mpp15"; + marvell,function = "sata0"; + }; + + pmx_act_sata1: pmx-act-sata1 { + marvell,pins = "mpp16"; + marvell,function = "sata1"; + }; + + pmx_power_sata0: pmx-power-sata0 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_power_sata1: pmx-power-sata1 { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_button_power: pmx-button-power { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&i2c0 { + status = "okay"; + + adt7476: thermal@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; +}; + +&nand { + status = "okay"; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; From 4a25432b13090b57d257fa0ffb6712d8acf94523 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 8 Jan 2015 18:38:05 +0100 Subject: [PATCH 05/13] ARM: mvebu: a38x: Fix node names Some nodes in the DTs have a reg property but no unit name in their node name. This contradicts the way the ePAPR defines the node names. Fix this. Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/armada-380.dtsi | 2 +- arch/arm/boot/dts/armada-385-db.dts | 2 +- arch/arm/boot/dts/armada-385-rd.dts | 2 +- arch/arm/boot/dts/armada-385.dtsi | 2 +- arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 4173a8ab34e7..13400ce88c54 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -32,7 +32,7 @@ soc { internal-regs { - pinctrl { + pinctrl@18000 { compatible = "marvell,mv88f6810-pinctrl"; reg = <0x18000 0x20>; }; diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 2aaa9d2ac284..212605ccc7b6 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -74,7 +74,7 @@ phy-mode = "rgmii-id"; }; - mdio { + mdio@72004 { phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts index aaca2861dc87..74a3bfe6efd7 100644 --- a/arch/arm/boot/dts/armada-385-rd.dts +++ b/arch/arm/boot/dts/armada-385-rd.dts @@ -67,7 +67,7 @@ }; - mdio { + mdio@72004 { phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index 6283d7912f71..5249a4d3c207 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -37,7 +37,7 @@ soc { internal-regs { - pinctrl { + pinctrl@18000 { compatible = "marvell,mv88f6820-pinctrl"; reg = <0x18000 0x20>; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 74391dace9e7..ada1f206028b 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -193,7 +193,7 @@ status = "disabled"; }; - pinctrl { + pinctrl@18000 { compatible = "marvell,mv88f6820-pinctrl"; reg = <0x18000 0x20>; }; @@ -373,7 +373,7 @@ status = "disabled"; }; - mdio { + mdio@72004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; From 684f216f9eee5b38432c398cbd045ee2f3f11ece Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 8 Jan 2015 18:38:07 +0100 Subject: [PATCH 06/13] ARM: mvebu: A38x: Remove redundant pinctrl informations The compatible set in the armada-38x DTSI is always overridden, and the reg defined in there is duplicated in the armada-380 and armada-385 DTSIs. Remove these useless items. Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/armada-380.dtsi | 1 - arch/arm/boot/dts/armada-385.dtsi | 1 - arch/arm/boot/dts/armada-38x.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 13400ce88c54..7e509d2d74d0 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -34,7 +34,6 @@ internal-regs { pinctrl@18000 { compatible = "marvell,mv88f6810-pinctrl"; - reg = <0x18000 0x20>; }; }; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index 5249a4d3c207..a54a252ddb4c 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -39,7 +39,6 @@ internal-regs { pinctrl@18000 { compatible = "marvell,mv88f6820-pinctrl"; - reg = <0x18000 0x20>; }; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index ada1f206028b..40200084c6c8 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -194,7 +194,6 @@ }; pinctrl@18000 { - compatible = "marvell,mv88f6820-pinctrl"; reg = <0x18000 0x20>; }; From 91b4c91f919abffa72cbf7545a944252f8e4f775 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 8 Jan 2015 18:38:08 +0100 Subject: [PATCH 07/13] ARM: mvebu: Add a number of pinctrl functions Some pinctrl functions can be shared with all DTS out there, since they are generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid duplication. Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 40200084c6c8..98885c58be29 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -195,6 +195,45 @@ pinctrl@18000 { reg = <0x18000 0x20>; + + ge0_rgmii_pins: ge-rgmii-pins-0 { + marvell,pins = "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "ge0"; + }; + + i2c0_pins: i2c-pins-0 { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + mdio_pins: mdio-pins { + marvell,pins = "mpp4", "mpp5"; + marvell,function = "ge"; + }; + + ref_clk0_pins: ref-clk-pins-0 { + marvell,pins = "mpp45"; + marvell,function = "ref"; + }; + + spi1_pins: spi-pins-1 { + marvell,pins = "mpp56", "mpp57", "mpp58", + "mpp59"; + marvell,function = "spi1"; + }; + + uart0_pins: uart-pins-0 { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "ua0"; + }; + + uart1_pins: uart-pins-1 { + marvell,pins = "mpp19", "mpp20"; + marvell,function = "ua1"; + }; }; gpio0: gpio@18100 { From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 8 Jan 2015 18:38:09 +0100 Subject: [PATCH 08/13] ARM: mvebu: Add Armada 385 Access Point Development Board support The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage. [gregory.clement@free-electrons.com: switch the license to the dual X11/GPL with the agreement of the author] Signed-off-by: Maxime Ripard Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6dc9c17f9ff5..d34837104949 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -536,6 +536,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ armada-375-db.dtb dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-385-db.dtb \ + armada-385-db-ap.dtb \ armada-385-rd.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts new file mode 100644 index 000000000000..57b9119fb3e0 --- /dev/null +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -0,0 +1,178 @@ +/* + * Device Tree file for Marvell Armada 385 Access Point Development board + * (DB-88F6820-AP) + * + * Copyright (C) 2014 Marvell + * + * Nadav Haklai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include + +/ { + model = "Marvell Armada 385 Access Point Development Board"; + compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2GB */ + }; + + soc { + ranges = ; + + internal-regs { + spi1: spi@10680 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <54000000>; + }; + }; + + i2c0: i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + /* + * This bus is wired to two EEPROM + * sockets, one of which holding the + * board ID used by the bootloader. + * Erasing this EEPROM's content will + * brick the board. + * Use this bus with caution. + */ + }; + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@4 { + reg = <4>; + }; + + phy2: ethernet-phy@6 { + reg = <6>; + }; + }; + + /* UART0 is exposed through the JP8 connector */ + uart0: serial@12000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + + /* + * UART1 is exposed through a FTDI chip + * wired to the mini-USB connector + */ + uart1: serial@12100 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + }; + + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + + ethernet@34000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + + ethernet@70000 { + pinctrl-names = "default"; + + /* + * The Reference Clock 0 is used to + * provide a clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The three PCIe units are accessible through + * standard mini-PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; + }; +}; From 34598503049688741edc45e800627d945293e5f2 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jan 2015 18:38:10 +0100 Subject: [PATCH 09/13] ARM: mvebu: a38x: Add more pinctrl functions With the Armada 385 GP board more pinctrl functions depending of the SoC are needed. Add them to the DTSI to avoid duplication. Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/armada-38x.dtsi | 47 +++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 98885c58be29..63fe15174fee 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -204,6 +204,14 @@ marvell,function = "ge0"; }; + ge1_rgmii_pins: ge-rgmii-pins-1 { + marvell,pins = "mpp21", "mpp27", "mpp28", + "mpp29", "mpp30", "mpp31", + "mpp32", "mpp37", "mpp38", + "mpp39", "mpp40", "mpp41"; + marvell,function = "ge1"; + }; + i2c0_pins: i2c-pins-0 { marvell,pins = "mpp2", "mpp3"; marvell,function = "i2c0"; @@ -219,6 +227,17 @@ marvell,function = "ref"; }; + ref_clk1_pins: ref-clk-pins-1 { + marvell,pins = "mpp46"; + marvell,function = "ref"; + }; + + spi0_pins: spi-pins-0 { + marvell,pins = "mpp22", "mpp23", "mpp24", + "mpp25"; + marvell,function = "spi0"; + }; + spi1_pins: spi-pins-1 { marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; @@ -234,6 +253,34 @@ marvell,pins = "mpp19", "mpp20"; marvell,function = "ua1"; }; + + sdhci_pins: sdhci-pins { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp52", "mpp53", "mpp54", + "mpp55", "mpp57", "mpp58", + "mpp59"; + marvell,function = "sd0"; + }; + + sata0_pins: sata-pins-0 { + marvell,pins = "mpp20"; + marvell,function = "sata0"; + }; + + sata1_pins: sata-pins-1 { + marvell,pins = "mpp19"; + marvell,function = "sata1"; + }; + + sata2_pins: sata-pins-2 { + marvell,pins = "mpp47"; + marvell,function = "sata2"; + }; + + sata3_pins: sata-pins-3 { + marvell,pins = "mpp44"; + marvell,function = "sata3"; + }; }; gpio0: gpio@18100 { From 10c5c472703714a933ac3761653dd3f248d35011 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jan 2015 18:38:11 +0100 Subject: [PATCH 10/13] ARM: mvebu: a38x: Add missing labels The pintcrl label was missing. Adding it allowed referring it from the root of the device tree. Also add the uart0 label used by the bootloader. Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 63fe15174fee..04fe80d101f8 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -173,7 +173,7 @@ status = "disabled"; }; - serial@12000 { + uart0: serial@12000 { compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; @@ -193,7 +193,7 @@ status = "disabled"; }; - pinctrl@18000 { + pinctrl: pinctrl@18000 { reg = <0x18000 0x20>; ge0_rgmii_pins: ge-rgmii-pins-0 { From 912cdb4eb08d23704d629d8191a1ee9bcf53e71c Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jan 2015 18:38:12 +0100 Subject: [PATCH 11/13] ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC Update the binding documentation of the Armada 38x Soc family with the Armada 388. Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- Documentation/devicetree/bindings/arm/armada-38x.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt index ad9f8ed4d9bd..202953f1887e 100644 --- a/Documentation/devicetree/bindings/arm/armada-38x.txt +++ b/Documentation/devicetree/bindings/arm/armada-38x.txt @@ -15,6 +15,13 @@ Required root node property: compatible: must contain "marvell,armada385" +In addition, boards using the Marvell Armada 388 SoC shall have the +following property before the previous one: + +Required root node property: + +compatible: must contain "marvell,armada388" + Example: compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; From 881a50e47f231fb0185396125234f3188e14c2f3 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jan 2015 18:38:13 +0100 Subject: [PATCH 12/13] ARM: mvebu: Add Device Tree description of the Armada 388 SoC This SoC belongs to the Armada 38x family. The main difference with the Armada 385 is that the 388 can handle two more SATA ports. Currently the consequence is the use of a different compatible string for the pinctrl node, in order to be able to use the pins associated to this 2 new SATA ports. The second SATA controller has also been moved from the armada38x.dtsi as it it specific to the Armada388 version. In the same time the Armada385 DB and Armada 385 RD board have been renamed in the 388 one and now include the armada-388.dtsi file. AS both of them have 4 SATA ports the SoC used on them were wrongly described. Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/Makefile | 4 +- .../{armada-385-db.dts => armada-388-db.dts} | 7 +- .../{armada-385-rd.dts => armada-388-rd.dts} | 7 +- arch/arm/boot/dts/armada-388.dtsi | 70 +++++++++++++++++++ 4 files changed, 80 insertions(+), 8 deletions(-) rename arch/arm/boot/dts/{armada-385-db.dts => armada-388-db.dts} (93%) rename arch/arm/boot/dts/{armada-385-rd.dts => armada-388-rd.dts} (89%) create mode 100644 arch/arm/boot/dts/armada-388.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d34837104949..3ed928e364de 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -535,9 +535,9 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \ dtb-$(CONFIG_MACH_ARMADA_375) += \ armada-375-db.dtb dtb-$(CONFIG_MACH_ARMADA_38X) += \ - armada-385-db.dtb \ armada-385-db-ap.dtb \ - armada-385-rd.dtb + armada-388-db.dtb \ + armada-388-rd.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-388-db.dts similarity index 93% rename from arch/arm/boot/dts/armada-385-db.dts rename to arch/arm/boot/dts/armada-388-db.dts index 212605ccc7b6..e200836c30be 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -1,5 +1,5 @@ /* - * Device Tree file for Marvell Armada 385 evaluation board + * Device Tree file for Marvell Armada 388 evaluation board * (DB-88F6820) * * Copyright (C) 2014 Marvell @@ -12,11 +12,12 @@ */ /dts-v1/; -#include "armada-385.dtsi" +#include "armada-388.dtsi" / { model = "Marvell Armada 385 Development Board"; - compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada380"; + compatible = "marvell,a385-db", "marvell,armada388", + "marvell,armada385", "marvell,armada380"; chosen { bootargs = "console=ttyS0,115200 earlyprintk"; diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts similarity index 89% rename from arch/arm/boot/dts/armada-385-rd.dts rename to arch/arm/boot/dts/armada-388-rd.dts index 74a3bfe6efd7..c98a8f8d01a9 100644 --- a/arch/arm/boot/dts/armada-385-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -1,5 +1,5 @@ /* - * Device Tree file for Marvell Armada 385 Reference Design board + * Device Tree file for Marvell Armada 388 Reference Design board * (RD-88F6820-AP) * * Copyright (C) 2014 Marvell @@ -13,11 +13,12 @@ */ /dts-v1/; -#include "armada-385.dtsi" +#include "armada-388.dtsi" / { model = "Marvell Armada 385 Reference Design"; - compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; + compatible = "marvell,a385-rd", "marvell,armada388", + "marvell,armada385","marvell,armada380"; chosen { bootargs = "console=ttyS0,115200 earlyprintk"; diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi new file mode 100644 index 000000000000..564fa5937e25 --- /dev/null +++ b/arch/arm/boot/dts/armada-388.dtsi @@ -0,0 +1,70 @@ +/* + * Device Tree Include file for Marvell Armada 388 SoC. + * + * Copyright (C) 2015 Marvell + * + * Gregory CLEMENT + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + * The main difference with the Armada 385 is that the 388 can handle two more + * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl + * property and the name of the SoC, and add the second SATA host which control + * the 2 other ports. + */ + +#include "armada-385.dtsi" + +/ { + model = "Marvell Armada 388 family SoC"; + compatible = "marvell,armada388", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6828-pinctrl"; + }; + + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = ; + clocks = <&gateclk 30>; + status = "disabled"; + }; + + }; + }; +}; From 928413bd859c0936f03f6a3504c4721e83a3d1d7 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jan 2015 19:11:33 +0100 Subject: [PATCH 13/13] ARM: mvebu: Add Armada 388 General Purpose Development Board support The A388-GP is a board produced by Marvell that holds - 1 PCIe slot - 2 mini PCIe slot (one of them is multiplexed with the PCIe slot, muxing is selected through the GPIO expander) - 1 16MB SPI-NOR - 2 Gigabit Ethernet ports - 4 SATA ports (2 of them are multiplexed with the mini PCIe slots, muxing is selected through the GPIO expander) - 1 SDIO slot - 1 USB3 port - 2 USB2 port - 2 GPIO/interrupts expander on I2C Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-388-gp.dts | 288 ++++++++++++++++++++++++++++ 2 files changed, 289 insertions(+) create mode 100644 arch/arm/boot/dts/armada-388-gp.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3ed928e364de..17ee1d6a0ac0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -537,6 +537,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-385-db-ap.dtb \ armada-388-db.dtb \ + armada-388-gp.dtb \ armada-388-rd.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts new file mode 100644 index 000000000000..4df22bf91683 --- /dev/null +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -0,0 +1,288 @@ +/* + * Device Tree file for Marvell Armada 385 development board + * (RD-88F6820-GP) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-388.dtsi" +#include + +/ { + model = "Marvell Armada 385 GP"; + compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10600 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; + }; + + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; + /* + * The EEPROM located at adresse 54 is needed + * for the boot - DO NOT ERASE IT - + */ + + expander0: pca9555@20 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + pinctrl-0 = <&pca0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20>; + }; + + expander1: pca9555@21 { + compatible = "nxp,pca9555"; + pinctrl-names = "default"; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x21>; + }; + + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON16 + * through an FTDI + */ + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + + /* GE1 CON15 */ + ethernet@30000 { + pinctrl-names = "default"; + pinctrl-0 = <&ge1_rgmii_pins>; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + /* CON4 */ + usb@50000 { + vcc-supply = <®_usb2_0_vbus>; + status = "okay"; + }; + + /* GE0 CON1 */ + ethernet@70000 { + pinctrl-names = "default"; + /* + * The Reference Clock 0 is used to provide a + * clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + sata@a8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sata0_pins>, <&sata1_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + }; + + sata@e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&sata2_pins>, <&sata3_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + }; + + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; + no-1-8-v; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; + + /* CON5 */ + usb3@f0000 { + vcc-supply = <®_usb2_1_vbus>; + status = "okay"; + }; + + /* CON7 */ + usb3@f8000 { + vcc-supply = <®_usb3_vbus>; + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * The two other PCIe units are accessible + * through mini PCIe slot on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; + + gpio-fan { + compatible = "gpio-fan"; + gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_0_vbus: v5-vbus0 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_1_vbus: v5-vbus1 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_1_vbus: v5-vbus1 { + compatible = "regulator-fixed"; + regulator-name = "v5.0-vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl { + pca0_pins: pca0_pins { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; +};