From 5f4081d6fafec6c9dca9e7990e783b70db854a5c Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 17 Apr 2025 15:44:22 +0200 Subject: [PATCH 1/8] clk: add a clk_hw helpers to get the clock device or device_node Add helpers to get the device or device_node associated with clk_hw. This can be used by clock drivers to access various device related functionality such as devres, dev_ prints, etc ... Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-1-7743e509612a@baylibre.com Reviewed-by: Brian Masney Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 12 ++++++++++++ include/linux/clk-provider.h | 26 ++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 0565c87656cf..b821b2cdb155 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -365,6 +365,18 @@ const char *clk_hw_get_name(const struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_get_name); +struct device *clk_hw_get_dev(const struct clk_hw *hw) +{ + return hw->core->dev; +} +EXPORT_SYMBOL_GPL(clk_hw_get_dev); + +struct device_node *clk_hw_get_of_node(const struct clk_hw *hw) +{ + return hw->core->of_node; +} +EXPORT_SYMBOL_GPL(clk_hw_get_of_node); + struct clk_hw *__clk_get_hw(struct clk *clk) { return !clk ? NULL : clk->core->hw; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2e6e603b7493..630705a47129 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1360,6 +1360,32 @@ void clk_hw_unregister(struct clk_hw *hw); /* helper functions */ const char *__clk_get_name(const struct clk *clk); const char *clk_hw_get_name(const struct clk_hw *hw); + +/** + * clk_hw_get_dev() - get device from an hardware clock. + * @hw: the clk_hw pointer to get the struct device from + * + * This is a helper to get the struct device associated with a hardware + * clock. Some clock controllers, such as the one registered with + * CLK_OF_DECLARE(), may have not provided a device pointer while + * registering the clock. + * + * Return: the struct device associated with the clock, or NULL if there + * is none. + */ +struct device *clk_hw_get_dev(const struct clk_hw *hw); + +/** + * clk_hw_get_of_node() - get device_node from a hardware clock. + * @hw: the clk_hw pointer to get the struct device_node from + * + * This is a helper to get the struct device_node associated with a + * hardware clock. + * + * Return: the struct device_node associated with the clock, or NULL + * if there is none. + */ +struct device_node *clk_hw_get_of_node(const struct clk_hw *hw); #ifdef CONFIG_COMMON_CLK struct clk_hw *__clk_get_hw(struct clk *clk); #else From b06ba1c353b80367804b9ca7d7dbb9b6ea3aec33 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 19 Jun 2025 23:46:03 -0700 Subject: [PATCH 2/8] clk: tests: Make clk_register_clk_parent_data_device_driver() common Rename clk_register_clk_parent_data_device_driver() to kunit_of_platform_driver_dev() and have it return a struct device pointer while accepting a match table. This will be useful to find the device associated with an OF node for more tests than only the clk_parent_data tests. Signed-off-by: Jerome Brunet [sboyd@kernel.org: Split out from next patch, carry SoB and authorship, rename API, return device pointer] Signed-off-by: Stephen Boyd --- drivers/clk/clk_test.c | 84 +++++++++++++++++++++++------------------- 1 file changed, 46 insertions(+), 38 deletions(-) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index f08feeaa3750..ac28c05d9c66 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -2794,49 +2794,49 @@ static struct kunit_suite clk_register_clk_parent_data_of_suite = { }; /** - * struct clk_register_clk_parent_data_device_ctx - Context for clk_parent_data device tests - * @dev: device of clk under test - * @hw: clk_hw for clk under test + * struct platform_driver_dev_ctx - Context to stash platform device + * @dev: device under test * @pdrv: driver to attach to find @dev */ -struct clk_register_clk_parent_data_device_ctx { +struct platform_driver_dev_ctx { struct device *dev; - struct clk_hw hw; struct platform_driver pdrv; }; -static inline struct clk_register_clk_parent_data_device_ctx * -clk_register_clk_parent_data_driver_to_test_context(struct platform_device *pdev) +static inline struct platform_driver_dev_ctx * +pdev_to_platform_driver_dev_ctx(struct platform_device *pdev) { return container_of(to_platform_driver(pdev->dev.driver), - struct clk_register_clk_parent_data_device_ctx, pdrv); + struct platform_driver_dev_ctx, pdrv); } -static int clk_register_clk_parent_data_device_probe(struct platform_device *pdev) +static int kunit_platform_driver_dev_probe(struct platform_device *pdev) { - struct clk_register_clk_parent_data_device_ctx *ctx; + struct platform_driver_dev_ctx *ctx; - ctx = clk_register_clk_parent_data_driver_to_test_context(pdev); + ctx = pdev_to_platform_driver_dev_ctx(pdev); ctx->dev = &pdev->dev; return 0; } -static void clk_register_clk_parent_data_device_driver(struct kunit *test) +static struct device * +kunit_of_platform_driver_dev(struct kunit *test, const struct of_device_id *match_table) { - struct clk_register_clk_parent_data_device_ctx *ctx = test->priv; - static const struct of_device_id match_table[] = { - { .compatible = "test,clk-parent-data" }, - { } - }; + struct platform_driver_dev_ctx *ctx; - ctx->pdrv.probe = clk_register_clk_parent_data_device_probe; + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->pdrv.probe = kunit_platform_driver_dev_probe; ctx->pdrv.driver.of_match_table = match_table; ctx->pdrv.driver.name = __func__; ctx->pdrv.driver.owner = THIS_MODULE; KUNIT_ASSERT_EQ(test, 0, kunit_platform_driver_register(test, &ctx->pdrv)); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->dev); + + return ctx->dev; } static const struct clk_register_clk_parent_data_test_case @@ -2909,30 +2909,34 @@ KUNIT_ARRAY_PARAM(clk_register_clk_parent_data_device_test, */ static void clk_register_clk_parent_data_device_test(struct kunit *test) { - struct clk_register_clk_parent_data_device_ctx *ctx; + struct device *dev; + struct clk_hw *hw; const struct clk_register_clk_parent_data_test_case *test_param; struct clk_hw *parent_hw; struct clk_init_data init = { }; struct clk *expected_parent, *actual_parent; + static const struct of_device_id match_table[] = { + { .compatible = "test,clk-parent-data" }, + { } + }; - ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); - KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); - test->priv = ctx; + dev = kunit_of_platform_driver_dev(test, match_table); - clk_register_clk_parent_data_device_driver(test); - - expected_parent = clk_get_kunit(test, ctx->dev, "50"); + expected_parent = clk_get_kunit(test, dev, "50"); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, expected_parent); + hw = kunit_kzalloc(test, sizeof(*hw), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + test_param = test->param_value; init.parent_data = &test_param->pdata; init.num_parents = 1; init.name = "parent_data_device_test_clk"; init.ops = &clk_dummy_single_parent_ops; - ctx->hw.init = &init; - KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, ctx->dev, &ctx->hw)); + hw->init = &init; + KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, dev, hw)); - parent_hw = clk_hw_get_parent(&ctx->hw); + parent_hw = clk_hw_get_parent(hw); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent_hw); actual_parent = clk_hw_get_clk_kunit(test, parent_hw, __func__); @@ -3016,18 +3020,19 @@ KUNIT_ARRAY_PARAM(clk_register_clk_parent_data_device_hw_test, */ static void clk_register_clk_parent_data_device_hw_test(struct kunit *test) { - struct clk_register_clk_parent_data_device_ctx *ctx; + struct device *dev; + struct clk_hw *hw; const struct clk_register_clk_parent_data_test_case *test_param; struct clk_dummy_context *parent; struct clk_hw *parent_hw; struct clk_parent_data pdata = { }; struct clk_init_data init = { }; + static const struct of_device_id match_table[] = { + { .compatible = "test,clk-parent-data" }, + { } + }; - ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); - KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); - test->priv = ctx; - - clk_register_clk_parent_data_device_driver(test); + dev = kunit_of_platform_driver_dev(test, match_table); parent = kunit_kzalloc(test, sizeof(*parent), GFP_KERNEL); KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); @@ -3036,7 +3041,10 @@ static void clk_register_clk_parent_data_device_hw_test(struct kunit *test) parent_hw->init = CLK_HW_INIT_NO_PARENT("parent-clk", &clk_dummy_rate_ops, 0); - KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, ctx->dev, parent_hw)); + KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, dev, parent_hw)); + + hw = kunit_kzalloc(test, sizeof(*hw), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); test_param = test->param_value; memcpy(&pdata, &test_param->pdata, sizeof(pdata)); @@ -3045,10 +3053,10 @@ static void clk_register_clk_parent_data_device_hw_test(struct kunit *test) init.num_parents = 1; init.ops = &clk_dummy_single_parent_ops; init.name = "parent_data_device_hw_test_clk"; - ctx->hw.init = &init; - KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, ctx->dev, &ctx->hw)); + hw->init = &init; + KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, dev, hw)); - KUNIT_EXPECT_PTR_EQ(test, parent_hw, clk_hw_get_parent(&ctx->hw)); + KUNIT_EXPECT_PTR_EQ(test, parent_hw, clk_hw_get_parent(hw)); } static struct kunit_case clk_register_clk_parent_data_device_test_cases[] = { From ac32d031f508e46c19ab38d6ba8b53fc28df9945 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 17 Apr 2025 15:44:23 +0200 Subject: [PATCH 3/8] clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests Add kunit test suites clk_hw_get_dev() and clk_hw_get_of_node() for clocks registered with clk_hw_register() and of_clk_hw_register() Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-2-7743e509612a@baylibre.com Reviewed-by: Brian Masney [sboyd@kernel.org: Drop genparams, rename tests, drop inits, combine suites, add test for non-DT platform device] Signed-off-by: Stephen Boyd --- drivers/clk/Makefile | 1 + drivers/clk/clk_test.c | 140 ++++++++++++++++++ drivers/clk/kunit_clk_hw_get_dev_of_node.dtso | 10 ++ 3 files changed, 151 insertions(+) create mode 100644 drivers/clk/kunit_clk_hw_get_dev_of_node.dtso diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 42867cd37c33..862c3eefa5b5 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -18,6 +18,7 @@ clk-test-y := clk_test.o \ kunit_clk_assigned_rates_without_consumer.dtbo.o \ kunit_clk_assigned_rates_zero.dtbo.o \ kunit_clk_assigned_rates_zero_consumer.dtbo.o \ + kunit_clk_hw_get_dev_of_node.dtbo.o \ kunit_clk_parent_data_test.dtbo.o obj-$(CONFIG_COMMON_CLK) += clk-divider.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index ac28c05d9c66..042e632045bb 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -3403,8 +3403,148 @@ static struct kunit_suite clk_assigned_rates_suite = { .init = clk_assigned_rates_test_init, }; +static const struct clk_init_data clk_hw_get_dev_of_node_init_data = { + .name = "clk_hw_get_dev_of_node", + .ops = &empty_clk_ops, +}; + +/* + * Test that a clk registered with a struct device returns the device from + * clk_hw_get_dev() and the node from clk_hw_get_of_node() + */ +static void clk_hw_register_dev_get_dev_returns_dev(struct kunit *test) +{ + struct device *dev; + struct clk_hw *hw; + static const struct of_device_id match_table[] = { + { .compatible = "test,clk-hw-get-dev-of-node" }, + { } + }; + + KUNIT_ASSERT_EQ(test, 0, of_overlay_apply_kunit(test, kunit_clk_hw_get_dev_of_node)); + + dev = kunit_of_platform_driver_dev(test, match_table); + + hw = kunit_kzalloc(test, sizeof(*hw), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + hw->init = &clk_hw_get_dev_of_node_init_data; + KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, dev, hw)); + + KUNIT_EXPECT_PTR_EQ(test, dev, clk_hw_get_dev(hw)); + KUNIT_EXPECT_PTR_EQ(test, dev_of_node(dev), clk_hw_get_of_node(hw)); +} + +/* + * Test that a clk registered with a struct device that's not associated with + * an OF node returns the device from clk_hw_get_dev() and NULL from + * clk_hw_get_of_node() + */ +static void clk_hw_register_dev_no_node_get_dev_returns_dev(struct kunit *test) +{ + struct platform_device *pdev; + struct device *dev; + struct clk_hw *hw; + + pdev = kunit_platform_device_alloc(test, "clk_hw_register_dev_no_node", -1); + KUNIT_ASSERT_NOT_NULL(test, pdev); + KUNIT_ASSERT_EQ(test, 0, kunit_platform_device_add(test, pdev)); + dev = &pdev->dev; + + hw = kunit_kzalloc(test, sizeof(*hw), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + hw->init = &clk_hw_get_dev_of_node_init_data; + KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, dev, hw)); + + KUNIT_EXPECT_PTR_EQ(test, dev, clk_hw_get_dev(hw)); + KUNIT_EXPECT_PTR_EQ(test, NULL, clk_hw_get_of_node(hw)); +} + +/* + * Test that a clk registered without a struct device returns NULL from + * clk_hw_get_dev() + */ +static void clk_hw_register_NULL_get_dev_of_node_returns_NULL(struct kunit *test) +{ + struct clk_hw *hw; + + hw = kunit_kzalloc(test, sizeof(*hw), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + hw->init = &clk_hw_get_dev_of_node_init_data; + + KUNIT_ASSERT_EQ(test, 0, clk_hw_register_kunit(test, NULL, hw)); + + KUNIT_EXPECT_PTR_EQ(test, NULL, clk_hw_get_dev(hw)); + KUNIT_EXPECT_PTR_EQ(test, NULL, clk_hw_get_of_node(hw)); +} + +/* + * Test that a clk registered with an of_node returns the node from + * clk_hw_get_of_node() and NULL from clk_hw_get_dev() + */ +static void of_clk_hw_register_node_get_of_node_returns_node(struct kunit *test) +{ + struct device_node *np; + struct clk_hw *hw; + + hw = kunit_kzalloc(test, sizeof(*hw), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + KUNIT_ASSERT_EQ(test, 0, of_overlay_apply_kunit(test, kunit_clk_hw_get_dev_of_node)); + + np = of_find_compatible_node(NULL, NULL, "test,clk-hw-get-dev-of-node"); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, np); + of_node_put_kunit(test, np); + + hw->init = &clk_hw_get_dev_of_node_init_data; + KUNIT_ASSERT_EQ(test, 0, of_clk_hw_register_kunit(test, np, hw)); + + KUNIT_EXPECT_PTR_EQ(test, NULL, clk_hw_get_dev(hw)); + KUNIT_EXPECT_PTR_EQ(test, np, clk_hw_get_of_node(hw)); +} + +/* + * Test that a clk registered without an of_node returns the node from + * clk_hw_get_of_node() and clk_hw_get_dev() + */ +static void of_clk_hw_register_NULL_get_of_node_returns_NULL(struct kunit *test) +{ + struct clk_hw *hw; + + hw = kunit_kzalloc(test, sizeof(*hw), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + hw->init = &clk_hw_get_dev_of_node_init_data; + KUNIT_ASSERT_EQ(test, 0, of_clk_hw_register_kunit(test, NULL, hw)); + + KUNIT_EXPECT_PTR_EQ(test, NULL, clk_hw_get_dev(hw)); + KUNIT_EXPECT_PTR_EQ(test, NULL, clk_hw_get_of_node(hw)); +} + +static struct kunit_case clk_hw_get_dev_of_node_test_cases[] = { + KUNIT_CASE(clk_hw_register_dev_get_dev_returns_dev), + KUNIT_CASE(clk_hw_register_dev_no_node_get_dev_returns_dev), + KUNIT_CASE(clk_hw_register_NULL_get_dev_of_node_returns_NULL), + KUNIT_CASE(of_clk_hw_register_node_get_of_node_returns_node), + KUNIT_CASE(of_clk_hw_register_NULL_get_of_node_returns_NULL), + {} +}; + +/* + * Test suite to verify clk_hw_get_dev() and clk_hw_get_of_node() when clk + * registered with clk_hw_register() and of_clk_hw_register() + */ +static struct kunit_suite clk_hw_get_dev_of_node_test_suite = { + .name = "clk_hw_get_dev_of_node_test_suite", + .test_cases = clk_hw_get_dev_of_node_test_cases, +}; + + kunit_test_suites( &clk_assigned_rates_suite, + &clk_hw_get_dev_of_node_test_suite, &clk_leaf_mux_set_rate_parent_test_suite, &clk_test_suite, &clk_multiple_parents_mux_test_suite, diff --git a/drivers/clk/kunit_clk_hw_get_dev_of_node.dtso b/drivers/clk/kunit_clk_hw_get_dev_of_node.dtso new file mode 100644 index 000000000000..760717da3235 --- /dev/null +++ b/drivers/clk/kunit_clk_hw_get_dev_of_node.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +&{/} { + kunit-clock-controller { + compatible = "test,clk-hw-get-dev-of-node"; + #clock-cells = <0>; + }; +}; From 301b96e0668a6a0770a334b7243858b4f2d05091 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 11 Jun 2025 14:53:59 +0200 Subject: [PATCH 4/8] clk: amlogic: axg-audio: use the auxiliary reset driver Remove the implementation of the reset driver in axg audio clock driver and migrate to the one provided by reset framework on the auxiliary bus. Link: https://lore.kernel.org/r/20250611-clk-aux-v1-4-fb6575ed86a7@baylibre.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 3 +- drivers/clk/meson/axg-audio.c | 114 ++++------------------------------ 2 files changed, 15 insertions(+), 102 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index ff003dc5ab20..5c669b2e2f26 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -106,7 +106,8 @@ config COMMON_CLK_AXG_AUDIO select COMMON_CLK_MESON_SCLK_DIV select COMMON_CLK_MESON_CLKC_UTILS select REGMAP_MMIO - select RESET_CONTROLLER + select AUXILIARY_BUS + imply RESET_MESON_AUX help Support for the audio clock controller on AmLogic A113D devices, aka axg, Say Y if you want audio subsystem to work. diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 9df627b142f8..3948f5d0faca 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -4,6 +4,7 @@ * Author: Jerome Brunet */ +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include #include #include "meson-clkc-utils.h" @@ -1678,84 +1678,6 @@ static struct clk_regmap *const sm1_clk_regmaps[] = { &sm1_earcrx_dmac_clk, }; -struct axg_audio_reset_data { - struct reset_controller_dev rstc; - struct regmap *map; - unsigned int offset; -}; - -static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst, - unsigned long id, - unsigned int *reg, - unsigned int *bit) -{ - unsigned int stride = regmap_get_reg_stride(rst->map); - - *reg = (id / (stride * BITS_PER_BYTE)) * stride; - *reg += rst->offset; - *bit = id % (stride * BITS_PER_BYTE); -} - -static int axg_audio_reset_update(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) -{ - struct axg_audio_reset_data *rst = - container_of(rcdev, struct axg_audio_reset_data, rstc); - unsigned int offset, bit; - - axg_audio_reset_reg_and_bit(rst, id, &offset, &bit); - - regmap_update_bits(rst->map, offset, BIT(bit), - assert ? BIT(bit) : 0); - - return 0; -} - -static int axg_audio_reset_status(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct axg_audio_reset_data *rst = - container_of(rcdev, struct axg_audio_reset_data, rstc); - unsigned int val, offset, bit; - - axg_audio_reset_reg_and_bit(rst, id, &offset, &bit); - - regmap_read(rst->map, offset, &val); - - return !!(val & BIT(bit)); -} - -static int axg_audio_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return axg_audio_reset_update(rcdev, id, true); -} - -static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - return axg_audio_reset_update(rcdev, id, false); -} - -static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev, - unsigned long id) -{ - int ret; - - ret = axg_audio_reset_assert(rcdev, id); - if (ret) - return ret; - - return axg_audio_reset_deassert(rcdev, id); -} - -static const struct reset_control_ops axg_audio_rstc_ops = { - .assert = axg_audio_reset_assert, - .deassert = axg_audio_reset_deassert, - .reset = axg_audio_reset_toggle, - .status = axg_audio_reset_status, -}; - static struct regmap_config axg_audio_regmap_cfg = { .reg_bits = 32, .val_bits = 32, @@ -1766,8 +1688,7 @@ struct audioclk_data { struct clk_regmap *const *regmap_clks; unsigned int regmap_clk_num; struct meson_clk_hw_data hw_clks; - unsigned int reset_offset; - unsigned int reset_num; + const char *rst_drvname; unsigned int max_register; }; @@ -1775,7 +1696,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct audioclk_data *data; - struct axg_audio_reset_data *rst; + struct auxiliary_device *auxdev; struct regmap *map; void __iomem *regs; struct clk_hw *hw; @@ -1834,22 +1755,15 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) if (ret) return ret; - /* Stop here if there is no reset */ - if (!data->reset_num) - return 0; + /* Register auxiliary reset driver when applicable */ + if (data->rst_drvname) { + auxdev = __devm_auxiliary_device_create(dev, dev->driver->name, + data->rst_drvname, NULL, 0); + if (!auxdev) + return -ENODEV; + } - rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); - if (!rst) - return -ENOMEM; - - rst->map = map; - rst->offset = data->reset_offset; - rst->rstc.nr_resets = data->reset_num; - rst->rstc.ops = &axg_audio_rstc_ops; - rst->rstc.of_node = dev->of_node; - rst->rstc.owner = THIS_MODULE; - - return devm_reset_controller_register(dev, &rst->rstc); + return 0; } static const struct audioclk_data axg_audioclk_data = { @@ -1869,8 +1783,7 @@ static const struct audioclk_data g12a_audioclk_data = { .hws = g12a_audio_hw_clks, .num = ARRAY_SIZE(g12a_audio_hw_clks), }, - .reset_offset = AUDIO_SW_RESET, - .reset_num = 26, + .rst_drvname = "rst-g12a", .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL, }; @@ -1881,8 +1794,7 @@ static const struct audioclk_data sm1_audioclk_data = { .hws = sm1_audio_hw_clks, .num = ARRAY_SIZE(sm1_audio_hw_clks), }, - .reset_offset = AUDIO_SM1_SW_RESET0, - .reset_num = 39, + .rst_drvname = "rst-sm1", .max_register = AUDIO_EARCRX_DMAC_CLK_CTRL, }; From 328d4a7eb07389157fca1c282ecae63406a2c293 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 23 Jun 2025 16:37:00 +0200 Subject: [PATCH 5/8] clk: amlogic: remove unnecessary headers Some Amlogic clock controller drivers have a dedicated headers file, some do not. Over time, these headers have evolved and now only carry register offset definitions. These offsets are only used by the related controller and are not meant to be shared. These headers are not serving any purpose now. Start enforcing some consistency between the different Amlogic clock drivers and move the register offset definitions to the related driver. Link: https://lore.kernel.org/r/20250623-clk-meson-no-headers-v1-1-468161a7279e@baylibre.com [jbrunet: checkpatch strict: removed extra blank line] Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-peripherals.c | 31 ++++++- drivers/clk/meson/a1-peripherals.h | 46 ---------- drivers/clk/meson/a1-pll.c | 12 ++- drivers/clk/meson/a1-pll.h | 28 ------- drivers/clk/meson/axg-audio.c | 56 ++++++++++++- drivers/clk/meson/axg-audio.h | 70 ---------------- drivers/clk/meson/axg.c | 87 ++++++++++++++++++- drivers/clk/meson/axg.h | 105 ----------------------- drivers/clk/meson/g12a.c | 111 +++++++++++++++++++++++- drivers/clk/meson/g12a.h | 130 ----------------------------- drivers/clk/meson/gxbb.c | 99 +++++++++++++++++++++- drivers/clk/meson/gxbb.h | 115 ------------------------- drivers/clk/meson/meson8b.c | 67 ++++++++++++++- drivers/clk/meson/meson8b.h | 80 ------------------ drivers/clk/meson/s4-peripherals.c | 47 ++++++++++- drivers/clk/meson/s4-peripherals.h | 56 ------------- drivers/clk/meson/s4-pll.c | 29 ++++++- drivers/clk/meson/s4-pll.h | 38 --------- 18 files changed, 530 insertions(+), 677 deletions(-) delete mode 100644 drivers/clk/meson/a1-peripherals.h delete mode 100644 drivers/clk/meson/a1-pll.h delete mode 100644 drivers/clk/meson/axg-audio.h delete mode 100644 drivers/clk/meson/axg.h delete mode 100644 drivers/clk/meson/g12a.h delete mode 100644 drivers/clk/meson/gxbb.h delete mode 100644 drivers/clk/meson/meson8b.h delete mode 100644 drivers/clk/meson/s4-peripherals.h delete mode 100644 drivers/clk/meson/s4-pll.h diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c index 36489e0f948a..8ae02df3490b 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -10,13 +10,42 @@ #include #include #include -#include "a1-peripherals.h" #include "clk-dualdiv.h" #include "clk-regmap.h" #include "meson-clkc-utils.h" #include +#define SYS_OSCIN_CTRL 0x0 +#define RTC_BY_OSCIN_CTRL0 0x4 +#define RTC_BY_OSCIN_CTRL1 0x8 +#define RTC_CTRL 0xc +#define SYS_CLK_CTRL0 0x10 +#define SYS_CLK_EN0 0x1c +#define SYS_CLK_EN1 0x20 +#define AXI_CLK_EN 0x24 +#define DSPA_CLK_EN 0x28 +#define DSPB_CLK_EN 0x2c +#define DSPA_CLK_CTRL0 0x30 +#define DSPB_CLK_CTRL0 0x34 +#define CLK12_24_CTRL 0x38 +#define GEN_CLK_CTRL 0x3c +#define SAR_ADC_CLK_CTRL 0xc0 +#define PWM_CLK_AB_CTRL 0xc4 +#define PWM_CLK_CD_CTRL 0xc8 +#define PWM_CLK_EF_CTRL 0xcc +#define SPICC_CLK_CTRL 0xd0 +#define TS_CLK_CTRL 0xd4 +#define SPIFC_CLK_CTRL 0xd8 +#define USB_BUSCLK_CTRL 0xdc +#define SD_EMMC_CLK_CTRL 0xe0 +#define CECA_CLK_CTRL0 0xe4 +#define CECA_CLK_CTRL1 0xe8 +#define CECB_CLK_CTRL0 0xec +#define CECB_CLK_CTRL1 0xf0 +#define PSRAM_CLK_CTRL 0xf4 +#define DMC_CLK_CTRL 0xf8 + static struct clk_regmap xtal_in = { .data = &(struct clk_regmap_gate_data){ .offset = SYS_OSCIN_CTRL, diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h deleted file mode 100644 index 26de8530184a..000000000000 --- a/drivers/clk/meson/a1-peripherals.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Amlogic A1 Peripherals Clock Controller internals - * - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov - */ - -#ifndef __A1_PERIPHERALS_H -#define __A1_PERIPHERALS_H - -/* peripherals clock controller register offset */ -#define SYS_OSCIN_CTRL 0x0 -#define RTC_BY_OSCIN_CTRL0 0x4 -#define RTC_BY_OSCIN_CTRL1 0x8 -#define RTC_CTRL 0xc -#define SYS_CLK_CTRL0 0x10 -#define SYS_CLK_EN0 0x1c -#define SYS_CLK_EN1 0x20 -#define AXI_CLK_EN 0x24 -#define DSPA_CLK_EN 0x28 -#define DSPB_CLK_EN 0x2c -#define DSPA_CLK_CTRL0 0x30 -#define DSPB_CLK_CTRL0 0x34 -#define CLK12_24_CTRL 0x38 -#define GEN_CLK_CTRL 0x3c -#define SAR_ADC_CLK_CTRL 0xc0 -#define PWM_CLK_AB_CTRL 0xc4 -#define PWM_CLK_CD_CTRL 0xc8 -#define PWM_CLK_EF_CTRL 0xcc -#define SPICC_CLK_CTRL 0xd0 -#define TS_CLK_CTRL 0xd4 -#define SPIFC_CLK_CTRL 0xd8 -#define USB_BUSCLK_CTRL 0xdc -#define SD_EMMC_CLK_CTRL 0xe0 -#define CECA_CLK_CTRL0 0xe4 -#define CECA_CLK_CTRL1 0xe8 -#define CECB_CLK_CTRL0 0xec -#define CECB_CLK_CTRL1 0xf0 -#define PSRAM_CLK_CTRL 0xf4 -#define DMC_CLK_CTRL 0xf8 - -#endif /* __A1_PERIPHERALS_H */ diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 86d8159f3319..f0ba283cf1d0 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -10,10 +10,20 @@ #include #include #include -#include "a1-pll.h" +#include "clk-pll.h" #include "clk-regmap.h" #include "meson-clkc-utils.h" +#define ANACTRL_FIXPLL_CTRL0 0x0 +#define ANACTRL_FIXPLL_CTRL1 0x4 +#define ANACTRL_FIXPLL_STS 0x14 +#define ANACTRL_HIFIPLL_CTRL0 0xc0 +#define ANACTRL_HIFIPLL_CTRL1 0xc4 +#define ANACTRL_HIFIPLL_CTRL2 0xc8 +#define ANACTRL_HIFIPLL_CTRL3 0xcc +#define ANACTRL_HIFIPLL_CTRL4 0xd0 +#define ANACTRL_HIFIPLL_STS 0xd4 + #include static struct clk_regmap fixed_pll_dco = { diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h deleted file mode 100644 index 4be17b2bf383..000000000000 --- a/drivers/clk/meson/a1-pll.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Amlogic A1 PLL Clock Controller internals - * - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov - */ - -#ifndef __A1_PLL_H -#define __A1_PLL_H - -#include "clk-pll.h" - -/* PLL register offset */ -#define ANACTRL_FIXPLL_CTRL0 0x0 -#define ANACTRL_FIXPLL_CTRL1 0x4 -#define ANACTRL_FIXPLL_STS 0x14 -#define ANACTRL_HIFIPLL_CTRL0 0xc0 -#define ANACTRL_HIFIPLL_CTRL1 0xc4 -#define ANACTRL_HIFIPLL_CTRL2 0xc8 -#define ANACTRL_HIFIPLL_CTRL3 0xcc -#define ANACTRL_HIFIPLL_CTRL4 0xd0 -#define ANACTRL_HIFIPLL_STS 0xd4 - -#endif /* __A1_PLL_H */ diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 3948f5d0faca..cb556eb1630d 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -16,13 +16,67 @@ #include #include "meson-clkc-utils.h" -#include "axg-audio.h" #include "clk-regmap.h" #include "clk-phase.h" #include "sclk-div.h" #include +/* Audio clock register offsets */ +#define AUDIO_CLK_GATE_EN 0x000 +#define AUDIO_MCLK_A_CTRL 0x004 +#define AUDIO_MCLK_B_CTRL 0x008 +#define AUDIO_MCLK_C_CTRL 0x00C +#define AUDIO_MCLK_D_CTRL 0x010 +#define AUDIO_MCLK_E_CTRL 0x014 +#define AUDIO_MCLK_F_CTRL 0x018 +#define AUDIO_MST_PAD_CTRL0 0x01c +#define AUDIO_MST_PAD_CTRL1 0x020 +#define AUDIO_SW_RESET 0x024 +#define AUDIO_MST_A_SCLK_CTRL0 0x040 +#define AUDIO_MST_A_SCLK_CTRL1 0x044 +#define AUDIO_MST_B_SCLK_CTRL0 0x048 +#define AUDIO_MST_B_SCLK_CTRL1 0x04C +#define AUDIO_MST_C_SCLK_CTRL0 0x050 +#define AUDIO_MST_C_SCLK_CTRL1 0x054 +#define AUDIO_MST_D_SCLK_CTRL0 0x058 +#define AUDIO_MST_D_SCLK_CTRL1 0x05C +#define AUDIO_MST_E_SCLK_CTRL0 0x060 +#define AUDIO_MST_E_SCLK_CTRL1 0x064 +#define AUDIO_MST_F_SCLK_CTRL0 0x068 +#define AUDIO_MST_F_SCLK_CTRL1 0x06C +#define AUDIO_CLK_TDMIN_A_CTRL 0x080 +#define AUDIO_CLK_TDMIN_B_CTRL 0x084 +#define AUDIO_CLK_TDMIN_C_CTRL 0x088 +#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C +#define AUDIO_CLK_TDMOUT_A_CTRL 0x090 +#define AUDIO_CLK_TDMOUT_B_CTRL 0x094 +#define AUDIO_CLK_TDMOUT_C_CTRL 0x098 +#define AUDIO_CLK_SPDIFIN_CTRL 0x09C +#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 +#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 +#define AUDIO_CLK_LOCKER_CTRL 0x0A8 +#define AUDIO_CLK_PDMIN_CTRL0 0x0AC +#define AUDIO_CLK_PDMIN_CTRL1 0x0B0 +#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 + +/* SM1 introduce new register and some shifts :( */ +#define AUDIO_CLK_GATE_EN1 0x004 +#define AUDIO_SM1_MCLK_A_CTRL 0x008 +#define AUDIO_SM1_MCLK_B_CTRL 0x00C +#define AUDIO_SM1_MCLK_C_CTRL 0x010 +#define AUDIO_SM1_MCLK_D_CTRL 0x014 +#define AUDIO_SM1_MCLK_E_CTRL 0x018 +#define AUDIO_SM1_MCLK_F_CTRL 0x01C +#define AUDIO_SM1_MST_PAD_CTRL0 0x020 +#define AUDIO_SM1_MST_PAD_CTRL1 0x024 +#define AUDIO_SM1_SW_RESET0 0x028 +#define AUDIO_SM1_SW_RESET1 0x02C +#define AUDIO_CLK81_CTRL 0x030 +#define AUDIO_CLK81_EN 0x034 +#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0 +#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4 + #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ .data = &(struct clk_regmap_gate_data){ \ .offset = (_reg), \ diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h deleted file mode 100644 index 9e7765b630c9..000000000000 --- a/drivers/clk/meson/axg-audio.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2018 BayLibre, SAS. - * Author: Jerome Brunet - */ - -#ifndef __AXG_AUDIO_CLKC_H -#define __AXG_AUDIO_CLKC_H - -/* - * Audio Clock register offsets - * - * Register offsets from the datasheet must be multiplied by 4 before - * to get the right offset - */ -#define AUDIO_CLK_GATE_EN 0x000 -#define AUDIO_MCLK_A_CTRL 0x004 -#define AUDIO_MCLK_B_CTRL 0x008 -#define AUDIO_MCLK_C_CTRL 0x00C -#define AUDIO_MCLK_D_CTRL 0x010 -#define AUDIO_MCLK_E_CTRL 0x014 -#define AUDIO_MCLK_F_CTRL 0x018 -#define AUDIO_MST_PAD_CTRL0 0x01c -#define AUDIO_MST_PAD_CTRL1 0x020 -#define AUDIO_SW_RESET 0x024 -#define AUDIO_MST_A_SCLK_CTRL0 0x040 -#define AUDIO_MST_A_SCLK_CTRL1 0x044 -#define AUDIO_MST_B_SCLK_CTRL0 0x048 -#define AUDIO_MST_B_SCLK_CTRL1 0x04C -#define AUDIO_MST_C_SCLK_CTRL0 0x050 -#define AUDIO_MST_C_SCLK_CTRL1 0x054 -#define AUDIO_MST_D_SCLK_CTRL0 0x058 -#define AUDIO_MST_D_SCLK_CTRL1 0x05C -#define AUDIO_MST_E_SCLK_CTRL0 0x060 -#define AUDIO_MST_E_SCLK_CTRL1 0x064 -#define AUDIO_MST_F_SCLK_CTRL0 0x068 -#define AUDIO_MST_F_SCLK_CTRL1 0x06C -#define AUDIO_CLK_TDMIN_A_CTRL 0x080 -#define AUDIO_CLK_TDMIN_B_CTRL 0x084 -#define AUDIO_CLK_TDMIN_C_CTRL 0x088 -#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C -#define AUDIO_CLK_TDMOUT_A_CTRL 0x090 -#define AUDIO_CLK_TDMOUT_B_CTRL 0x094 -#define AUDIO_CLK_TDMOUT_C_CTRL 0x098 -#define AUDIO_CLK_SPDIFIN_CTRL 0x09C -#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 -#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 -#define AUDIO_CLK_LOCKER_CTRL 0x0A8 -#define AUDIO_CLK_PDMIN_CTRL0 0x0AC -#define AUDIO_CLK_PDMIN_CTRL1 0x0B0 -#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 - -/* SM1 introduce new register and some shifts :( */ -#define AUDIO_CLK_GATE_EN1 0x004 -#define AUDIO_SM1_MCLK_A_CTRL 0x008 -#define AUDIO_SM1_MCLK_B_CTRL 0x00C -#define AUDIO_SM1_MCLK_C_CTRL 0x010 -#define AUDIO_SM1_MCLK_D_CTRL 0x014 -#define AUDIO_SM1_MCLK_E_CTRL 0x018 -#define AUDIO_SM1_MCLK_F_CTRL 0x01C -#define AUDIO_SM1_MST_PAD_CTRL0 0x020 -#define AUDIO_SM1_MST_PAD_CTRL1 0x024 -#define AUDIO_SM1_SW_RESET0 0x028 -#define AUDIO_SM1_SW_RESET1 0x02C -#define AUDIO_CLK81_CTRL 0x030 -#define AUDIO_CLK81_EN 0x034 -#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0 -#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4 - -#endif /*__AXG_AUDIO_CLKC_H */ diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 448eece246ca..766764b50b36 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -18,11 +18,96 @@ #include "clk-regmap.h" #include "clk-pll.h" #include "clk-mpll.h" -#include "axg.h" #include "meson-eeclk.h" #include +#define HHI_GP0_PLL_CNTL 0x40 +#define HHI_GP0_PLL_CNTL2 0x44 +#define HHI_GP0_PLL_CNTL3 0x48 +#define HHI_GP0_PLL_CNTL4 0x4c +#define HHI_GP0_PLL_CNTL5 0x50 +#define HHI_GP0_PLL_STS 0x54 +#define HHI_GP0_PLL_CNTL1 0x58 +#define HHI_HIFI_PLL_CNTL 0x80 +#define HHI_HIFI_PLL_CNTL2 0x84 +#define HHI_HIFI_PLL_CNTL3 0x88 +#define HHI_HIFI_PLL_CNTL4 0x8C +#define HHI_HIFI_PLL_CNTL5 0x90 +#define HHI_HIFI_PLL_STS 0x94 +#define HHI_HIFI_PLL_CNTL1 0x98 + +#define HHI_XTAL_DIVN_CNTL 0xbc +#define HHI_GCLK2_MPEG0 0xc0 +#define HHI_GCLK2_MPEG1 0xc4 +#define HHI_GCLK2_MPEG2 0xc8 +#define HHI_GCLK2_OTHER 0xd0 +#define HHI_GCLK2_AO 0xd4 +#define HHI_PCIE_PLL_CNTL 0xd8 +#define HHI_PCIE_PLL_CNTL1 0xdC +#define HHI_PCIE_PLL_CNTL2 0xe0 +#define HHI_PCIE_PLL_CNTL3 0xe4 +#define HHI_PCIE_PLL_CNTL4 0xe8 +#define HHI_PCIE_PLL_CNTL5 0xec +#define HHI_PCIE_PLL_CNTL6 0xf0 +#define HHI_PCIE_PLL_STS 0xf4 + +#define HHI_MEM_PD_REG0 0x100 +#define HHI_VPU_MEM_PD_REG0 0x104 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c + +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_SYS_CPU_RESET_CNTL 0x160 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_SPICC_HCLK_CNTL 0x168 + +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_VPU_CLK_CNTL 0x1bC + +#define HHI_VAPBCLK_CNTL 0x1F4 + +#define HHI_GEN_CLK_CNTL 0x228 + +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 + +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28C +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29C +#define HHI_MPLL_CNTL9 0x2A0 +#define HHI_MPLL_CNTL10 0x2A4 + +#define HHI_MPLL3_CNTL0 0x2E0 +#define HHI_MPLL3_CNTL1 0x2E4 +#define HHI_PLL_TOP_MISC 0x2E8 + +#define HHI_SYS_PLL_CNTL1 0x2FC +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_SYS_PLL_CNTL2 0x304 +#define HHI_SYS_PLL_CNTL3 0x308 +#define HHI_SYS_PLL_CNTL4 0x30c +#define HHI_SYS_PLL_CNTL5 0x310 +#define HHI_SYS_PLL_STS 0x314 +#define HHI_DPLL_TOP_I 0x318 +#define HHI_DPLL_TOP2_I 0x31C + static struct clk_regmap axg_fixed_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h deleted file mode 100644 index 624d8d3ce7c4..000000000000 --- a/drivers/clk/meson/axg.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2016 AmLogic, Inc. - * Author: Michael Turquette - * - * Copyright (c) 2017 Amlogic, inc. - * Author: Qiufang Dai - * - */ -#ifndef __AXG_H -#define __AXG_H - -/* - * Clock controller register offsets - * - * Register offsets from the data sheet must be multiplied by 4 before - * adding them to the base address to get the right value. - */ -#define HHI_GP0_PLL_CNTL 0x40 -#define HHI_GP0_PLL_CNTL2 0x44 -#define HHI_GP0_PLL_CNTL3 0x48 -#define HHI_GP0_PLL_CNTL4 0x4c -#define HHI_GP0_PLL_CNTL5 0x50 -#define HHI_GP0_PLL_STS 0x54 -#define HHI_GP0_PLL_CNTL1 0x58 -#define HHI_HIFI_PLL_CNTL 0x80 -#define HHI_HIFI_PLL_CNTL2 0x84 -#define HHI_HIFI_PLL_CNTL3 0x88 -#define HHI_HIFI_PLL_CNTL4 0x8C -#define HHI_HIFI_PLL_CNTL5 0x90 -#define HHI_HIFI_PLL_STS 0x94 -#define HHI_HIFI_PLL_CNTL1 0x98 - -#define HHI_XTAL_DIVN_CNTL 0xbc -#define HHI_GCLK2_MPEG0 0xc0 -#define HHI_GCLK2_MPEG1 0xc4 -#define HHI_GCLK2_MPEG2 0xc8 -#define HHI_GCLK2_OTHER 0xd0 -#define HHI_GCLK2_AO 0xd4 -#define HHI_PCIE_PLL_CNTL 0xd8 -#define HHI_PCIE_PLL_CNTL1 0xdC -#define HHI_PCIE_PLL_CNTL2 0xe0 -#define HHI_PCIE_PLL_CNTL3 0xe4 -#define HHI_PCIE_PLL_CNTL4 0xe8 -#define HHI_PCIE_PLL_CNTL5 0xec -#define HHI_PCIE_PLL_CNTL6 0xf0 -#define HHI_PCIE_PLL_STS 0xf4 - -#define HHI_MEM_PD_REG0 0x100 -#define HHI_VPU_MEM_PD_REG0 0x104 -#define HHI_VIID_CLK_DIV 0x128 -#define HHI_VIID_CLK_CNTL 0x12c - -#define HHI_GCLK_MPEG0 0x140 -#define HHI_GCLK_MPEG1 0x144 -#define HHI_GCLK_MPEG2 0x148 -#define HHI_GCLK_OTHER 0x150 -#define HHI_GCLK_AO 0x154 -#define HHI_SYS_CPU_CLK_CNTL1 0x15c -#define HHI_SYS_CPU_RESET_CNTL 0x160 -#define HHI_VID_CLK_DIV 0x164 -#define HHI_SPICC_HCLK_CNTL 0x168 - -#define HHI_MPEG_CLK_CNTL 0x174 -#define HHI_VID_CLK_CNTL 0x17c -#define HHI_TS_CLK_CNTL 0x190 -#define HHI_VID_CLK_CNTL2 0x194 -#define HHI_SYS_CPU_CLK_CNTL0 0x19c -#define HHI_VID_PLL_CLK_DIV 0x1a0 -#define HHI_VPU_CLK_CNTL 0x1bC - -#define HHI_VAPBCLK_CNTL 0x1F4 - -#define HHI_GEN_CLK_CNTL 0x228 - -#define HHI_VDIN_MEAS_CLK_CNTL 0x250 -#define HHI_NAND_CLK_CNTL 0x25C -#define HHI_SD_EMMC_CLK_CNTL 0x264 - -#define HHI_MPLL_CNTL 0x280 -#define HHI_MPLL_CNTL2 0x284 -#define HHI_MPLL_CNTL3 0x288 -#define HHI_MPLL_CNTL4 0x28C -#define HHI_MPLL_CNTL5 0x290 -#define HHI_MPLL_CNTL6 0x294 -#define HHI_MPLL_CNTL7 0x298 -#define HHI_MPLL_CNTL8 0x29C -#define HHI_MPLL_CNTL9 0x2A0 -#define HHI_MPLL_CNTL10 0x2A4 - -#define HHI_MPLL3_CNTL0 0x2E0 -#define HHI_MPLL3_CNTL1 0x2E4 -#define HHI_PLL_TOP_MISC 0x2E8 - -#define HHI_SYS_PLL_CNTL1 0x2FC -#define HHI_SYS_PLL_CNTL 0x300 -#define HHI_SYS_PLL_CNTL2 0x304 -#define HHI_SYS_PLL_CNTL3 0x308 -#define HHI_SYS_PLL_CNTL4 0x30c -#define HHI_SYS_PLL_CNTL5 0x310 -#define HHI_SYS_PLL_STS 0x314 -#define HHI_DPLL_TOP_I 0x318 -#define HHI_DPLL_TOP2_I 0x31C - -#endif /* __AXG_H */ diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d9e546e006d7..e59bae56a4a5 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -24,10 +24,119 @@ #include "vid-pll-div.h" #include "vclk.h" #include "meson-eeclk.h" -#include "g12a.h" #include +#define HHI_MIPI_CNTL0 0x000 +#define HHI_MIPI_CNTL1 0x004 +#define HHI_MIPI_CNTL2 0x008 +#define HHI_MIPI_STS 0x00c +#define HHI_GP0_PLL_CNTL0 0x040 +#define HHI_GP0_PLL_CNTL1 0x044 +#define HHI_GP0_PLL_CNTL2 0x048 +#define HHI_GP0_PLL_CNTL3 0x04c +#define HHI_GP0_PLL_CNTL4 0x050 +#define HHI_GP0_PLL_CNTL5 0x054 +#define HHI_GP0_PLL_CNTL6 0x058 +#define HHI_GP0_PLL_STS 0x05c +#define HHI_GP1_PLL_CNTL0 0x060 +#define HHI_GP1_PLL_CNTL1 0x064 +#define HHI_GP1_PLL_CNTL2 0x068 +#define HHI_GP1_PLL_CNTL3 0x06c +#define HHI_GP1_PLL_CNTL4 0x070 +#define HHI_GP1_PLL_CNTL5 0x074 +#define HHI_GP1_PLL_CNTL6 0x078 +#define HHI_GP1_PLL_STS 0x07c +#define HHI_PCIE_PLL_CNTL0 0x098 +#define HHI_PCIE_PLL_CNTL1 0x09c +#define HHI_PCIE_PLL_CNTL2 0x0a0 +#define HHI_PCIE_PLL_CNTL3 0x0a4 +#define HHI_PCIE_PLL_CNTL4 0x0a8 +#define HHI_PCIE_PLL_CNTL5 0x0ac +#define HHI_PCIE_PLL_STS 0x0b8 +#define HHI_HIFI_PLL_CNTL0 0x0d8 +#define HHI_HIFI_PLL_CNTL1 0x0dc +#define HHI_HIFI_PLL_CNTL2 0x0e0 +#define HHI_HIFI_PLL_CNTL3 0x0e4 +#define HHI_HIFI_PLL_CNTL4 0x0e8 +#define HHI_HIFI_PLL_CNTL5 0x0ec +#define HHI_HIFI_PLL_CNTL6 0x0f0 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_OTHER2 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLKC_CNTL 0x1b4 +#define HHI_VPU_CLK_CNTL 0x1bc +#define HHI_ISP_CLK_CNTL 0x1c0 +#define HHI_NNA_CLK_CNTL 0x1c8 +#define HHI_HDMI_CLK_CNTL 0x1cc +#define HHI_VDEC_CLK_CNTL 0x1e0 +#define HHI_VDEC2_CLK_CNTL 0x1e4 +#define HHI_VDEC3_CLK_CNTL 0x1e8 +#define HHI_VDEC4_CLK_CNTL 0x1ec +#define HHI_HDCP22_CLK_CNTL 0x1f0 +#define HHI_VAPBCLK_CNTL 0x1f4 +#define HHI_SYS_CPUB_CLK_CNTL1 0x200 +#define HHI_SYS_CPUB_CLK_CNTL 0x208 +#define HHI_VPU_CLKB_CNTL 0x20c +#define HHI_SYS_CPU_CLK_CNTL2 0x210 +#define HHI_SYS_CPU_CLK_CNTL3 0x214 +#define HHI_SYS_CPU_CLK_CNTL4 0x218 +#define HHI_SYS_CPU_CLK_CNTL5 0x21c +#define HHI_SYS_CPU_CLK_CNTL6 0x220 +#define HHI_GEN_CLK_CNTL 0x228 +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 +#define HHI_NAND_CLK_CNTL 0x25c +#define HHI_SD_EMMC_CLK_CNTL 0x264 +#define HHI_MPLL_CNTL0 0x278 +#define HHI_MPLL_CNTL1 0x27c +#define HHI_MPLL_CNTL2 0x280 +#define HHI_MPLL_CNTL3 0x284 +#define HHI_MPLL_CNTL4 0x288 +#define HHI_MPLL_CNTL5 0x28c +#define HHI_MPLL_CNTL6 0x290 +#define HHI_MPLL_CNTL7 0x294 +#define HHI_MPLL_CNTL8 0x298 +#define HHI_FIX_PLL_CNTL0 0x2a0 +#define HHI_FIX_PLL_CNTL1 0x2a4 +#define HHI_FIX_PLL_CNTL3 0x2ac +#define HHI_SYS_PLL_CNTL0 0x2f4 +#define HHI_SYS_PLL_CNTL1 0x2f8 +#define HHI_SYS_PLL_CNTL2 0x2fc +#define HHI_SYS_PLL_CNTL3 0x300 +#define HHI_SYS_PLL_CNTL4 0x304 +#define HHI_SYS_PLL_CNTL5 0x308 +#define HHI_SYS_PLL_CNTL6 0x30c +#define HHI_HDMI_PLL_CNTL0 0x320 +#define HHI_HDMI_PLL_CNTL1 0x324 +#define HHI_HDMI_PLL_CNTL2 0x328 +#define HHI_HDMI_PLL_CNTL3 0x32c +#define HHI_HDMI_PLL_CNTL4 0x330 +#define HHI_HDMI_PLL_CNTL5 0x334 +#define HHI_HDMI_PLL_CNTL6 0x338 +#define HHI_SPICC_CLK_CNTL 0x3dc +#define HHI_SYS1_PLL_CNTL0 0x380 +#define HHI_SYS1_PLL_CNTL1 0x384 +#define HHI_SYS1_PLL_CNTL2 0x388 +#define HHI_SYS1_PLL_CNTL3 0x38c +#define HHI_SYS1_PLL_CNTL4 0x390 +#define HHI_SYS1_PLL_CNTL5 0x394 +#define HHI_SYS1_PLL_CNTL6 0x398 + static struct clk_regmap g12a_fixed_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h deleted file mode 100644 index 27df99c4565a..000000000000 --- a/drivers/clk/meson/g12a.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2016 Amlogic, Inc. - * Author: Michael Turquette - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai - * Author: Jian Hu - * - */ -#ifndef __G12A_H -#define __G12A_H - -/* - * Clock controller register offsets - * - * Register offsets from the data sheet must be multiplied by 4 before - * adding them to the base address to get the right value. - */ -#define HHI_MIPI_CNTL0 0x000 -#define HHI_MIPI_CNTL1 0x004 -#define HHI_MIPI_CNTL2 0x008 -#define HHI_MIPI_STS 0x00C -#define HHI_GP0_PLL_CNTL0 0x040 -#define HHI_GP0_PLL_CNTL1 0x044 -#define HHI_GP0_PLL_CNTL2 0x048 -#define HHI_GP0_PLL_CNTL3 0x04C -#define HHI_GP0_PLL_CNTL4 0x050 -#define HHI_GP0_PLL_CNTL5 0x054 -#define HHI_GP0_PLL_CNTL6 0x058 -#define HHI_GP0_PLL_STS 0x05C -#define HHI_GP1_PLL_CNTL0 0x060 -#define HHI_GP1_PLL_CNTL1 0x064 -#define HHI_GP1_PLL_CNTL2 0x068 -#define HHI_GP1_PLL_CNTL3 0x06C -#define HHI_GP1_PLL_CNTL4 0x070 -#define HHI_GP1_PLL_CNTL5 0x074 -#define HHI_GP1_PLL_CNTL6 0x078 -#define HHI_GP1_PLL_STS 0x07C -#define HHI_PCIE_PLL_CNTL0 0x098 -#define HHI_PCIE_PLL_CNTL1 0x09C -#define HHI_PCIE_PLL_CNTL2 0x0A0 -#define HHI_PCIE_PLL_CNTL3 0x0A4 -#define HHI_PCIE_PLL_CNTL4 0x0A8 -#define HHI_PCIE_PLL_CNTL5 0x0AC -#define HHI_PCIE_PLL_STS 0x0B8 -#define HHI_HIFI_PLL_CNTL0 0x0D8 -#define HHI_HIFI_PLL_CNTL1 0x0DC -#define HHI_HIFI_PLL_CNTL2 0x0E0 -#define HHI_HIFI_PLL_CNTL3 0x0E4 -#define HHI_HIFI_PLL_CNTL4 0x0E8 -#define HHI_HIFI_PLL_CNTL5 0x0EC -#define HHI_HIFI_PLL_CNTL6 0x0F0 -#define HHI_VIID_CLK_DIV 0x128 -#define HHI_VIID_CLK_CNTL 0x12C -#define HHI_GCLK_MPEG0 0x140 -#define HHI_GCLK_MPEG1 0x144 -#define HHI_GCLK_MPEG2 0x148 -#define HHI_GCLK_OTHER 0x150 -#define HHI_GCLK_OTHER2 0x154 -#define HHI_SYS_CPU_CLK_CNTL1 0x15c -#define HHI_VID_CLK_DIV 0x164 -#define HHI_MPEG_CLK_CNTL 0x174 -#define HHI_AUD_CLK_CNTL 0x178 -#define HHI_VID_CLK_CNTL 0x17c -#define HHI_TS_CLK_CNTL 0x190 -#define HHI_VID_CLK_CNTL2 0x194 -#define HHI_SYS_CPU_CLK_CNTL0 0x19c -#define HHI_VID_PLL_CLK_DIV 0x1A0 -#define HHI_MALI_CLK_CNTL 0x1b0 -#define HHI_VPU_CLKC_CNTL 0x1b4 -#define HHI_VPU_CLK_CNTL 0x1bC -#define HHI_ISP_CLK_CNTL 0x1C0 -#define HHI_NNA_CLK_CNTL 0x1C8 -#define HHI_HDMI_CLK_CNTL 0x1CC -#define HHI_VDEC_CLK_CNTL 0x1E0 -#define HHI_VDEC2_CLK_CNTL 0x1E4 -#define HHI_VDEC3_CLK_CNTL 0x1E8 -#define HHI_VDEC4_CLK_CNTL 0x1EC -#define HHI_HDCP22_CLK_CNTL 0x1F0 -#define HHI_VAPBCLK_CNTL 0x1F4 -#define HHI_SYS_CPUB_CLK_CNTL1 0x200 -#define HHI_SYS_CPUB_CLK_CNTL 0x208 -#define HHI_VPU_CLKB_CNTL 0x20C -#define HHI_SYS_CPU_CLK_CNTL2 0x210 -#define HHI_SYS_CPU_CLK_CNTL3 0x214 -#define HHI_SYS_CPU_CLK_CNTL4 0x218 -#define HHI_SYS_CPU_CLK_CNTL5 0x21c -#define HHI_SYS_CPU_CLK_CNTL6 0x220 -#define HHI_GEN_CLK_CNTL 0x228 -#define HHI_VDIN_MEAS_CLK_CNTL 0x250 -#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 -#define HHI_NAND_CLK_CNTL 0x25C -#define HHI_SD_EMMC_CLK_CNTL 0x264 -#define HHI_MPLL_CNTL0 0x278 -#define HHI_MPLL_CNTL1 0x27C -#define HHI_MPLL_CNTL2 0x280 -#define HHI_MPLL_CNTL3 0x284 -#define HHI_MPLL_CNTL4 0x288 -#define HHI_MPLL_CNTL5 0x28c -#define HHI_MPLL_CNTL6 0x290 -#define HHI_MPLL_CNTL7 0x294 -#define HHI_MPLL_CNTL8 0x298 -#define HHI_FIX_PLL_CNTL0 0x2A0 -#define HHI_FIX_PLL_CNTL1 0x2A4 -#define HHI_FIX_PLL_CNTL3 0x2AC -#define HHI_SYS_PLL_CNTL0 0x2f4 -#define HHI_SYS_PLL_CNTL1 0x2f8 -#define HHI_SYS_PLL_CNTL2 0x2fc -#define HHI_SYS_PLL_CNTL3 0x300 -#define HHI_SYS_PLL_CNTL4 0x304 -#define HHI_SYS_PLL_CNTL5 0x308 -#define HHI_SYS_PLL_CNTL6 0x30c -#define HHI_HDMI_PLL_CNTL0 0x320 -#define HHI_HDMI_PLL_CNTL1 0x324 -#define HHI_HDMI_PLL_CNTL2 0x328 -#define HHI_HDMI_PLL_CNTL3 0x32c -#define HHI_HDMI_PLL_CNTL4 0x330 -#define HHI_HDMI_PLL_CNTL5 0x334 -#define HHI_HDMI_PLL_CNTL6 0x338 -#define HHI_SPICC_CLK_CNTL 0x3dc -#define HHI_SYS1_PLL_CNTL0 0x380 -#define HHI_SYS1_PLL_CNTL1 0x384 -#define HHI_SYS1_PLL_CNTL2 0x388 -#define HHI_SYS1_PLL_CNTL3 0x38c -#define HHI_SYS1_PLL_CNTL4 0x390 -#define HHI_SYS1_PLL_CNTL5 0x394 -#define HHI_SYS1_PLL_CNTL6 0x398 - -#endif /* __G12A_H */ diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 3abb44a2532b..9aed0ea657ab 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -10,7 +10,6 @@ #include #include -#include "gxbb.h" #include "clk-regmap.h" #include "clk-pll.h" #include "clk-mpll.h" @@ -19,6 +18,104 @@ #include +#define SCR 0x2c +#define TIMEOUT_VALUE 0x3c + +#define HHI_GP0_PLL_CNTL 0x40 +#define HHI_GP0_PLL_CNTL2 0x44 +#define HHI_GP0_PLL_CNTL3 0x48 +#define HHI_GP0_PLL_CNTL4 0x4c +#define HHI_GP0_PLL_CNTL5 0x50 +#define HHI_GP0_PLL_CNTL1 0x58 + +#define HHI_XTAL_DIVN_CNTL 0xbc +#define HHI_TIMER90K 0xec + +#define HHI_MEM_PD_REG0 0x100 +#define HHI_MEM_PD_REG1 0x104 +#define HHI_VPU_MEM_PD_REG1 0x108 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c + +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_OSCIN_CNTL 0x158 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_SYS_CPU_RESET_CNTL 0x160 +#define HHI_VID_CLK_DIV 0x164 + +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_AUD_CLK_CNTL2 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1a0 +#define HHI_AUD_CLK_CNTL3 0x1a4 +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLK_CNTL 0x1bc + +#define HHI_HDMI_CLK_CNTL 0x1cc +#define HHI_VDEC_CLK_CNTL 0x1e0 +#define HHI_VDEC2_CLK_CNTL 0x1e4 +#define HHI_VDEC3_CLK_CNTL 0x1e8 +#define HHI_VDEC4_CLK_CNTL 0x1ec +#define HHI_HDCP22_CLK_CNTL 0x1f0 +#define HHI_VAPBCLK_CNTL 0x1f4 + +#define HHI_VPU_CLKB_CNTL 0x20c +#define HHI_USB_CLK_CNTL 0x220 +#define HHI_32K_CLK_CNTL 0x224 +#define HHI_GEN_CLK_CNTL 0x228 + +#define HHI_PCM_CLK_CNTL 0x258 +#define HHI_NAND_CLK_CNTL 0x25c +#define HHI_SD_EMMC_CLK_CNTL 0x264 + +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28c +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29c +#define HHI_MPLL_CNTL9 0x2a0 +#define HHI_MPLL_CNTL10 0x2a4 + +#define HHI_MPLL3_CNTL0 0x2e0 +#define HHI_MPLL3_CNTL1 0x2e4 +#define HHI_VDAC_CNTL0 0x2f4 +#define HHI_VDAC_CNTL1 0x2f8 + +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_SYS_PLL_CNTL2 0x304 +#define HHI_SYS_PLL_CNTL3 0x308 +#define HHI_SYS_PLL_CNTL4 0x30c +#define HHI_SYS_PLL_CNTL5 0x310 +#define HHI_DPLL_TOP_I 0x318 +#define HHI_DPLL_TOP2_I 0x31c +#define HHI_HDMI_PLL_CNTL 0x320 +#define HHI_HDMI_PLL_CNTL2 0x324 +#define HHI_HDMI_PLL_CNTL3 0x328 +#define HHI_HDMI_PLL_CNTL4 0x32c +#define HHI_HDMI_PLL_CNTL5 0x330 +#define HHI_HDMI_PLL_CNTL6 0x334 +#define HHI_HDMI_PLL_CNTL_I 0x338 +#define HHI_HDMI_PLL_CNTL7 0x33c + +#define HHI_HDMI_PHY_CNTL0 0x3a0 +#define HHI_HDMI_PHY_CNTL1 0x3a4 +#define HHI_HDMI_PHY_CNTL2 0x3a8 +#define HHI_HDMI_PHY_CNTL3 0x3ac + +#define HHI_VID_LOCK_CLK_CNTL 0x3c8 +#define HHI_BT656_CLK_CNTL 0x3d4 +#define HHI_SAR_CLK_CNTL 0x3d8 + static const struct pll_params_table gxbb_gp0_pll_params_table[] = { PLL_PARAMS(32, 1), PLL_PARAMS(33, 1), diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h deleted file mode 100644 index ba5f39a8d746..000000000000 --- a/drivers/clk/meson/gxbb.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 AmLogic, Inc. - * Author: Michael Turquette - */ - -#ifndef __GXBB_H -#define __GXBB_H - -/* - * Clock controller register offsets - * - * Register offsets from the data sheet are listed in comment blocks below. - * Those offsets must be multiplied by 4 before adding them to the base address - * to get the right value - */ -#define SCR 0x2C /* 0x0b offset in data sheet */ -#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ - -#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ -#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ -#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ -#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ -#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ -#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ - -#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ -#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ - -#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ -#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ -#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ -#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ -#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ - -#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ -#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ -#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ -#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ -#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ -#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ -#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ -#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ - -#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ -#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ -#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ -#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ -#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ -#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ -#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ -#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ -#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ - -#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ -#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ -#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ -#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ -#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ -#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ -#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ - -#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ -#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ -#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ -#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ - -#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ -#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ -#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ - -#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ -#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ -#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ -#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ -#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ -#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ -#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */ -#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */ -#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */ -#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */ - -#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ -#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ -#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ -#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ - -#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ -#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ -#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ -#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ -#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ -#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ -#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ -#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ -#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ -#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ -#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ -#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ -#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ - -#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ -#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ -#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ -#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ - -#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ -#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ -#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ - -#endif /* __GXBB_H */ diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index e4b474c5f86c..cff07006016b 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -16,7 +16,6 @@ #include #include -#include "meson8b.h" #include "clk-regmap.h" #include "meson-clkc-utils.h" #include "clk-pll.h" @@ -25,6 +24,72 @@ #include #include +/* + * Clock controller register offsets + * + * Register offsets from the HardKernel[0] data sheet must be multiplied + * by 4 before adding them to the base address to get the right value + * + * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf + */ +#define HHI_GP_PLL_CNTL 0x40 +#define HHI_GP_PLL_CNTL2 0x44 +#define HHI_GP_PLL_CNTL3 0x48 +#define HHI_GP_PLL_CNTL4 0x4C +#define HHI_GP_PLL_CNTL5 0x50 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_AUD_CLK_CNTL2 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_VID_DIVIDER_CNTL 0x198 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLK_CNTL 0x1bc +#define HHI_HDMI_CLK_CNTL 0x1cc +#define HHI_VDEC_CLK_CNTL 0x1e0 +#define HHI_VDEC2_CLK_CNTL 0x1e4 +#define HHI_VDEC3_CLK_CNTL 0x1e8 +#define HHI_NAND_CLK_CNTL 0x25c +#define HHI_MPLL_CNTL 0x280 +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_VID_PLL_CNTL 0x320 +#define HHI_VID_PLL_CNTL2 0x324 +#define HHI_VID_PLL_CNTL3 0x328 +#define HHI_VID_PLL_CNTL4 0x32c +#define HHI_VID_PLL_CNTL5 0x330 +#define HHI_VID_PLL_CNTL6 0x334 +#define HHI_VID2_PLL_CNTL 0x380 +#define HHI_VID2_PLL_CNTL2 0x384 +#define HHI_VID2_PLL_CNTL3 0x388 +#define HHI_VID2_PLL_CNTL4 0x38c +#define HHI_VID2_PLL_CNTL5 0x390 +#define HHI_VID2_PLL_CNTL6 0x394 + +/* + * MPLL register offeset taken from the S905 datasheet. Vendor kernel source + * confirm these are the same for the S805. + */ +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28c +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29c +#define HHI_MPLL_CNTL9 0x2a0 +#define HHI_MPLL_CNTL10 0x2a4 + struct meson8b_clk_reset { struct reset_controller_dev reset; struct regmap *regmap; diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h deleted file mode 100644 index a5b6e67eeefb..000000000000 --- a/drivers/clk/meson/meson8b.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015 Endless Mobile, Inc. - * Author: Carlo Caione - * - * Copyright (c) 2016 BayLibre, Inc. - * Michael Turquette - */ - -#ifndef __MESON8B_H -#define __MESON8B_H - -/* - * Clock controller register offsets - * - * Register offsets from the HardKernel[0] data sheet are listed in comment - * blocks below. Those offsets must be multiplied by 4 before adding them to - * the base address to get the right value - * - * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf - */ -#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ -#define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ -#define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ -#define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */ -#define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ -#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ -#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ -#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ -#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ -#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ -#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ -#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ -#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ -#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ -#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ -#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ -#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ -#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ -#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ -#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ -#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ -#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */ -#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ -#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */ -#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */ -#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */ -#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */ -#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ -#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ -#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ -#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ -#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ -#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */ -#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ -#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ -#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */ -#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */ -#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */ -#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */ -#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */ -#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */ - -/* - * MPLL register offeset taken from the S905 datasheet. Vendor kernel source - * confirm these are the same for the S805. - */ -#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ -#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ -#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ -#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ -#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ -#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ -#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ -#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ -#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ -#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */ - -#endif /* __MESON8B_H */ diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c index 8a4037377787..4c663dc33572 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -13,10 +13,55 @@ #include "clk-regmap.h" #include "vid-pll-div.h" #include "clk-dualdiv.h" -#include "s4-peripherals.h" #include "meson-clkc-utils.h" #include +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c +#define CLKCTRL_RTC_CTRL 0x010 +#define CLKCTRL_SYS_CLK_CTRL0 0x040 +#define CLKCTRL_SYS_CLK_EN0_REG0 0x044 +#define CLKCTRL_SYS_CLK_EN0_REG1 0x048 +#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c +#define CLKCTRL_SYS_CLK_EN0_REG3 0x050 +#define CLKCTRL_CECA_CTRL0 0x088 +#define CLKCTRL_CECA_CTRL1 0x08c +#define CLKCTRL_CECB_CTRL0 0x090 +#define CLKCTRL_CECB_CTRL1 0x094 +#define CLKCTRL_SC_CLK_CTRL 0x098 +#define CLKCTRL_CLK12_24_CTRL 0x0a8 +#define CLKCTRL_VID_CLK_CTRL 0x0c0 +#define CLKCTRL_VID_CLK_CTRL2 0x0c4 +#define CLKCTRL_VID_CLK_DIV 0x0c8 +#define CLKCTRL_VIID_CLK_DIV 0x0cc +#define CLKCTRL_VIID_CLK_CTRL 0x0d0 +#define CLKCTRL_HDMI_CLK_CTRL 0x0e0 +#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 +#define CLKCTRL_VPU_CLK_CTRL 0x0e8 +#define CLKCTRL_VPU_CLKB_CTRL 0x0ec +#define CLKCTRL_VPU_CLKC_CTRL 0x0f0 +#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4 +#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 +#define CLKCTRL_VAPBCLK_CTRL 0x0fc +#define CLKCTRL_HDCP22_CTRL 0x100 +#define CLKCTRL_VDEC_CLK_CTRL 0x140 +#define CLKCTRL_VDEC2_CLK_CTRL 0x144 +#define CLKCTRL_VDEC3_CLK_CTRL 0x148 +#define CLKCTRL_VDEC4_CLK_CTRL 0x14c +#define CLKCTRL_TS_CLK_CTRL 0x158 +#define CLKCTRL_MALI_CLK_CTRL 0x15c +#define CLKCTRL_NAND_CLK_CTRL 0x168 +#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c +#define CLKCTRL_SPICC_CLK_CTRL 0x174 +#define CLKCTRL_GEN_CLK_CTRL 0x178 +#define CLKCTRL_SAR_CLK_CTRL 0x17c +#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 +#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 +#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 +#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c +#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 +#define CLKCTRL_DEMOD_CLK_CTRL 0x200 + static struct clk_regmap s4_rtc_32k_by_oscin_clkin = { .data = &(struct clk_regmap_gate_data){ .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, diff --git a/drivers/clk/meson/s4-peripherals.h b/drivers/clk/meson/s4-peripherals.h deleted file mode 100644 index 1e298713c2b2..000000000000 --- a/drivers/clk/meson/s4-peripherals.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved - * Author: Yu Tu - */ - -#ifndef __MESON_S4_PERIPHERALS_H__ -#define __MESON_S4_PERIPHERALS_H__ - -#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 -#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c -#define CLKCTRL_RTC_CTRL 0x010 -#define CLKCTRL_SYS_CLK_CTRL0 0x040 -#define CLKCTRL_SYS_CLK_EN0_REG0 0x044 -#define CLKCTRL_SYS_CLK_EN0_REG1 0x048 -#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c -#define CLKCTRL_SYS_CLK_EN0_REG3 0x050 -#define CLKCTRL_CECA_CTRL0 0x088 -#define CLKCTRL_CECA_CTRL1 0x08c -#define CLKCTRL_CECB_CTRL0 0x090 -#define CLKCTRL_CECB_CTRL1 0x094 -#define CLKCTRL_SC_CLK_CTRL 0x098 -#define CLKCTRL_CLK12_24_CTRL 0x0a8 -#define CLKCTRL_VID_CLK_CTRL 0x0c0 -#define CLKCTRL_VID_CLK_CTRL2 0x0c4 -#define CLKCTRL_VID_CLK_DIV 0x0c8 -#define CLKCTRL_VIID_CLK_DIV 0x0cc -#define CLKCTRL_VIID_CLK_CTRL 0x0d0 -#define CLKCTRL_HDMI_CLK_CTRL 0x0e0 -#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 -#define CLKCTRL_VPU_CLK_CTRL 0x0e8 -#define CLKCTRL_VPU_CLKB_CTRL 0x0ec -#define CLKCTRL_VPU_CLKC_CTRL 0x0f0 -#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4 -#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 -#define CLKCTRL_VAPBCLK_CTRL 0x0fc -#define CLKCTRL_HDCP22_CTRL 0x100 -#define CLKCTRL_VDEC_CLK_CTRL 0x140 -#define CLKCTRL_VDEC2_CLK_CTRL 0x144 -#define CLKCTRL_VDEC3_CLK_CTRL 0x148 -#define CLKCTRL_VDEC4_CLK_CTRL 0x14c -#define CLKCTRL_TS_CLK_CTRL 0x158 -#define CLKCTRL_MALI_CLK_CTRL 0x15c -#define CLKCTRL_NAND_CLK_CTRL 0x168 -#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c -#define CLKCTRL_SPICC_CLK_CTRL 0x174 -#define CLKCTRL_GEN_CLK_CTRL 0x178 -#define CLKCTRL_SAR_CLK_CTRL 0x17c -#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 -#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 -#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 -#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c -#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 -#define CLKCTRL_DEMOD_CLK_CTRL 0x200 - -#endif /* __MESON_S4_PERIPHERALS_H__ */ diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index f9cc05a506e3..911a590d206f 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -13,10 +13,37 @@ #include "clk-mpll.h" #include "clk-pll.h" #include "clk-regmap.h" -#include "s4-pll.h" #include "meson-clkc-utils.h" #include +#define ANACTRL_FIXPLL_CTRL0 0x040 +#define ANACTRL_FIXPLL_CTRL1 0x044 +#define ANACTRL_FIXPLL_CTRL3 0x04c +#define ANACTRL_GP0PLL_CTRL0 0x080 +#define ANACTRL_GP0PLL_CTRL1 0x084 +#define ANACTRL_GP0PLL_CTRL2 0x088 +#define ANACTRL_GP0PLL_CTRL3 0x08c +#define ANACTRL_GP0PLL_CTRL4 0x090 +#define ANACTRL_GP0PLL_CTRL5 0x094 +#define ANACTRL_GP0PLL_CTRL6 0x098 +#define ANACTRL_HIFIPLL_CTRL0 0x100 +#define ANACTRL_HIFIPLL_CTRL1 0x104 +#define ANACTRL_HIFIPLL_CTRL2 0x108 +#define ANACTRL_HIFIPLL_CTRL3 0x10c +#define ANACTRL_HIFIPLL_CTRL4 0x110 +#define ANACTRL_HIFIPLL_CTRL5 0x114 +#define ANACTRL_HIFIPLL_CTRL6 0x118 +#define ANACTRL_MPLL_CTRL0 0x180 +#define ANACTRL_MPLL_CTRL1 0x184 +#define ANACTRL_MPLL_CTRL2 0x188 +#define ANACTRL_MPLL_CTRL3 0x18c +#define ANACTRL_MPLL_CTRL4 0x190 +#define ANACTRL_MPLL_CTRL5 0x194 +#define ANACTRL_MPLL_CTRL6 0x198 +#define ANACTRL_MPLL_CTRL7 0x19c +#define ANACTRL_MPLL_CTRL8 0x1a0 +#define ANACTRL_HDMIPLL_CTRL0 0x1c0 + /* * These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode. * The chip was changed fixed pll for security reasons. Fixed PLL registers are not writable diff --git a/drivers/clk/meson/s4-pll.h b/drivers/clk/meson/s4-pll.h deleted file mode 100644 index ff7d58302f2a..000000000000 --- a/drivers/clk/meson/s4-pll.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved - * Author: Yu Tu - */ - -#ifndef __MESON_S4_PLL_H__ -#define __MESON_S4_PLL_H__ - -#define ANACTRL_FIXPLL_CTRL0 0x040 -#define ANACTRL_FIXPLL_CTRL1 0x044 -#define ANACTRL_FIXPLL_CTRL3 0x04c -#define ANACTRL_GP0PLL_CTRL0 0x080 -#define ANACTRL_GP0PLL_CTRL1 0x084 -#define ANACTRL_GP0PLL_CTRL2 0x088 -#define ANACTRL_GP0PLL_CTRL3 0x08c -#define ANACTRL_GP0PLL_CTRL4 0x090 -#define ANACTRL_GP0PLL_CTRL5 0x094 -#define ANACTRL_GP0PLL_CTRL6 0x098 -#define ANACTRL_HIFIPLL_CTRL0 0x100 -#define ANACTRL_HIFIPLL_CTRL1 0x104 -#define ANACTRL_HIFIPLL_CTRL2 0x108 -#define ANACTRL_HIFIPLL_CTRL3 0x10c -#define ANACTRL_HIFIPLL_CTRL4 0x110 -#define ANACTRL_HIFIPLL_CTRL5 0x114 -#define ANACTRL_HIFIPLL_CTRL6 0x118 -#define ANACTRL_MPLL_CTRL0 0x180 -#define ANACTRL_MPLL_CTRL1 0x184 -#define ANACTRL_MPLL_CTRL2 0x188 -#define ANACTRL_MPLL_CTRL3 0x18c -#define ANACTRL_MPLL_CTRL4 0x190 -#define ANACTRL_MPLL_CTRL5 0x194 -#define ANACTRL_MPLL_CTRL6 0x198 -#define ANACTRL_MPLL_CTRL7 0x19c -#define ANACTRL_MPLL_CTRL8 0x1a0 -#define ANACTRL_HDMIPLL_CTRL0 0x1c0 - -#endif /* __MESON_S4_PLL_H__ */ From 21ed19d1186314940d4300c39bf54fe0a410ee44 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 23 Jun 2025 18:37:37 +0200 Subject: [PATCH 6/8] clk: amlogic: get regmap with clk_regmap_init Add clk_regmap_init() and use it with all clock types which derive from clk_regmap. This helps initialise clk_regmap clocks without requiring tables to keep track of the clock using this type. The way it is done couples clk_regmap with the controllers, which is not ideal. This is a temporary solution to get rid of the tables. The situation will eventually be improved. Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-1-ff04918211cc@baylibre.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 1 + drivers/clk/meson/clk-cpu-dyndiv.c | 1 + drivers/clk/meson/clk-dualdiv.c | 2 ++ drivers/clk/meson/clk-mpll.c | 6 ++++ drivers/clk/meson/clk-phase.c | 11 +++++++ drivers/clk/meson/clk-pll.c | 7 +++++ drivers/clk/meson/clk-regmap.c | 49 ++++++++++++++++++++++++++++++ drivers/clk/meson/clk-regmap.h | 4 +++ drivers/clk/meson/sclk-div.c | 5 +++ drivers/clk/meson/vclk.c | 2 ++ drivers/clk/meson/vid-pll-div.c | 1 + 11 files changed, 89 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 5c669b2e2f26..7197d23543b8 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -5,6 +5,7 @@ menu "Clock support for Amlogic platforms" config COMMON_CLK_MESON_REGMAP tristate select REGMAP + select MFD_SYSCON config COMMON_CLK_MESON_DUALDIV tristate diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c index cb043b52b65d..83aedbfd2891 100644 --- a/drivers/clk/meson/clk-cpu-dyndiv.c +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -61,6 +61,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, }; const struct clk_ops meson_clk_cpu_dyndiv_ops = { + .init = clk_regmap_init, .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate, .determine_rate = meson_clk_cpu_dyndiv_determine_rate, .set_rate = meson_clk_cpu_dyndiv_set_rate, diff --git a/drivers/clk/meson/clk-dualdiv.c b/drivers/clk/meson/clk-dualdiv.c index c896cf29b318..787df6cdf841 100644 --- a/drivers/clk/meson/clk-dualdiv.c +++ b/drivers/clk/meson/clk-dualdiv.c @@ -126,6 +126,7 @@ static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate, } const struct clk_ops meson_clk_dualdiv_ops = { + .init = clk_regmap_init, .recalc_rate = meson_clk_dualdiv_recalc_rate, .determine_rate = meson_clk_dualdiv_determine_rate, .set_rate = meson_clk_dualdiv_set_rate, @@ -133,6 +134,7 @@ const struct clk_ops meson_clk_dualdiv_ops = { EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ops, "CLK_MESON"); const struct clk_ops meson_clk_dualdiv_ro_ops = { + .init = clk_regmap_init, .recalc_rate = meson_clk_dualdiv_recalc_rate, }; EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ro_ops, "CLK_MESON"); diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index ee91e32b4050..7f8dada66e16 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -128,6 +128,11 @@ static int mpll_init(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); + int ret; + + ret = clk_regmap_init(hw); + if (ret) + return ret; if (mpll->init_count) regmap_multi_reg_write(clk->map, mpll->init_regs, @@ -151,6 +156,7 @@ static int mpll_init(struct clk_hw *hw) } const struct clk_ops meson_clk_mpll_ro_ops = { + .init = clk_regmap_init, .recalc_rate = mpll_recalc_rate, .determine_rate = mpll_determine_rate, }; diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c index 701211120610..58dd982e6878 100644 --- a/drivers/clk/meson/clk-phase.c +++ b/drivers/clk/meson/clk-phase.c @@ -58,6 +58,7 @@ static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees) } const struct clk_ops meson_clk_phase_ops = { + .init = clk_regmap_init, .get_phase = meson_clk_phase_get_phase, .set_phase = meson_clk_phase_set_phase, }; @@ -83,6 +84,11 @@ static int meson_clk_triphase_sync(struct clk_hw *hw) struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk); unsigned int val; + int ret; + + ret = clk_regmap_init(hw); + if (ret) + return ret; /* Get phase 0 and sync it to phase 1 and 2 */ val = meson_parm_read(clk->map, &tph->ph0); @@ -142,6 +148,11 @@ static int meson_sclk_ws_inv_sync(struct clk_hw *hw) struct clk_regmap *clk = to_clk_regmap(hw); struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk); unsigned int val; + int ret; + + ret = clk_regmap_init(hw); + if (ret) + return ret; /* Get phase and sync the inverted value to ws */ val = meson_parm_read(clk->map, &tph->ph); diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index e8e53855b00a..1ea6579a760f 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -311,6 +311,11 @@ static int meson_clk_pll_init(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + int ret; + + ret = clk_regmap_init(hw); + if (ret) + return ret; /* * Keep the clock running, which was already initialized and enabled @@ -468,6 +473,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, * the other ops except set_rate since the rate is fixed. */ const struct clk_ops meson_clk_pcie_pll_ops = { + .init = clk_regmap_init, .recalc_rate = meson_clk_pll_recalc_rate, .determine_rate = meson_clk_pll_determine_rate, .is_enabled = meson_clk_pll_is_enabled, @@ -488,6 +494,7 @@ const struct clk_ops meson_clk_pll_ops = { EXPORT_SYMBOL_NS_GPL(meson_clk_pll_ops, "CLK_MESON"); const struct clk_ops meson_clk_pll_ro_ops = { + .init = clk_regmap_init, .recalc_rate = meson_clk_pll_recalc_rate, .is_enabled = meson_clk_pll_is_enabled, }; diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c index f3e504f67571..1ed56fe63cae 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/meson/clk-regmap.c @@ -4,9 +4,52 @@ * Author: Jerome Brunet */ +#include #include +#include #include "clk-regmap.h" +int clk_regmap_init(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct device_node *np, *parent_np; + struct device *dev; + + /* Allow regmap to be preset as it was historically done */ + if (clk->map) + return 0; + + /* + * FIXME: what follows couples the controller implementation + * and clk_regmap clock type. This situation is not desirable + * but temporary, until the controller is able to register + * a hook to initialize a clock type + */ + + /* Check the usual dev enabled controller with an basic IO regmap */ + dev = clk_hw_get_dev(hw); + if (dev) { + clk->map = dev_get_regmap(dev, NULL); + if (clk->map) + return 0; + } + + /* Move on to early and syscon based controllers */ + np = clk_hw_get_of_node(hw); + if (np) { + parent_np = of_get_parent(np); + clk->map = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + + if (!IS_ERR_OR_NULL(clk->map)) + return 0; + } + + /* Bail out if regmap can't be found */ + return -EINVAL; +} +EXPORT_SYMBOL_NS_GPL(clk_regmap_init, "CLK_MESON"); + static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable) { struct clk_regmap *clk = to_clk_regmap(hw); @@ -45,6 +88,7 @@ static int clk_regmap_gate_is_enabled(struct clk_hw *hw) } const struct clk_ops clk_regmap_gate_ops = { + .init = clk_regmap_init, .enable = clk_regmap_gate_enable, .disable = clk_regmap_gate_disable, .is_enabled = clk_regmap_gate_is_enabled, @@ -52,6 +96,7 @@ const struct clk_ops clk_regmap_gate_ops = { EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ops, "CLK_MESON"); const struct clk_ops clk_regmap_gate_ro_ops = { + .init = clk_regmap_init, .is_enabled = clk_regmap_gate_is_enabled, }; EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ro_ops, "CLK_MESON"); @@ -121,6 +166,7 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, /* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ const struct clk_ops clk_regmap_divider_ops = { + .init = clk_regmap_init, .recalc_rate = clk_regmap_div_recalc_rate, .determine_rate = clk_regmap_div_determine_rate, .set_rate = clk_regmap_div_set_rate, @@ -128,6 +174,7 @@ const struct clk_ops clk_regmap_divider_ops = { EXPORT_SYMBOL_NS_GPL(clk_regmap_divider_ops, "CLK_MESON"); const struct clk_ops clk_regmap_divider_ro_ops = { + .init = clk_regmap_init, .recalc_rate = clk_regmap_div_recalc_rate, .determine_rate = clk_regmap_div_determine_rate, }; @@ -170,6 +217,7 @@ static int clk_regmap_mux_determine_rate(struct clk_hw *hw, } const struct clk_ops clk_regmap_mux_ops = { + .init = clk_regmap_init, .get_parent = clk_regmap_mux_get_parent, .set_parent = clk_regmap_mux_set_parent, .determine_rate = clk_regmap_mux_determine_rate, @@ -177,6 +225,7 @@ const struct clk_ops clk_regmap_mux_ops = { EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ops, "CLK_MESON"); const struct clk_ops clk_regmap_mux_ro_ops = { + .init = clk_regmap_init, .get_parent = clk_regmap_mux_get_parent, }; EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ro_ops, "CLK_MESON"); diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index e365312da54e..f8cac2df5755 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -7,6 +7,7 @@ #ifndef __CLK_REGMAP_H #define __CLK_REGMAP_H +#include #include #include @@ -31,6 +32,9 @@ static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) return container_of(hw, struct clk_regmap, hw); } +/* clk_regmap init op to get and cache regmap from the controllers */ +int clk_regmap_init(struct clk_hw *hw); + /** * struct clk_regmap_gate_data - regmap backed gate specific data * diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c index 9c4945234f26..4ba3d82810e8 100644 --- a/drivers/clk/meson/sclk-div.c +++ b/drivers/clk/meson/sclk-div.c @@ -222,6 +222,11 @@ static int sclk_div_init(struct clk_hw *hw) struct clk_regmap *clk = to_clk_regmap(hw); struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); unsigned int val; + int ret; + + ret = clk_regmap_init(hw); + if (ret) + return ret; val = meson_parm_read(clk->map, &sclk->div); diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c index 6a167ebdc8d7..009bd1193042 100644 --- a/drivers/clk/meson/vclk.c +++ b/drivers/clk/meson/vclk.c @@ -45,6 +45,7 @@ static int meson_vclk_gate_is_enabled(struct clk_hw *hw) } const struct clk_ops meson_vclk_gate_ops = { + .init = clk_regmap_init, .enable = meson_vclk_gate_enable, .disable = meson_vclk_gate_disable, .is_enabled = meson_vclk_gate_is_enabled, @@ -127,6 +128,7 @@ static int meson_vclk_div_is_enabled(struct clk_hw *hw) } const struct clk_ops meson_vclk_div_ops = { + .init = clk_regmap_init, .recalc_rate = meson_vclk_div_recalc_rate, .determine_rate = meson_vclk_div_determine_rate, .set_rate = meson_vclk_div_set_rate, diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-div.c index 965ed7281f57..2a3cdbe6d86a 100644 --- a/drivers/clk/meson/vid-pll-div.c +++ b/drivers/clk/meson/vid-pll-div.c @@ -90,6 +90,7 @@ static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw, } const struct clk_ops meson_vid_pll_div_ro_ops = { + .init = clk_regmap_init, .recalc_rate = meson_vid_pll_div_recalc_rate, }; EXPORT_SYMBOL_NS_GPL(meson_vid_pll_div_ro_ops, "CLK_MESON"); From 4cb53fff9db2751f9d94e45c3bcac13f4be4458b Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 23 Jun 2025 18:37:38 +0200 Subject: [PATCH 7/8] clk: amlogic: drop clk_regmap tables Remove the clk_regmap tables that are used to keep track which clock need to be initialised before being registered. The initialisation is now done by the .init() operation of clk_regmap. This rework saves a bit memory and makes maintenance a bit easier. Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-2-ff04918211cc@baylibre.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-peripherals.c | 163 +---------- drivers/clk/meson/a1-pll.c | 16 +- drivers/clk/meson/axg-aoclk.c | 22 -- drivers/clk/meson/axg-audio.c | 433 ----------------------------- drivers/clk/meson/axg.c | 131 --------- drivers/clk/meson/c3-peripherals.c | 210 +------------- drivers/clk/meson/c3-pll.c | 32 +-- drivers/clk/meson/g12a-aoclk.c | 34 --- drivers/clk/meson/g12a.c | 261 ----------------- drivers/clk/meson/gxbb-aoclk.c | 19 -- drivers/clk/meson/gxbb.c | 393 -------------------------- drivers/clk/meson/meson-aoclk.c | 5 +- drivers/clk/meson/meson-aoclk.h | 2 - drivers/clk/meson/meson-eeclk.c | 4 - drivers/clk/meson/meson-eeclk.h | 2 - drivers/clk/meson/meson8-ddr.c | 9 - drivers/clk/meson/meson8b.c | 200 ------------- drivers/clk/meson/s4-peripherals.c | 229 --------------- drivers/clk/meson/s4-pll.c | 31 --- 19 files changed, 5 insertions(+), 2191 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c index 8ae02df3490b..1f5d445d44fe 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -2055,163 +2055,6 @@ static struct clk_hw *a1_periphs_hw_clks[] = { [CLKID_DMC_SEL2] = &dmc_sel2.hw, }; -/* Convenience table to populate regmap in .probe */ -static struct clk_regmap *const a1_periphs_regmaps[] = { - &xtal_in, - &fixpll_in, - &usb_phy_in, - &usb_ctrl_in, - &hifipll_in, - &syspll_in, - &dds_in, - &sys, - &clktree, - &reset_ctrl, - &analog_ctrl, - &pwr_ctrl, - &pad_ctrl, - &sys_ctrl, - &temp_sensor, - &am2axi_dev, - &spicc_b, - &spicc_a, - &msr, - &audio, - &jtag_ctrl, - &saradc_en, - &pwm_ef, - &pwm_cd, - &pwm_ab, - &cec, - &i2c_s, - &ir_ctrl, - &i2c_m_d, - &i2c_m_c, - &i2c_m_b, - &i2c_m_a, - &acodec, - &otp, - &sd_emmc_a, - &usb_phy, - &usb_ctrl, - &sys_dspb, - &sys_dspa, - &dma, - &irq_ctrl, - &nic, - &gic, - &uart_c, - &uart_b, - &uart_a, - &sys_psram, - &rsa, - &coresight, - &am2axi_vad, - &audio_vad, - &axi_dmc, - &axi_psram, - &ramb, - &rama, - &axi_spifc, - &axi_nic, - &axi_dma, - &cpu_ctrl, - &rom, - &prod_i2c, - &dspa_sel, - &dspb_sel, - &dspa_en, - &dspa_en_nic, - &dspb_en, - &dspb_en_nic, - &rtc, - &ceca_32k_out, - &cecb_32k_out, - &clk_24m, - &clk_12m, - &fclk_div2_divn, - &gen, - &saradc_sel, - &saradc, - &pwm_a, - &pwm_b, - &pwm_c, - &pwm_d, - &pwm_e, - &pwm_f, - &spicc, - &ts, - &spifc, - &usb_bus, - &sd_emmc, - &psram, - &dmc, - &sys_a_sel, - &sys_a_div, - &sys_a, - &sys_b_sel, - &sys_b_div, - &sys_b, - &dspa_a_sel, - &dspa_a_div, - &dspa_a, - &dspa_b_sel, - &dspa_b_div, - &dspa_b, - &dspb_a_sel, - &dspb_a_div, - &dspb_a, - &dspb_b_sel, - &dspb_b_div, - &dspb_b, - &rtc_32k_in, - &rtc_32k_div, - &rtc_32k_xtal, - &rtc_32k_sel, - &cecb_32k_in, - &cecb_32k_div, - &cecb_32k_sel_pre, - &cecb_32k_sel, - &ceca_32k_in, - &ceca_32k_div, - &ceca_32k_sel_pre, - &ceca_32k_sel, - &fclk_div2_divn_pre, - &gen_sel, - &gen_div, - &saradc_div, - &pwm_a_sel, - &pwm_a_div, - &pwm_b_sel, - &pwm_b_div, - &pwm_c_sel, - &pwm_c_div, - &pwm_d_sel, - &pwm_d_div, - &pwm_e_sel, - &pwm_e_div, - &pwm_f_sel, - &pwm_f_div, - &spicc_sel, - &spicc_div, - &spicc_sel2, - &ts_div, - &spifc_sel, - &spifc_div, - &spifc_sel2, - &usb_bus_sel, - &usb_bus_div, - &sd_emmc_sel, - &sd_emmc_div, - &sd_emmc_sel2, - &psram_sel, - &psram_div, - &psram_sel2, - &dmc_sel, - &dmc_div, - &dmc_sel2, -}; - static const struct regmap_config a1_periphs_regmap_cfg = { .reg_bits = 32, .val_bits = 32, @@ -2229,7 +2072,7 @@ static int meson_a1_periphs_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; void __iomem *base; struct regmap *map; - int clkid, i, err; + int clkid, err; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -2241,10 +2084,6 @@ static int meson_a1_periphs_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(map), "can't init regmap mmio region\n"); - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++) - a1_periphs_regmaps[i]->map = map; - for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) { err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]); if (err) diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index f0ba283cf1d0..dabd4fad1f57 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -295,16 +295,6 @@ static struct clk_hw *a1_pll_hw_clks[] = { [CLKID_HIFI_PLL] = &hifi_pll.hw, }; -static struct clk_regmap *const a1_pll_regmaps[] = { - &fixed_pll_dco, - &fixed_pll, - &fclk_div2, - &fclk_div3, - &fclk_div5, - &fclk_div7, - &hifi_pll, -}; - static const struct regmap_config a1_pll_regmap_cfg = { .reg_bits = 32, .val_bits = 32, @@ -322,7 +312,7 @@ static int meson_a1_pll_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; void __iomem *base; struct regmap *map; - int clkid, i, err; + int clkid, err; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -334,10 +324,6 @@ static int meson_a1_pll_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(map), "can't init regmap mmio region\n"); - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++) - a1_pll_regmaps[i]->map = map; - /* Register clocks */ for (clkid = 0; clkid < a1_pll_clks.num; clkid++) { err = devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]); diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index f44091ffb57d..cd5d0b5ebdb2 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -270,26 +270,6 @@ static const unsigned int axg_aoclk_reset[] = { [RESET_AO_IR_BLASTER] = 23, }; -static struct clk_regmap *axg_aoclk_regmap[] = { - &axg_aoclk_remote, - &axg_aoclk_i2c_master, - &axg_aoclk_i2c_slave, - &axg_aoclk_uart1, - &axg_aoclk_uart2, - &axg_aoclk_ir_blaster, - &axg_aoclk_saradc, - &axg_aoclk_cts_oscin, - &axg_aoclk_32k_pre, - &axg_aoclk_32k_div, - &axg_aoclk_32k_sel, - &axg_aoclk_32k, - &axg_aoclk_cts_rtc_oscin, - &axg_aoclk_clk81, - &axg_aoclk_saradc_mux, - &axg_aoclk_saradc_div, - &axg_aoclk_saradc_gate, -}; - static struct clk_hw *axg_aoclk_hw_clks[] = { [CLKID_AO_REMOTE] = &axg_aoclk_remote.hw, [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw, @@ -314,8 +294,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = { .reset_reg = AO_RTI_GEN_CNTL_REG0, .num_reset = ARRAY_SIZE(axg_aoclk_reset), .reset = axg_aoclk_reset, - .num_clks = ARRAY_SIZE(axg_aoclk_regmap), - .clks = axg_aoclk_regmap, .hw_clks = { .hws = axg_aoclk_hw_clks, .num = ARRAY_SIZE(axg_aoclk_hw_clks), diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index cb556eb1630d..fd7eca652261 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -1311,427 +1311,6 @@ static struct clk_hw *sm1_audio_hw_clks[] = { [AUD_CLKID_EARCRX_DMAC] = &sm1_earcrx_dmac_clk.hw, }; - -/* Convenience table to populate regmap in .probe(). */ -static struct clk_regmap *const axg_clk_regmaps[] = { - &ddr_arb, - &pdm, - &tdmin_a, - &tdmin_b, - &tdmin_c, - &tdmin_lb, - &tdmout_a, - &tdmout_b, - &tdmout_c, - &frddr_a, - &frddr_b, - &frddr_c, - &toddr_a, - &toddr_b, - &toddr_c, - &loopback, - &spdifin, - &spdifout, - &resample, - &power_detect, - &mst_a_mclk_sel, - &mst_b_mclk_sel, - &mst_c_mclk_sel, - &mst_d_mclk_sel, - &mst_e_mclk_sel, - &mst_f_mclk_sel, - &mst_a_mclk_div, - &mst_b_mclk_div, - &mst_c_mclk_div, - &mst_d_mclk_div, - &mst_e_mclk_div, - &mst_f_mclk_div, - &mst_a_mclk, - &mst_b_mclk, - &mst_c_mclk, - &mst_d_mclk, - &mst_e_mclk, - &mst_f_mclk, - &spdifout_clk_sel, - &spdifout_clk_div, - &spdifout_clk, - &spdifin_clk_sel, - &spdifin_clk_div, - &spdifin_clk, - &pdm_dclk_sel, - &pdm_dclk_div, - &pdm_dclk, - &pdm_sysclk_sel, - &pdm_sysclk_div, - &pdm_sysclk, - &mst_a_sclk_pre_en, - &mst_b_sclk_pre_en, - &mst_c_sclk_pre_en, - &mst_d_sclk_pre_en, - &mst_e_sclk_pre_en, - &mst_f_sclk_pre_en, - &mst_a_sclk_div, - &mst_b_sclk_div, - &mst_c_sclk_div, - &mst_d_sclk_div, - &mst_e_sclk_div, - &mst_f_sclk_div, - &mst_a_sclk_post_en, - &mst_b_sclk_post_en, - &mst_c_sclk_post_en, - &mst_d_sclk_post_en, - &mst_e_sclk_post_en, - &mst_f_sclk_post_en, - &mst_a_sclk, - &mst_b_sclk, - &mst_c_sclk, - &mst_d_sclk, - &mst_e_sclk, - &mst_f_sclk, - &mst_a_lrclk_div, - &mst_b_lrclk_div, - &mst_c_lrclk_div, - &mst_d_lrclk_div, - &mst_e_lrclk_div, - &mst_f_lrclk_div, - &mst_a_lrclk, - &mst_b_lrclk, - &mst_c_lrclk, - &mst_d_lrclk, - &mst_e_lrclk, - &mst_f_lrclk, - &tdmin_a_sclk_sel, - &tdmin_b_sclk_sel, - &tdmin_c_sclk_sel, - &tdmin_lb_sclk_sel, - &tdmout_a_sclk_sel, - &tdmout_b_sclk_sel, - &tdmout_c_sclk_sel, - &tdmin_a_sclk_pre_en, - &tdmin_b_sclk_pre_en, - &tdmin_c_sclk_pre_en, - &tdmin_lb_sclk_pre_en, - &tdmout_a_sclk_pre_en, - &tdmout_b_sclk_pre_en, - &tdmout_c_sclk_pre_en, - &tdmin_a_sclk_post_en, - &tdmin_b_sclk_post_en, - &tdmin_c_sclk_post_en, - &tdmin_lb_sclk_post_en, - &tdmout_a_sclk_post_en, - &tdmout_b_sclk_post_en, - &tdmout_c_sclk_post_en, - &tdmin_a_sclk, - &tdmin_b_sclk, - &tdmin_c_sclk, - &tdmin_lb_sclk, - &axg_tdmout_a_sclk, - &axg_tdmout_b_sclk, - &axg_tdmout_c_sclk, - &tdmin_a_lrclk, - &tdmin_b_lrclk, - &tdmin_c_lrclk, - &tdmin_lb_lrclk, - &tdmout_a_lrclk, - &tdmout_b_lrclk, - &tdmout_c_lrclk, -}; - -static struct clk_regmap *const g12a_clk_regmaps[] = { - &ddr_arb, - &pdm, - &tdmin_a, - &tdmin_b, - &tdmin_c, - &tdmin_lb, - &tdmout_a, - &tdmout_b, - &tdmout_c, - &frddr_a, - &frddr_b, - &frddr_c, - &toddr_a, - &toddr_b, - &toddr_c, - &loopback, - &spdifin, - &spdifout, - &resample, - &power_detect, - &spdifout_b, - &mst_a_mclk_sel, - &mst_b_mclk_sel, - &mst_c_mclk_sel, - &mst_d_mclk_sel, - &mst_e_mclk_sel, - &mst_f_mclk_sel, - &mst_a_mclk_div, - &mst_b_mclk_div, - &mst_c_mclk_div, - &mst_d_mclk_div, - &mst_e_mclk_div, - &mst_f_mclk_div, - &mst_a_mclk, - &mst_b_mclk, - &mst_c_mclk, - &mst_d_mclk, - &mst_e_mclk, - &mst_f_mclk, - &spdifout_clk_sel, - &spdifout_clk_div, - &spdifout_clk, - &spdifin_clk_sel, - &spdifin_clk_div, - &spdifin_clk, - &pdm_dclk_sel, - &pdm_dclk_div, - &pdm_dclk, - &pdm_sysclk_sel, - &pdm_sysclk_div, - &pdm_sysclk, - &mst_a_sclk_pre_en, - &mst_b_sclk_pre_en, - &mst_c_sclk_pre_en, - &mst_d_sclk_pre_en, - &mst_e_sclk_pre_en, - &mst_f_sclk_pre_en, - &mst_a_sclk_div, - &mst_b_sclk_div, - &mst_c_sclk_div, - &mst_d_sclk_div, - &mst_e_sclk_div, - &mst_f_sclk_div, - &mst_a_sclk_post_en, - &mst_b_sclk_post_en, - &mst_c_sclk_post_en, - &mst_d_sclk_post_en, - &mst_e_sclk_post_en, - &mst_f_sclk_post_en, - &mst_a_sclk, - &mst_b_sclk, - &mst_c_sclk, - &mst_d_sclk, - &mst_e_sclk, - &mst_f_sclk, - &mst_a_lrclk_div, - &mst_b_lrclk_div, - &mst_c_lrclk_div, - &mst_d_lrclk_div, - &mst_e_lrclk_div, - &mst_f_lrclk_div, - &mst_a_lrclk, - &mst_b_lrclk, - &mst_c_lrclk, - &mst_d_lrclk, - &mst_e_lrclk, - &mst_f_lrclk, - &tdmin_a_sclk_sel, - &tdmin_b_sclk_sel, - &tdmin_c_sclk_sel, - &tdmin_lb_sclk_sel, - &tdmout_a_sclk_sel, - &tdmout_b_sclk_sel, - &tdmout_c_sclk_sel, - &tdmin_a_sclk_pre_en, - &tdmin_b_sclk_pre_en, - &tdmin_c_sclk_pre_en, - &tdmin_lb_sclk_pre_en, - &tdmout_a_sclk_pre_en, - &tdmout_b_sclk_pre_en, - &tdmout_c_sclk_pre_en, - &tdmin_a_sclk_post_en, - &tdmin_b_sclk_post_en, - &tdmin_c_sclk_post_en, - &tdmin_lb_sclk_post_en, - &tdmout_a_sclk_post_en, - &tdmout_b_sclk_post_en, - &tdmout_c_sclk_post_en, - &tdmin_a_sclk, - &tdmin_b_sclk, - &tdmin_c_sclk, - &tdmin_lb_sclk, - &g12a_tdmout_a_sclk, - &g12a_tdmout_b_sclk, - &g12a_tdmout_c_sclk, - &tdmin_a_lrclk, - &tdmin_b_lrclk, - &tdmin_c_lrclk, - &tdmin_lb_lrclk, - &tdmout_a_lrclk, - &tdmout_b_lrclk, - &tdmout_c_lrclk, - &spdifout_b_clk_sel, - &spdifout_b_clk_div, - &spdifout_b_clk, - &g12a_tdm_mclk_pad_0, - &g12a_tdm_mclk_pad_1, - &g12a_tdm_lrclk_pad_0, - &g12a_tdm_lrclk_pad_1, - &g12a_tdm_lrclk_pad_2, - &g12a_tdm_sclk_pad_0, - &g12a_tdm_sclk_pad_1, - &g12a_tdm_sclk_pad_2, - &toram, - &eqdrc, -}; - -static struct clk_regmap *const sm1_clk_regmaps[] = { - &ddr_arb, - &pdm, - &tdmin_a, - &tdmin_b, - &tdmin_c, - &tdmin_lb, - &tdmout_a, - &tdmout_b, - &tdmout_c, - &frddr_a, - &frddr_b, - &frddr_c, - &toddr_a, - &toddr_b, - &toddr_c, - &loopback, - &spdifin, - &spdifout, - &resample, - &spdifout_b, - &sm1_mst_a_mclk_sel, - &sm1_mst_b_mclk_sel, - &sm1_mst_c_mclk_sel, - &sm1_mst_d_mclk_sel, - &sm1_mst_e_mclk_sel, - &sm1_mst_f_mclk_sel, - &sm1_mst_a_mclk_div, - &sm1_mst_b_mclk_div, - &sm1_mst_c_mclk_div, - &sm1_mst_d_mclk_div, - &sm1_mst_e_mclk_div, - &sm1_mst_f_mclk_div, - &sm1_mst_a_mclk, - &sm1_mst_b_mclk, - &sm1_mst_c_mclk, - &sm1_mst_d_mclk, - &sm1_mst_e_mclk, - &sm1_mst_f_mclk, - &spdifout_clk_sel, - &spdifout_clk_div, - &spdifout_clk, - &spdifin_clk_sel, - &spdifin_clk_div, - &spdifin_clk, - &pdm_dclk_sel, - &pdm_dclk_div, - &pdm_dclk, - &pdm_sysclk_sel, - &pdm_sysclk_div, - &pdm_sysclk, - &mst_a_sclk_pre_en, - &mst_b_sclk_pre_en, - &mst_c_sclk_pre_en, - &mst_d_sclk_pre_en, - &mst_e_sclk_pre_en, - &mst_f_sclk_pre_en, - &mst_a_sclk_div, - &mst_b_sclk_div, - &mst_c_sclk_div, - &mst_d_sclk_div, - &mst_e_sclk_div, - &mst_f_sclk_div, - &mst_a_sclk_post_en, - &mst_b_sclk_post_en, - &mst_c_sclk_post_en, - &mst_d_sclk_post_en, - &mst_e_sclk_post_en, - &mst_f_sclk_post_en, - &mst_a_sclk, - &mst_b_sclk, - &mst_c_sclk, - &mst_d_sclk, - &mst_e_sclk, - &mst_f_sclk, - &mst_a_lrclk_div, - &mst_b_lrclk_div, - &mst_c_lrclk_div, - &mst_d_lrclk_div, - &mst_e_lrclk_div, - &mst_f_lrclk_div, - &mst_a_lrclk, - &mst_b_lrclk, - &mst_c_lrclk, - &mst_d_lrclk, - &mst_e_lrclk, - &mst_f_lrclk, - &tdmin_a_sclk_sel, - &tdmin_b_sclk_sel, - &tdmin_c_sclk_sel, - &tdmin_lb_sclk_sel, - &tdmout_a_sclk_sel, - &tdmout_b_sclk_sel, - &tdmout_c_sclk_sel, - &tdmin_a_sclk_pre_en, - &tdmin_b_sclk_pre_en, - &tdmin_c_sclk_pre_en, - &tdmin_lb_sclk_pre_en, - &tdmout_a_sclk_pre_en, - &tdmout_b_sclk_pre_en, - &tdmout_c_sclk_pre_en, - &tdmin_a_sclk_post_en, - &tdmin_b_sclk_post_en, - &tdmin_c_sclk_post_en, - &tdmin_lb_sclk_post_en, - &tdmout_a_sclk_post_en, - &tdmout_b_sclk_post_en, - &tdmout_c_sclk_post_en, - &tdmin_a_sclk, - &tdmin_b_sclk, - &tdmin_c_sclk, - &tdmin_lb_sclk, - &g12a_tdmout_a_sclk, - &g12a_tdmout_b_sclk, - &g12a_tdmout_c_sclk, - &tdmin_a_lrclk, - &tdmin_b_lrclk, - &tdmin_c_lrclk, - &tdmin_lb_lrclk, - &tdmout_a_lrclk, - &tdmout_b_lrclk, - &tdmout_c_lrclk, - &spdifout_b_clk_sel, - &spdifout_b_clk_div, - &spdifout_b_clk, - &sm1_tdm_mclk_pad_0, - &sm1_tdm_mclk_pad_1, - &sm1_tdm_lrclk_pad_0, - &sm1_tdm_lrclk_pad_1, - &sm1_tdm_lrclk_pad_2, - &sm1_tdm_sclk_pad_0, - &sm1_tdm_sclk_pad_1, - &sm1_tdm_sclk_pad_2, - &sm1_aud_top, - &toram, - &eqdrc, - &resample_b, - &tovad, - &locker, - &spdifin_lb, - &frddr_d, - &toddr_d, - &loopback_b, - &sm1_clk81_en, - &sm1_sysclk_a_div, - &sm1_sysclk_a_en, - &sm1_sysclk_b_div, - &sm1_sysclk_b_en, - &earcrx, - &sm1_earcrx_cmdc_clk_sel, - &sm1_earcrx_cmdc_clk_div, - &sm1_earcrx_cmdc_clk, - &sm1_earcrx_dmac_clk_sel, - &sm1_earcrx_dmac_clk_div, - &sm1_earcrx_dmac_clk, -}; - static struct regmap_config axg_audio_regmap_cfg = { .reg_bits = 32, .val_bits = 32, @@ -1739,8 +1318,6 @@ static struct regmap_config axg_audio_regmap_cfg = { }; struct audioclk_data { - struct clk_regmap *const *regmap_clks; - unsigned int regmap_clk_num; struct meson_clk_hw_data hw_clks; const char *rst_drvname; unsigned int max_register; @@ -1783,10 +1360,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) return ret; } - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < data->regmap_clk_num; i++) - data->regmap_clks[i]->map = map; - /* Take care to skip the registered input clocks */ for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) { const char *name; @@ -1821,8 +1394,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) } static const struct audioclk_data axg_audioclk_data = { - .regmap_clks = axg_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), .hw_clks = { .hws = axg_audio_hw_clks, .num = ARRAY_SIZE(axg_audio_hw_clks), @@ -1831,8 +1402,6 @@ static const struct audioclk_data axg_audioclk_data = { }; static const struct audioclk_data g12a_audioclk_data = { - .regmap_clks = g12a_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), .hw_clks = { .hws = g12a_audio_hw_clks, .num = ARRAY_SIZE(g12a_audio_hw_clks), @@ -1842,8 +1411,6 @@ static const struct audioclk_data g12a_audioclk_data = { }; static const struct audioclk_data sm1_audioclk_data = { - .regmap_clks = sm1_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps), .hw_clks = { .hws = sm1_audio_hw_clks, .num = ARRAY_SIZE(sm1_audio_hw_clks), diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 766764b50b36..564655d4d188 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -2110,138 +2110,7 @@ static struct clk_hw *axg_hw_clks[] = { [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw, }; -/* Convenience table to populate regmap in .probe */ -static struct clk_regmap *const axg_clk_regmaps[] = { - &axg_clk81, - &axg_ddr, - &axg_audio_locker, - &axg_mipi_dsi_host, - &axg_isa, - &axg_pl301, - &axg_periphs, - &axg_spicc_0, - &axg_i2c, - &axg_rng0, - &axg_uart0, - &axg_mipi_dsi_phy, - &axg_spicc_1, - &axg_pcie_a, - &axg_pcie_b, - &axg_hiu_reg, - &axg_assist_misc, - &axg_emmc_b, - &axg_emmc_c, - &axg_dma, - &axg_spi, - &axg_audio, - &axg_eth_core, - &axg_uart1, - &axg_g2d, - &axg_usb0, - &axg_usb1, - &axg_reset, - &axg_usb_general, - &axg_ahb_arb0, - &axg_efuse, - &axg_boot_rom, - &axg_ahb_data_bus, - &axg_ahb_ctrl_bus, - &axg_usb1_to_ddr, - &axg_usb0_to_ddr, - &axg_mmc_pclk, - &axg_vpu_intr, - &axg_sec_ahb_ahb3_bridge, - &axg_gic, - &axg_ao_media_cpu, - &axg_ao_ahb_sram, - &axg_ao_ahb_bus, - &axg_ao_iface, - &axg_ao_i2c, - &axg_sd_emmc_b_clk0, - &axg_sd_emmc_c_clk0, - &axg_mpeg_clk_div, - &axg_sd_emmc_b_clk0_div, - &axg_sd_emmc_c_clk0_div, - &axg_mpeg_clk_sel, - &axg_sd_emmc_b_clk0_sel, - &axg_sd_emmc_c_clk0_sel, - &axg_mpll0, - &axg_mpll1, - &axg_mpll2, - &axg_mpll3, - &axg_mpll0_div, - &axg_mpll1_div, - &axg_mpll2_div, - &axg_mpll3_div, - &axg_fixed_pll, - &axg_sys_pll, - &axg_gp0_pll, - &axg_hifi_pll, - &axg_mpll_prediv, - &axg_fclk_div2, - &axg_fclk_div3, - &axg_fclk_div4, - &axg_fclk_div5, - &axg_fclk_div7, - &axg_pcie_pll_dco, - &axg_pcie_pll_od, - &axg_pcie_pll, - &axg_pcie_mux, - &axg_pcie_ref, - &axg_pcie_cml_en0, - &axg_pcie_cml_en1, - &axg_gen_clk_sel, - &axg_gen_clk_div, - &axg_gen_clk, - &axg_fixed_pll_dco, - &axg_sys_pll_dco, - &axg_gp0_pll_dco, - &axg_hifi_pll_dco, - &axg_pcie_pll_dco, - &axg_pcie_pll_od, - &axg_vpu_0_div, - &axg_vpu_0_sel, - &axg_vpu_0, - &axg_vpu_1_div, - &axg_vpu_1_sel, - &axg_vpu_1, - &axg_vpu, - &axg_vapb_0_div, - &axg_vapb_0_sel, - &axg_vapb_0, - &axg_vapb_1_div, - &axg_vapb_1_sel, - &axg_vapb_1, - &axg_vapb_sel, - &axg_vapb, - &axg_vclk, - &axg_vclk2, - &axg_vclk_sel, - &axg_vclk2_sel, - &axg_vclk_input, - &axg_vclk2_input, - &axg_vclk_div, - &axg_vclk_div1, - &axg_vclk2_div, - &axg_vclk2_div1, - &axg_vclk_div2_en, - &axg_vclk_div4_en, - &axg_vclk_div6_en, - &axg_vclk_div12_en, - &axg_vclk2_div2_en, - &axg_vclk2_div4_en, - &axg_vclk2_div6_en, - &axg_vclk2_div12_en, - &axg_cts_encl_sel, - &axg_cts_encl, - &axg_vdin_meas_sel, - &axg_vdin_meas_div, - &axg_vdin_meas, -}; - static const struct meson_eeclkc_data axg_clkc_data = { - .regmap_clks = axg_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), .hw_clks = { .hws = axg_hw_clks, .num = ARRAY_SIZE(axg_hw_clks), diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peripherals.c index 2075668ed306..a25e7d5dc669 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -2092,210 +2092,6 @@ static struct clk_hw *c3_periphs_hw_clks[] = { [CLKID_VAPB] = &vapb.hw, }; -/* Convenience table to populate regmap in .probe */ -static struct clk_regmap *const c3_periphs_clk_regmaps[] = { - &rtc_xtal_clkin, - &rtc_32k_div, - &rtc_32k_mux, - &rtc_32k, - &rtc_clk, - &sys_reset_ctrl, - &sys_pwr_ctrl, - &sys_pad_ctrl, - &sys_ctrl, - &sys_ts_pll, - &sys_dev_arb, - &sys_mmc_pclk, - &sys_cpu_ctrl, - &sys_jtag_ctrl, - &sys_ir_ctrl, - &sys_irq_ctrl, - &sys_msr_clk, - &sys_rom, - &sys_uart_f, - &sys_cpu_apb, - &sys_rsa, - &sys_sar_adc, - &sys_startup, - &sys_secure, - &sys_spifc, - &sys_nna, - &sys_eth_mac, - &sys_gic, - &sys_rama, - &sys_big_nic, - &sys_ramb, - &sys_audio_pclk, - &sys_pwm_kl, - &sys_pwm_ij, - &sys_usb, - &sys_sd_emmc_a, - &sys_sd_emmc_c, - &sys_pwm_ab, - &sys_pwm_cd, - &sys_pwm_ef, - &sys_pwm_gh, - &sys_spicc_1, - &sys_spicc_0, - &sys_uart_a, - &sys_uart_b, - &sys_uart_c, - &sys_uart_d, - &sys_uart_e, - &sys_i2c_m_a, - &sys_i2c_m_b, - &sys_i2c_m_c, - &sys_i2c_m_d, - &sys_i2c_s_a, - &sys_rtc, - &sys_ge2d, - &sys_isp, - &sys_gpv_isp_nic, - &sys_gpv_cve_nic, - &sys_mipi_dsi_host, - &sys_mipi_dsi_phy, - &sys_eth_phy, - &sys_acodec, - &sys_dwap, - &sys_dos, - &sys_cve, - &sys_vout, - &sys_vc9000e, - &sys_pwm_mn, - &sys_sd_emmc_b, - &axi_sys_nic, - &axi_isp_nic, - &axi_cve_nic, - &axi_ramb, - &axi_rama, - &axi_cpu_dmc, - &axi_nic, - &axi_dma, - &axi_mux_nic, - &axi_cve, - &axi_dev1_dmc, - &axi_dev0_dmc, - &axi_dsp_dmc, - &clk_12_24m_in, - &clk_12_24m, - &fclk_25m_div, - &fclk_25m, - &gen_sel, - &gen_div, - &gen, - &saradc_sel, - &saradc_div, - &saradc, - &pwm_a_sel, - &pwm_a_div, - &pwm_a, - &pwm_b_sel, - &pwm_b_div, - &pwm_b, - &pwm_c_sel, - &pwm_c_div, - &pwm_c, - &pwm_d_sel, - &pwm_d_div, - &pwm_d, - &pwm_e_sel, - &pwm_e_div, - &pwm_e, - &pwm_f_sel, - &pwm_f_div, - &pwm_f, - &pwm_g_sel, - &pwm_g_div, - &pwm_g, - &pwm_h_sel, - &pwm_h_div, - &pwm_h, - &pwm_i_sel, - &pwm_i_div, - &pwm_i, - &pwm_j_sel, - &pwm_j_div, - &pwm_j, - &pwm_k_sel, - &pwm_k_div, - &pwm_k, - &pwm_l_sel, - &pwm_l_div, - &pwm_l, - &pwm_m_sel, - &pwm_m_div, - &pwm_m, - &pwm_n_sel, - &pwm_n_div, - &pwm_n, - &spicc_a_sel, - &spicc_a_div, - &spicc_a, - &spicc_b_sel, - &spicc_b_div, - &spicc_b, - &spifc_sel, - &spifc_div, - &spifc, - &sd_emmc_a_sel, - &sd_emmc_a_div, - &sd_emmc_a, - &sd_emmc_b_sel, - &sd_emmc_b_div, - &sd_emmc_b, - &sd_emmc_c_sel, - &sd_emmc_c_div, - &sd_emmc_c, - &ts_div, - &ts, - ð_125m, - ð_rmii_div, - ð_rmii, - &mipi_dsi_meas_sel, - &mipi_dsi_meas_div, - &mipi_dsi_meas, - &dsi_phy_sel, - &dsi_phy_div, - &dsi_phy, - &vout_mclk_sel, - &vout_mclk_div, - &vout_mclk, - &vout_enc_sel, - &vout_enc_div, - &vout_enc, - &hcodec_0_sel, - &hcodec_0_div, - &hcodec_0, - &hcodec_1_sel, - &hcodec_1_div, - &hcodec_1, - &hcodec, - &vc9000e_aclk_sel, - &vc9000e_aclk_div, - &vc9000e_aclk, - &vc9000e_core_sel, - &vc9000e_core_div, - &vc9000e_core, - &csi_phy0_sel, - &csi_phy0_div, - &csi_phy0, - &dewarpa_sel, - &dewarpa_div, - &dewarpa, - &isp0_sel, - &isp0_div, - &isp0, - &nna_core_sel, - &nna_core_div, - &nna_core, - &ge2d_sel, - &ge2d_div, - &ge2d, - &vapb_sel, - &vapb_div, - &vapb, -}; - static const struct regmap_config clkc_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -2313,7 +2109,7 @@ static int c3_peripherals_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct regmap *regmap; void __iomem *base; - int clkid, ret, i; + int clkid, ret; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -2323,10 +2119,6 @@ static int c3_peripherals_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(c3_periphs_clk_regmaps); i++) - c3_periphs_clk_regmaps[i]->map = regmap; - for (clkid = 0; clkid < c3_periphs_clks.num; clkid++) { /* array might be sparse */ if (!c3_periphs_clks.hws[clkid]) diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c index ed4bc495862e..2c5594b8e49a 100644 --- a/drivers/clk/meson/c3-pll.c +++ b/drivers/clk/meson/c3-pll.c @@ -653,32 +653,6 @@ static struct clk_hw *c3_pll_hw_clks[] = { [CLKID_MCLK1] = &mclk1.hw }; -/* Convenience table to populate regmap in .probe */ -static struct clk_regmap *const c3_pll_clk_regmaps[] = { - &fclk_50m_en, - &fclk_div2, - &fclk_div2p5, - &fclk_div3, - &fclk_div4, - &fclk_div5, - &fclk_div7, - &gp0_pll_dco, - &gp0_pll, - &hifi_pll_dco, - &hifi_pll, - &mclk_pll_dco, - &mclk_pll_od, - &mclk_pll, - &mclk0_sel, - &mclk0_div_en, - &mclk0_div, - &mclk0, - &mclk1_sel, - &mclk1_div_en, - &mclk1_div, - &mclk1, -}; - static const struct regmap_config clkc_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -696,7 +670,7 @@ static int c3_pll_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct regmap *regmap; void __iomem *base; - int clkid, ret, i; + int clkid, ret; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -706,10 +680,6 @@ static int c3_pll_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(c3_pll_clk_regmaps); i++) - c3_pll_clk_regmaps[i]->map = regmap; - for (clkid = 0; clkid < c3_pll_clks.num; clkid++) { /* array might be sparse */ if (!c3_pll_clks.hws[clkid]) diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 71c758ffa493..4095a1b2bb80 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -381,38 +381,6 @@ static const unsigned int g12a_aoclk_reset[] = { [RESET_AO_IR_OUT] = 23, }; -static struct clk_regmap *g12a_aoclk_regmap[] = { - &g12a_aoclk_ahb, - &g12a_aoclk_ir_in, - &g12a_aoclk_i2c_m0, - &g12a_aoclk_i2c_s0, - &g12a_aoclk_uart, - &g12a_aoclk_prod_i2c, - &g12a_aoclk_uart2, - &g12a_aoclk_ir_out, - &g12a_aoclk_saradc, - &g12a_aoclk_mailbox, - &g12a_aoclk_m3, - &g12a_aoclk_ahb_sram, - &g12a_aoclk_rti, - &g12a_aoclk_m4_fclk, - &g12a_aoclk_m4_hclk, - &g12a_aoclk_cts_oscin, - &g12a_aoclk_32k_by_oscin_pre, - &g12a_aoclk_32k_by_oscin_div, - &g12a_aoclk_32k_by_oscin_sel, - &g12a_aoclk_32k_by_oscin, - &g12a_aoclk_cec_pre, - &g12a_aoclk_cec_div, - &g12a_aoclk_cec_sel, - &g12a_aoclk_cec, - &g12a_aoclk_cts_rtc_oscin, - &g12a_aoclk_clk81, - &g12a_aoclk_saradc_mux, - &g12a_aoclk_saradc_div, - &g12a_aoclk_saradc_gate, -}; - static struct clk_hw *g12a_aoclk_hw_clks[] = { [CLKID_AO_AHB] = &g12a_aoclk_ahb.hw, [CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw, @@ -449,8 +417,6 @@ static const struct meson_aoclk_data g12a_aoclkc_data = { .reset_reg = AO_RTI_GEN_CNTL_REG0, .num_reset = ARRAY_SIZE(g12a_aoclk_reset), .reset = g12a_aoclk_reset, - .num_clks = ARRAY_SIZE(g12a_aoclk_regmap), - .clks = g12a_aoclk_regmap, .hw_clks = { .hws = g12a_aoclk_hw_clks, .num = ARRAY_SIZE(g12a_aoclk_hw_clks), diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index e59bae56a4a5..1b30f1bcca55 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -5235,261 +5235,6 @@ static struct clk_hw *sm1_hw_clks[] = { [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, }; -/* Convenience table to populate regmap in .probe */ -static struct clk_regmap *const g12a_clk_regmaps[] = { - &g12a_clk81, - &g12a_dos, - &g12a_ddr, - &g12a_audio_locker, - &g12a_mipi_dsi_host, - &g12a_eth_phy, - &g12a_isa, - &g12a_pl301, - &g12a_periphs, - &g12a_spicc_0, - &g12a_i2c, - &g12a_sana, - &g12a_sd, - &g12a_rng0, - &g12a_uart0, - &g12a_spicc_1, - &g12a_hiu_reg, - &g12a_mipi_dsi_phy, - &g12a_assist_misc, - &g12a_emmc_a, - &g12a_emmc_b, - &g12a_emmc_c, - &g12a_audio_codec, - &g12a_audio, - &g12a_eth_core, - &g12a_demux, - &g12a_audio_ififo, - &g12a_adc, - &g12a_uart1, - &g12a_g2d, - &g12a_reset, - &g12a_pcie_comb, - &g12a_parser, - &g12a_usb_general, - &g12a_pcie_phy, - &g12a_ahb_arb0, - &g12a_ahb_data_bus, - &g12a_ahb_ctrl_bus, - &g12a_htx_hdcp22, - &g12a_htx_pclk, - &g12a_bt656, - &g12a_usb1_to_ddr, - &g12a_mmc_pclk, - &g12a_uart2, - &g12a_vpu_intr, - &g12a_gic, - &g12a_sd_emmc_a_clk0, - &g12a_sd_emmc_b_clk0, - &g12a_sd_emmc_c_clk0, - &g12a_mpeg_clk_div, - &g12a_sd_emmc_a_clk0_div, - &g12a_sd_emmc_b_clk0_div, - &g12a_sd_emmc_c_clk0_div, - &g12a_mpeg_clk_sel, - &g12a_sd_emmc_a_clk0_sel, - &g12a_sd_emmc_b_clk0_sel, - &g12a_sd_emmc_c_clk0_sel, - &g12a_mpll0, - &g12a_mpll1, - &g12a_mpll2, - &g12a_mpll3, - &g12a_mpll0_div, - &g12a_mpll1_div, - &g12a_mpll2_div, - &g12a_mpll3_div, - &g12a_fixed_pll, - &g12a_sys_pll, - &g12a_gp0_pll, - &g12a_hifi_pll, - &g12a_vclk2_venci0, - &g12a_vclk2_venci1, - &g12a_vclk2_vencp0, - &g12a_vclk2_vencp1, - &g12a_vclk2_venct0, - &g12a_vclk2_venct1, - &g12a_vclk2_other, - &g12a_vclk2_enci, - &g12a_vclk2_encp, - &g12a_dac_clk, - &g12a_aoclk_gate, - &g12a_iec958_gate, - &g12a_enc480p, - &g12a_rng1, - &g12a_vclk2_enct, - &g12a_vclk2_encl, - &g12a_vclk2_venclmmc, - &g12a_vclk2_vencl, - &g12a_vclk2_other1, - &g12a_fixed_pll_dco, - &g12a_sys_pll_dco, - &g12a_gp0_pll_dco, - &g12a_hifi_pll_dco, - &g12a_fclk_div2, - &g12a_fclk_div3, - &g12a_fclk_div4, - &g12a_fclk_div5, - &g12a_fclk_div7, - &g12a_fclk_div2p5, - &g12a_dma, - &g12a_efuse, - &g12a_rom_boot, - &g12a_reset_sec, - &g12a_sec_ahb_apb3, - &g12a_vpu_0_sel, - &g12a_vpu_0_div, - &g12a_vpu_0, - &g12a_vpu_1_sel, - &g12a_vpu_1_div, - &g12a_vpu_1, - &g12a_vpu, - &g12a_vapb_0_sel, - &g12a_vapb_0_div, - &g12a_vapb_0, - &g12a_vapb_1_sel, - &g12a_vapb_1_div, - &g12a_vapb_1, - &g12a_vapb_sel, - &g12a_vapb, - &g12a_hdmi_pll_dco, - &g12a_hdmi_pll_od, - &g12a_hdmi_pll_od2, - &g12a_hdmi_pll, - &g12a_vid_pll_div, - &g12a_vid_pll_sel, - &g12a_vid_pll, - &g12a_vclk_sel, - &g12a_vclk2_sel, - &g12a_vclk_input, - &g12a_vclk2_input, - &g12a_vclk_div, - &g12a_vclk2_div, - &g12a_vclk, - &g12a_vclk2, - &g12a_vclk_div1, - &g12a_vclk_div2_en, - &g12a_vclk_div4_en, - &g12a_vclk_div6_en, - &g12a_vclk_div12_en, - &g12a_vclk2_div1, - &g12a_vclk2_div2_en, - &g12a_vclk2_div4_en, - &g12a_vclk2_div6_en, - &g12a_vclk2_div12_en, - &g12a_cts_enci_sel, - &g12a_cts_encp_sel, - &g12a_cts_encl_sel, - &g12a_cts_vdac_sel, - &g12a_hdmi_tx_sel, - &g12a_cts_enci, - &g12a_cts_encp, - &g12a_cts_encl, - &g12a_cts_vdac, - &g12a_hdmi_tx, - &g12a_hdmi_sel, - &g12a_hdmi_div, - &g12a_hdmi, - &g12a_mali_0_sel, - &g12a_mali_0_div, - &g12a_mali_0, - &g12a_mali_1_sel, - &g12a_mali_1_div, - &g12a_mali_1, - &g12a_mali, - &g12a_mpll_50m, - &g12a_sys_pll_div16_en, - &g12a_cpu_clk_premux0, - &g12a_cpu_clk_mux0_div, - &g12a_cpu_clk_postmux0, - &g12a_cpu_clk_premux1, - &g12a_cpu_clk_mux1_div, - &g12a_cpu_clk_postmux1, - &g12a_cpu_clk_dyn, - &g12a_cpu_clk, - &g12a_cpu_clk_div16_en, - &g12a_cpu_clk_apb_div, - &g12a_cpu_clk_apb, - &g12a_cpu_clk_atb_div, - &g12a_cpu_clk_atb, - &g12a_cpu_clk_axi_div, - &g12a_cpu_clk_axi, - &g12a_cpu_clk_trace_div, - &g12a_cpu_clk_trace, - &g12a_pcie_pll_od, - &g12a_pcie_pll_dco, - &g12a_vdec_1_sel, - &g12a_vdec_1_div, - &g12a_vdec_1, - &g12a_vdec_hevc_sel, - &g12a_vdec_hevc_div, - &g12a_vdec_hevc, - &g12a_vdec_hevcf_sel, - &g12a_vdec_hevcf_div, - &g12a_vdec_hevcf, - &g12a_ts_div, - &g12a_ts, - &g12b_cpu_clk, - &g12b_sys1_pll_dco, - &g12b_sys1_pll, - &g12b_sys1_pll_div16_en, - &g12b_cpub_clk_premux0, - &g12b_cpub_clk_mux0_div, - &g12b_cpub_clk_postmux0, - &g12b_cpub_clk_premux1, - &g12b_cpub_clk_mux1_div, - &g12b_cpub_clk_postmux1, - &g12b_cpub_clk_dyn, - &g12b_cpub_clk, - &g12b_cpub_clk_div16_en, - &g12b_cpub_clk_apb_sel, - &g12b_cpub_clk_apb, - &g12b_cpub_clk_atb_sel, - &g12b_cpub_clk_atb, - &g12b_cpub_clk_axi_sel, - &g12b_cpub_clk_axi, - &g12b_cpub_clk_trace_sel, - &g12b_cpub_clk_trace, - &sm1_gp1_pll_dco, - &sm1_gp1_pll, - &sm1_dsu_clk_premux0, - &sm1_dsu_clk_premux1, - &sm1_dsu_clk_mux0_div, - &sm1_dsu_clk_postmux0, - &sm1_dsu_clk_mux1_div, - &sm1_dsu_clk_postmux1, - &sm1_dsu_clk_dyn, - &sm1_dsu_final_clk, - &sm1_dsu_clk, - &sm1_cpu1_clk, - &sm1_cpu2_clk, - &sm1_cpu3_clk, - &g12a_spicc0_sclk_sel, - &g12a_spicc0_sclk_div, - &g12a_spicc0_sclk, - &g12a_spicc1_sclk_sel, - &g12a_spicc1_sclk_div, - &g12a_spicc1_sclk, - &sm1_nna_axi_clk_sel, - &sm1_nna_axi_clk_div, - &sm1_nna_axi_clk, - &sm1_nna_core_clk_sel, - &sm1_nna_core_clk_div, - &sm1_nna_core_clk, - &g12a_mipi_dsi_pxclk_sel, - &g12a_mipi_dsi_pxclk_div, - &g12a_mipi_dsi_pxclk, - &g12b_mipi_isp_sel, - &g12b_mipi_isp_div, - &g12b_mipi_isp, - &g12b_mipi_isp_gate, - &g12b_csi_phy1, - &g12b_csi_phy0, -}; - static const struct reg_sequence g12a_init_regs[] = { { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 }, }; @@ -5668,8 +5413,6 @@ static int meson_g12a_probe(struct platform_device *pdev) static const struct meson_g12a_data g12a_clkc_data = { .eeclkc_data = { - .regmap_clks = g12a_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), .hw_clks = { .hws = g12a_hw_clks, .num = ARRAY_SIZE(g12a_hw_clks), @@ -5682,8 +5425,6 @@ static const struct meson_g12a_data g12a_clkc_data = { static const struct meson_g12a_data g12b_clkc_data = { .eeclkc_data = { - .regmap_clks = g12a_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), .hw_clks = { .hws = g12b_hw_clks, .num = ARRAY_SIZE(g12b_hw_clks), @@ -5694,8 +5435,6 @@ static const struct meson_g12a_data g12b_clkc_data = { static const struct meson_g12a_data sm1_clkc_data = { .eeclkc_data = { - .regmap_clks = g12a_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), .hw_clks = { .hws = sm1_hw_clks, .num = ARRAY_SIZE(sm1_hw_clks), diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 43940232f718..f075fbd450f3 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -237,23 +237,6 @@ static const unsigned int gxbb_aoclk_reset[] = { [RESET_AO_IR_BLASTER] = 23, }; -static struct clk_regmap *gxbb_aoclk[] = { - &remote_ao, - &i2c_master_ao, - &i2c_slave_ao, - &uart1_ao, - &uart2_ao, - &ir_blaster_ao, - &ao_cts_oscin, - &ao_32k_pre, - &ao_32k_div, - &ao_32k_sel, - &ao_32k, - &ao_cts_rtc_oscin, - &ao_clk81, - &ao_cts_cec, -}; - static struct clk_hw *gxbb_aoclk_hw_clks[] = { [CLKID_AO_REMOTE] = &remote_ao.hw, [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw, @@ -275,8 +258,6 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = { .reset_reg = AO_RTI_GEN_CNTL_REG0, .num_reset = ARRAY_SIZE(gxbb_aoclk_reset), .reset = gxbb_aoclk_reset, - .num_clks = ARRAY_SIZE(gxbb_aoclk), - .clks = gxbb_aoclk, .hw_clks = { .hws = gxbb_aoclk_hw_clks, .num = ARRAY_SIZE(gxbb_aoclk_hw_clks), diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 9aed0ea657ab..3b8731ec2016 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -3237,398 +3237,7 @@ static struct clk_hw *gxl_hw_clks[] = { [CLKID_ACODEC] = &gxl_acodec.hw, }; -static struct clk_regmap *const gxbb_clk_regmaps[] = { - &gxbb_clk81, - &gxbb_ddr, - &gxbb_dos, - &gxbb_isa, - &gxbb_pl301, - &gxbb_periphs, - &gxbb_spicc, - &gxbb_i2c, - &gxbb_sar_adc, - &gxbb_smart_card, - &gxbb_rng0, - &gxbb_uart0, - &gxbb_sdhc, - &gxbb_stream, - &gxbb_async_fifo, - &gxbb_sdio, - &gxbb_abuf, - &gxbb_hiu_iface, - &gxbb_assist_misc, - &gxbb_spi, - &gxbb_i2s_spdif, - &gxbb_eth, - &gxbb_demux, - &gxbb_aiu_glue, - &gxbb_iec958, - &gxbb_i2s_out, - &gxbb_amclk, - &gxbb_aififo2, - &gxbb_mixer, - &gxbb_mixer_iface, - &gxbb_adc, - &gxbb_blkmv, - &gxbb_aiu, - &gxbb_uart1, - &gxbb_g2d, - &gxbb_usb0, - &gxbb_usb1, - &gxbb_reset, - &gxbb_nand, - &gxbb_dos_parser, - &gxbb_usb, - &gxbb_vdin1, - &gxbb_ahb_arb0, - &gxbb_efuse, - &gxbb_boot_rom, - &gxbb_ahb_data_bus, - &gxbb_ahb_ctrl_bus, - &gxbb_hdmi_intr_sync, - &gxbb_hdmi_pclk, - &gxbb_usb1_ddr_bridge, - &gxbb_usb0_ddr_bridge, - &gxbb_mmc_pclk, - &gxbb_dvin, - &gxbb_uart2, - &gxbb_sana, - &gxbb_vpu_intr, - &gxbb_sec_ahb_ahb3_bridge, - &gxbb_clk81_a53, - &gxbb_vclk2_venci0, - &gxbb_vclk2_venci1, - &gxbb_vclk2_vencp0, - &gxbb_vclk2_vencp1, - &gxbb_gclk_venci_int0, - &gxbb_gclk_vencp_int, - &gxbb_dac_clk, - &gxbb_aoclk_gate, - &gxbb_iec958_gate, - &gxbb_enc480p, - &gxbb_rng1, - &gxbb_gclk_venci_int1, - &gxbb_vclk2_venclmcc, - &gxbb_vclk2_vencl, - &gxbb_vclk_other, - &gxbb_edp, - &gxbb_ao_media_cpu, - &gxbb_ao_ahb_sram, - &gxbb_ao_ahb_bus, - &gxbb_ao_iface, - &gxbb_ao_i2c, - &gxbb_emmc_a, - &gxbb_emmc_b, - &gxbb_emmc_c, - &gxbb_sar_adc_clk, - &gxbb_mali_0, - &gxbb_mali_1, - &gxbb_cts_amclk, - &gxbb_cts_mclk_i958, - &gxbb_32k_clk, - &gxbb_sd_emmc_a_clk0, - &gxbb_sd_emmc_b_clk0, - &gxbb_sd_emmc_c_clk0, - &gxbb_vpu_0, - &gxbb_vpu_1, - &gxbb_vapb_0, - &gxbb_vapb_1, - &gxbb_vapb, - &gxbb_mpeg_clk_div, - &gxbb_sar_adc_clk_div, - &gxbb_mali_0_div, - &gxbb_mali_1_div, - &gxbb_cts_mclk_i958_div, - &gxbb_32k_clk_div, - &gxbb_sd_emmc_a_clk0_div, - &gxbb_sd_emmc_b_clk0_div, - &gxbb_sd_emmc_c_clk0_div, - &gxbb_vpu_0_div, - &gxbb_vpu_1_div, - &gxbb_vapb_0_div, - &gxbb_vapb_1_div, - &gxbb_mpeg_clk_sel, - &gxbb_sar_adc_clk_sel, - &gxbb_mali_0_sel, - &gxbb_mali_1_sel, - &gxbb_mali, - &gxbb_cts_amclk_sel, - &gxbb_cts_mclk_i958_sel, - &gxbb_cts_i958, - &gxbb_32k_clk_sel, - &gxbb_sd_emmc_a_clk0_sel, - &gxbb_sd_emmc_b_clk0_sel, - &gxbb_sd_emmc_c_clk0_sel, - &gxbb_vpu_0_sel, - &gxbb_vpu_1_sel, - &gxbb_vpu, - &gxbb_vapb_0_sel, - &gxbb_vapb_1_sel, - &gxbb_vapb_sel, - &gxbb_mpll0, - &gxbb_mpll1, - &gxbb_mpll2, - &gxbb_mpll0_div, - &gxbb_mpll1_div, - &gxbb_mpll2_div, - &gxbb_cts_amclk_div, - &gxbb_fixed_pll, - &gxbb_sys_pll, - &gxbb_mpll_prediv, - &gxbb_fclk_div2, - &gxbb_fclk_div3, - &gxbb_fclk_div4, - &gxbb_fclk_div5, - &gxbb_fclk_div7, - &gxbb_vdec_1_sel, - &gxbb_vdec_1_div, - &gxbb_vdec_1, - &gxbb_vdec_hevc_sel, - &gxbb_vdec_hevc_div, - &gxbb_vdec_hevc, - &gxbb_gen_clk_sel, - &gxbb_gen_clk_div, - &gxbb_gen_clk, - &gxbb_fixed_pll_dco, - &gxbb_sys_pll_dco, - &gxbb_gp0_pll, - &gxbb_vid_pll, - &gxbb_vid_pll_sel, - &gxbb_vid_pll_div, - &gxbb_vclk, - &gxbb_vclk_sel, - &gxbb_vclk_div, - &gxbb_vclk_input, - &gxbb_vclk_div1, - &gxbb_vclk_div2_en, - &gxbb_vclk_div4_en, - &gxbb_vclk_div6_en, - &gxbb_vclk_div12_en, - &gxbb_vclk2, - &gxbb_vclk2_sel, - &gxbb_vclk2_div, - &gxbb_vclk2_input, - &gxbb_vclk2_div1, - &gxbb_vclk2_div2_en, - &gxbb_vclk2_div4_en, - &gxbb_vclk2_div6_en, - &gxbb_vclk2_div12_en, - &gxbb_cts_enci, - &gxbb_cts_enci_sel, - &gxbb_cts_encp, - &gxbb_cts_encp_sel, - &gxbb_cts_vdac, - &gxbb_cts_vdac_sel, - &gxbb_hdmi_tx, - &gxbb_hdmi_tx_sel, - &gxbb_hdmi_sel, - &gxbb_hdmi_div, - &gxbb_hdmi, - &gxbb_gp0_pll_dco, - &gxbb_hdmi_pll, - &gxbb_hdmi_pll_od, - &gxbb_hdmi_pll_od2, - &gxbb_hdmi_pll_dco, -}; - -static struct clk_regmap *const gxl_clk_regmaps[] = { - &gxbb_clk81, - &gxbb_ddr, - &gxbb_dos, - &gxbb_isa, - &gxbb_pl301, - &gxbb_periphs, - &gxbb_spicc, - &gxbb_i2c, - &gxbb_sar_adc, - &gxbb_smart_card, - &gxbb_rng0, - &gxbb_uart0, - &gxbb_sdhc, - &gxbb_stream, - &gxbb_async_fifo, - &gxbb_sdio, - &gxbb_abuf, - &gxbb_hiu_iface, - &gxbb_assist_misc, - &gxbb_spi, - &gxbb_i2s_spdif, - &gxbb_eth, - &gxbb_demux, - &gxbb_aiu_glue, - &gxbb_iec958, - &gxbb_i2s_out, - &gxbb_amclk, - &gxbb_aififo2, - &gxbb_mixer, - &gxbb_mixer_iface, - &gxbb_adc, - &gxbb_blkmv, - &gxbb_aiu, - &gxbb_uart1, - &gxbb_g2d, - &gxbb_usb0, - &gxbb_usb1, - &gxbb_reset, - &gxbb_nand, - &gxbb_dos_parser, - &gxbb_usb, - &gxbb_vdin1, - &gxbb_ahb_arb0, - &gxbb_efuse, - &gxbb_boot_rom, - &gxbb_ahb_data_bus, - &gxbb_ahb_ctrl_bus, - &gxbb_hdmi_intr_sync, - &gxbb_hdmi_pclk, - &gxbb_usb1_ddr_bridge, - &gxbb_usb0_ddr_bridge, - &gxbb_mmc_pclk, - &gxbb_dvin, - &gxbb_uart2, - &gxbb_sana, - &gxbb_vpu_intr, - &gxbb_sec_ahb_ahb3_bridge, - &gxbb_clk81_a53, - &gxbb_vclk2_venci0, - &gxbb_vclk2_venci1, - &gxbb_vclk2_vencp0, - &gxbb_vclk2_vencp1, - &gxbb_gclk_venci_int0, - &gxbb_gclk_vencp_int, - &gxbb_dac_clk, - &gxbb_aoclk_gate, - &gxbb_iec958_gate, - &gxbb_enc480p, - &gxbb_rng1, - &gxbb_gclk_venci_int1, - &gxbb_vclk2_venclmcc, - &gxbb_vclk2_vencl, - &gxbb_vclk_other, - &gxbb_edp, - &gxbb_ao_media_cpu, - &gxbb_ao_ahb_sram, - &gxbb_ao_ahb_bus, - &gxbb_ao_iface, - &gxbb_ao_i2c, - &gxbb_emmc_a, - &gxbb_emmc_b, - &gxbb_emmc_c, - &gxbb_sar_adc_clk, - &gxbb_mali_0, - &gxbb_mali_1, - &gxbb_cts_amclk, - &gxbb_cts_mclk_i958, - &gxbb_32k_clk, - &gxbb_sd_emmc_a_clk0, - &gxbb_sd_emmc_b_clk0, - &gxbb_sd_emmc_c_clk0, - &gxbb_vpu_0, - &gxbb_vpu_1, - &gxbb_vapb_0, - &gxbb_vapb_1, - &gxbb_vapb, - &gxbb_mpeg_clk_div, - &gxbb_sar_adc_clk_div, - &gxbb_mali_0_div, - &gxbb_mali_1_div, - &gxbb_cts_mclk_i958_div, - &gxbb_32k_clk_div, - &gxbb_sd_emmc_a_clk0_div, - &gxbb_sd_emmc_b_clk0_div, - &gxbb_sd_emmc_c_clk0_div, - &gxbb_vpu_0_div, - &gxbb_vpu_1_div, - &gxbb_vapb_0_div, - &gxbb_vapb_1_div, - &gxbb_mpeg_clk_sel, - &gxbb_sar_adc_clk_sel, - &gxbb_mali_0_sel, - &gxbb_mali_1_sel, - &gxbb_mali, - &gxbb_cts_amclk_sel, - &gxbb_cts_mclk_i958_sel, - &gxbb_cts_i958, - &gxbb_32k_clk_sel, - &gxbb_sd_emmc_a_clk0_sel, - &gxbb_sd_emmc_b_clk0_sel, - &gxbb_sd_emmc_c_clk0_sel, - &gxbb_vpu_0_sel, - &gxbb_vpu_1_sel, - &gxbb_vpu, - &gxbb_vapb_0_sel, - &gxbb_vapb_1_sel, - &gxbb_vapb_sel, - &gxbb_mpll0, - &gxbb_mpll1, - &gxbb_mpll2, - &gxl_mpll0_div, - &gxbb_mpll1_div, - &gxbb_mpll2_div, - &gxbb_cts_amclk_div, - &gxbb_fixed_pll, - &gxbb_sys_pll, - &gxbb_mpll_prediv, - &gxbb_fclk_div2, - &gxbb_fclk_div3, - &gxbb_fclk_div4, - &gxbb_fclk_div5, - &gxbb_fclk_div7, - &gxbb_vdec_1_sel, - &gxbb_vdec_1_div, - &gxbb_vdec_1, - &gxbb_vdec_hevc_sel, - &gxbb_vdec_hevc_div, - &gxbb_vdec_hevc, - &gxbb_gen_clk_sel, - &gxbb_gen_clk_div, - &gxbb_gen_clk, - &gxbb_fixed_pll_dco, - &gxbb_sys_pll_dco, - &gxbb_gp0_pll, - &gxbb_vid_pll, - &gxbb_vid_pll_sel, - &gxbb_vid_pll_div, - &gxbb_vclk, - &gxbb_vclk_sel, - &gxbb_vclk_div, - &gxbb_vclk_input, - &gxbb_vclk_div1, - &gxbb_vclk_div2_en, - &gxbb_vclk_div4_en, - &gxbb_vclk_div6_en, - &gxbb_vclk_div12_en, - &gxbb_vclk2, - &gxbb_vclk2_sel, - &gxbb_vclk2_div, - &gxbb_vclk2_input, - &gxbb_vclk2_div1, - &gxbb_vclk2_div2_en, - &gxbb_vclk2_div4_en, - &gxbb_vclk2_div6_en, - &gxbb_vclk2_div12_en, - &gxbb_cts_enci, - &gxbb_cts_enci_sel, - &gxbb_cts_encp, - &gxbb_cts_encp_sel, - &gxbb_cts_vdac, - &gxbb_cts_vdac_sel, - &gxbb_hdmi_tx, - &gxbb_hdmi_tx_sel, - &gxbb_hdmi_sel, - &gxbb_hdmi_div, - &gxbb_hdmi, - &gxl_gp0_pll_dco, - &gxl_hdmi_pll, - &gxl_hdmi_pll_od, - &gxl_hdmi_pll_od2, - &gxl_hdmi_pll_dco, - &gxl_acodec, -}; - static const struct meson_eeclkc_data gxbb_clkc_data = { - .regmap_clks = gxbb_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps), .hw_clks = { .hws = gxbb_hw_clks, .num = ARRAY_SIZE(gxbb_hw_clks), @@ -3636,8 +3245,6 @@ static const struct meson_eeclkc_data gxbb_clkc_data = { }; static const struct meson_eeclkc_data gxl_clkc_data = { - .regmap_clks = gxl_clk_regmaps, - .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps), .hw_clks = { .hws = gxl_hw_clks, .num = ARRAY_SIZE(gxl_hw_clks), diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c index 995be51987f4..894c02fda072 100644 --- a/drivers/clk/meson/meson-aoclk.c +++ b/drivers/clk/meson/meson-aoclk.c @@ -18,6 +18,7 @@ #include #include "meson-aoclk.h" +#include "clk-regmap.h" static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev, unsigned long id) @@ -70,10 +71,6 @@ int meson_aoclkc_probe(struct platform_device *pdev) return ret; } - /* Populate regmap */ - for (clkid = 0; clkid < data->num_clks; clkid++) - data->clks[clkid]->map = regmap; - /* Register all clks */ for (clkid = 0; clkid < data->hw_clks.num; clkid++) { if (!data->hw_clks.hws[clkid]) diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h index 308be3e4814a..ea5fc61308af 100644 --- a/drivers/clk/meson/meson-aoclk.h +++ b/drivers/clk/meson/meson-aoclk.h @@ -23,8 +23,6 @@ struct meson_aoclk_data { const unsigned int reset_reg; const int num_reset; const unsigned int *reset; - const int num_clks; - struct clk_regmap **clks; struct meson_clk_hw_data hw_clks; }; diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c index 3053ee7425eb..6236bf970d79 100644 --- a/drivers/clk/meson/meson-eeclk.c +++ b/drivers/clk/meson/meson-eeclk.c @@ -39,10 +39,6 @@ int meson_eeclkc_probe(struct platform_device *pdev) if (data->init_count) regmap_multi_reg_write(map, data->init_regs, data->init_count); - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < data->regmap_clk_num; i++) - data->regmap_clks[i]->map = map; - for (i = 0; i < data->hw_clks.num; i++) { /* array might be sparse */ if (!data->hw_clks.hws[i]) diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eeclk.h index 37a48b75c660..6a81d67b46b2 100644 --- a/drivers/clk/meson/meson-eeclk.h +++ b/drivers/clk/meson/meson-eeclk.h @@ -14,8 +14,6 @@ struct platform_device; struct meson_eeclkc_data { - struct clk_regmap *const *regmap_clks; - unsigned int regmap_clk_num; const struct reg_sequence *init_regs; unsigned int init_count; struct meson_clk_hw_data hw_clks; diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c index 4b73ea244b63..1975fc3987e2 100644 --- a/drivers/clk/meson/meson8-ddr.c +++ b/drivers/clk/meson/meson8-ddr.c @@ -85,11 +85,6 @@ static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { .num = 2, }; -static struct clk_regmap *const meson8_ddr_clk_regmaps[] = { - &meson8_ddr_pll_dco, - &meson8_ddr_pll, -}; - static const struct regmap_config meson8_ddr_clkc_regmap_config = { .reg_bits = 8, .val_bits = 32, @@ -113,10 +108,6 @@ static int meson8_ddr_clkc_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* Populate regmap */ - for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++) - meson8_ddr_clk_regmaps[i]->map = regmap; - /* Register all clks */ for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { hw = meson8_ddr_clk_hw_onecell_data.hws[i]; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index cff07006016b..206538326614 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3472,202 +3472,6 @@ static struct clk_hw *meson8m2_hw_clks[] = { [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, }; -static struct clk_regmap *const meson8b_clk_regmaps[] = { - &meson8b_clk81, - &meson8b_ddr, - &meson8b_dos, - &meson8b_isa, - &meson8b_pl301, - &meson8b_periphs, - &meson8b_spicc, - &meson8b_i2c, - &meson8b_sar_adc, - &meson8b_smart_card, - &meson8b_rng0, - &meson8b_uart0, - &meson8b_sdhc, - &meson8b_stream, - &meson8b_async_fifo, - &meson8b_sdio, - &meson8b_abuf, - &meson8b_hiu_iface, - &meson8b_assist_misc, - &meson8b_spi, - &meson8b_i2s_spdif, - &meson8b_eth, - &meson8b_demux, - &meson8b_aiu_glue, - &meson8b_iec958, - &meson8b_i2s_out, - &meson8b_amclk, - &meson8b_aififo2, - &meson8b_mixer, - &meson8b_mixer_iface, - &meson8b_adc, - &meson8b_blkmv, - &meson8b_aiu, - &meson8b_uart1, - &meson8b_g2d, - &meson8b_usb0, - &meson8b_usb1, - &meson8b_reset, - &meson8b_nand, - &meson8b_dos_parser, - &meson8b_usb, - &meson8b_vdin1, - &meson8b_ahb_arb0, - &meson8b_efuse, - &meson8b_boot_rom, - &meson8b_ahb_data_bus, - &meson8b_ahb_ctrl_bus, - &meson8b_hdmi_intr_sync, - &meson8b_hdmi_pclk, - &meson8b_usb1_ddr_bridge, - &meson8b_usb0_ddr_bridge, - &meson8b_mmc_pclk, - &meson8b_dvin, - &meson8b_uart2, - &meson8b_sana, - &meson8b_vpu_intr, - &meson8b_sec_ahb_ahb3_bridge, - &meson8b_clk81_a9, - &meson8b_vclk2_venci0, - &meson8b_vclk2_venci1, - &meson8b_vclk2_vencp0, - &meson8b_vclk2_vencp1, - &meson8b_gclk_venci_int, - &meson8b_gclk_vencp_int, - &meson8b_dac_clk, - &meson8b_aoclk_gate, - &meson8b_iec958_gate, - &meson8b_enc480p, - &meson8b_rng1, - &meson8b_gclk_vencl_int, - &meson8b_vclk2_venclmcc, - &meson8b_vclk2_vencl, - &meson8b_vclk2_other, - &meson8b_edp, - &meson8b_ao_media_cpu, - &meson8b_ao_ahb_sram, - &meson8b_ao_ahb_bus, - &meson8b_ao_iface, - &meson8b_mpeg_clk_div, - &meson8b_mpeg_clk_sel, - &meson8b_mpll0, - &meson8b_mpll1, - &meson8b_mpll2, - &meson8b_mpll0_div, - &meson8b_mpll1_div, - &meson8b_mpll2_div, - &meson8b_fixed_pll, - &meson8b_sys_pll, - &meson8b_cpu_in_sel, - &meson8b_cpu_scale_div, - &meson8b_cpu_scale_out_sel, - &meson8b_cpu_clk, - &meson8b_mpll_prediv, - &meson8b_fclk_div2, - &meson8b_fclk_div3, - &meson8b_fclk_div4, - &meson8b_fclk_div5, - &meson8b_fclk_div7, - &meson8b_nand_clk_sel, - &meson8b_nand_clk_div, - &meson8b_nand_clk_gate, - &meson8b_fixed_pll_dco, - &meson8b_hdmi_pll_dco, - &meson8b_sys_pll_dco, - &meson8b_apb_clk_sel, - &meson8b_apb_clk_gate, - &meson8b_periph_clk_sel, - &meson8b_periph_clk_gate, - &meson8b_axi_clk_sel, - &meson8b_axi_clk_gate, - &meson8b_l2_dram_clk_sel, - &meson8b_l2_dram_clk_gate, - &meson8b_hdmi_pll_lvds_out, - &meson8b_hdmi_pll_hdmi_out, - &meson8b_vid_pll_in_sel, - &meson8b_vid_pll_in_en, - &meson8b_vid_pll_pre_div, - &meson8b_vid_pll_post_div, - &meson8b_vid_pll, - &meson8b_vid_pll_final_div, - &meson8b_vclk_in_sel, - &meson8b_vclk_in_en, - &meson8b_vclk_en, - &meson8b_vclk_div1_gate, - &meson8b_vclk_div2_div_gate, - &meson8b_vclk_div4_div_gate, - &meson8b_vclk_div6_div_gate, - &meson8b_vclk_div12_div_gate, - &meson8b_vclk2_in_sel, - &meson8b_vclk2_clk_in_en, - &meson8b_vclk2_clk_en, - &meson8b_vclk2_div1_gate, - &meson8b_vclk2_div2_div_gate, - &meson8b_vclk2_div4_div_gate, - &meson8b_vclk2_div6_div_gate, - &meson8b_vclk2_div12_div_gate, - &meson8b_cts_enct_sel, - &meson8b_cts_enct, - &meson8b_cts_encp_sel, - &meson8b_cts_encp, - &meson8b_cts_enci_sel, - &meson8b_cts_enci, - &meson8b_hdmi_tx_pixel_sel, - &meson8b_hdmi_tx_pixel, - &meson8b_cts_encl_sel, - &meson8b_cts_encl, - &meson8b_cts_vdac0_sel, - &meson8b_cts_vdac0, - &meson8b_hdmi_sys_sel, - &meson8b_hdmi_sys_div, - &meson8b_hdmi_sys, - &meson8b_mali_0_sel, - &meson8b_mali_0_div, - &meson8b_mali_0, - &meson8b_mali_1_sel, - &meson8b_mali_1_div, - &meson8b_mali_1, - &meson8b_mali, - &meson8m2_gp_pll_dco, - &meson8m2_gp_pll, - &meson8b_vpu_0_sel, - &meson8m2_vpu_0_sel, - &meson8b_vpu_0_div, - &meson8b_vpu_0, - &meson8b_vpu_1_sel, - &meson8m2_vpu_1_sel, - &meson8b_vpu_1_div, - &meson8b_vpu_1, - &meson8b_vpu, - &meson8b_vdec_1_sel, - &meson8b_vdec_1_1_div, - &meson8b_vdec_1_1, - &meson8b_vdec_1_2_div, - &meson8b_vdec_1_2, - &meson8b_vdec_1, - &meson8b_vdec_hcodec_sel, - &meson8b_vdec_hcodec_div, - &meson8b_vdec_hcodec, - &meson8b_vdec_2_sel, - &meson8b_vdec_2_div, - &meson8b_vdec_2, - &meson8b_vdec_hevc_sel, - &meson8b_vdec_hevc_div, - &meson8b_vdec_hevc_en, - &meson8b_vdec_hevc, - &meson8b_cts_amclk, - &meson8b_cts_amclk_sel, - &meson8b_cts_amclk_div, - &meson8b_cts_mclk_i958_sel, - &meson8b_cts_mclk_i958_div, - &meson8b_cts_mclk_i958, - &meson8b_cts_i958, - &meson8b_vid_pll_lvds_en, -}; - static const struct meson8b_clk_reset_line { u32 reg; u8 bit_idx; @@ -3884,10 +3688,6 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) - meson8b_clk_regmaps[i]->map = map; - /* * register all clks and start with the first used ID (which is * CLKID_PLL_FIXED) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c index 4c663dc33572..fd2d4d725f9e 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3567,231 +3567,6 @@ static struct clk_hw *s4_periphs_hw_clks[] = { [CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk_gate.hw, }; -/* Convenience table to populate regmap in .probe */ -static struct clk_regmap *const s4_periphs_clk_regmaps[] = { - &s4_rtc_32k_by_oscin_clkin, - &s4_rtc_32k_by_oscin_div, - &s4_rtc_32k_by_oscin_sel, - &s4_rtc_32k_by_oscin, - &s4_rtc_clk, - &s4_sysclk_b_sel, - &s4_sysclk_b_div, - &s4_sysclk_b, - &s4_sysclk_a_sel, - &s4_sysclk_a_div, - &s4_sysclk_a, - &s4_sys_clk, - &s4_ceca_32k_clkin, - &s4_ceca_32k_div, - &s4_ceca_32k_sel_pre, - &s4_ceca_32k_sel, - &s4_ceca_32k_clkout, - &s4_cecb_32k_clkin, - &s4_cecb_32k_div, - &s4_cecb_32k_sel_pre, - &s4_cecb_32k_sel, - &s4_cecb_32k_clkout, - &s4_sc_clk_mux, - &s4_sc_clk_div, - &s4_sc_clk_gate, - &s4_12_24M_clk_gate, - &s4_12_24M_clk, - &s4_vid_pll_div, - &s4_vid_pll_sel, - &s4_vid_pll, - &s4_vclk_sel, - &s4_vclk2_sel, - &s4_vclk_input, - &s4_vclk2_input, - &s4_vclk_div, - &s4_vclk2_div, - &s4_vclk, - &s4_vclk2, - &s4_vclk_div1, - &s4_vclk_div2_en, - &s4_vclk_div4_en, - &s4_vclk_div6_en, - &s4_vclk_div12_en, - &s4_vclk2_div1, - &s4_vclk2_div2_en, - &s4_vclk2_div4_en, - &s4_vclk2_div6_en, - &s4_vclk2_div12_en, - &s4_cts_enci_sel, - &s4_cts_encp_sel, - &s4_cts_vdac_sel, - &s4_hdmi_tx_sel, - &s4_cts_enci, - &s4_cts_encp, - &s4_cts_vdac, - &s4_hdmi_tx, - &s4_hdmi_sel, - &s4_hdmi_div, - &s4_hdmi, - &s4_ts_clk_div, - &s4_ts_clk_gate, - &s4_mali_0_sel, - &s4_mali_0_div, - &s4_mali_0, - &s4_mali_1_sel, - &s4_mali_1_div, - &s4_mali_1, - &s4_mali_mux, - &s4_vdec_p0_mux, - &s4_vdec_p0_div, - &s4_vdec_p0, - &s4_vdec_p1_mux, - &s4_vdec_p1_div, - &s4_vdec_p1, - &s4_vdec_mux, - &s4_hevcf_p0_mux, - &s4_hevcf_p0_div, - &s4_hevcf_p0, - &s4_hevcf_p1_mux, - &s4_hevcf_p1_div, - &s4_hevcf_p1, - &s4_hevcf_mux, - &s4_vpu_0_sel, - &s4_vpu_0_div, - &s4_vpu_0, - &s4_vpu_1_sel, - &s4_vpu_1_div, - &s4_vpu_1, - &s4_vpu, - &s4_vpu_clkb_tmp_mux, - &s4_vpu_clkb_tmp_div, - &s4_vpu_clkb_tmp, - &s4_vpu_clkb_div, - &s4_vpu_clkb, - &s4_vpu_clkc_p0_mux, - &s4_vpu_clkc_p0_div, - &s4_vpu_clkc_p0, - &s4_vpu_clkc_p1_mux, - &s4_vpu_clkc_p1_div, - &s4_vpu_clkc_p1, - &s4_vpu_clkc_mux, - &s4_vapb_0_sel, - &s4_vapb_0_div, - &s4_vapb_0, - &s4_vapb_1_sel, - &s4_vapb_1_div, - &s4_vapb_1, - &s4_vapb, - &s4_ge2d_gate, - &s4_hdcp22_esmclk_mux, - &s4_hdcp22_esmclk_div, - &s4_hdcp22_esmclk_gate, - &s4_hdcp22_skpclk_mux, - &s4_hdcp22_skpclk_div, - &s4_hdcp22_skpclk_gate, - &s4_vdin_meas_mux, - &s4_vdin_meas_div, - &s4_vdin_meas_gate, - &s4_sd_emmc_c_clk0_sel, - &s4_sd_emmc_c_clk0_div, - &s4_sd_emmc_c_clk0, - &s4_sd_emmc_a_clk0_sel, - &s4_sd_emmc_a_clk0_div, - &s4_sd_emmc_a_clk0, - &s4_sd_emmc_b_clk0_sel, - &s4_sd_emmc_b_clk0_div, - &s4_sd_emmc_b_clk0, - &s4_spicc0_mux, - &s4_spicc0_div, - &s4_spicc0_gate, - &s4_pwm_a_mux, - &s4_pwm_a_div, - &s4_pwm_a_gate, - &s4_pwm_b_mux, - &s4_pwm_b_div, - &s4_pwm_b_gate, - &s4_pwm_c_mux, - &s4_pwm_c_div, - &s4_pwm_c_gate, - &s4_pwm_d_mux, - &s4_pwm_d_div, - &s4_pwm_d_gate, - &s4_pwm_e_mux, - &s4_pwm_e_div, - &s4_pwm_e_gate, - &s4_pwm_f_mux, - &s4_pwm_f_div, - &s4_pwm_f_gate, - &s4_pwm_g_mux, - &s4_pwm_g_div, - &s4_pwm_g_gate, - &s4_pwm_h_mux, - &s4_pwm_h_div, - &s4_pwm_h_gate, - &s4_pwm_i_mux, - &s4_pwm_i_div, - &s4_pwm_i_gate, - &s4_pwm_j_mux, - &s4_pwm_j_div, - &s4_pwm_j_gate, - &s4_saradc_mux, - &s4_saradc_div, - &s4_saradc_gate, - &s4_gen_clk_sel, - &s4_gen_clk_div, - &s4_gen_clk, - &s4_ddr, - &s4_dos, - &s4_ethphy, - &s4_mali, - &s4_aocpu, - &s4_aucpu, - &s4_cec, - &s4_sdemmca, - &s4_sdemmcb, - &s4_nand, - &s4_smartcard, - &s4_acodec, - &s4_spifc, - &s4_msr_clk, - &s4_ir_ctrl, - &s4_audio, - &s4_eth, - &s4_uart_a, - &s4_uart_b, - &s4_uart_c, - &s4_uart_d, - &s4_uart_e, - &s4_aififo, - &s4_ts_ddr, - &s4_ts_pll, - &s4_g2d, - &s4_spicc0, - &s4_usb, - &s4_i2c_m_a, - &s4_i2c_m_b, - &s4_i2c_m_c, - &s4_i2c_m_d, - &s4_i2c_m_e, - &s4_hdmitx_apb, - &s4_i2c_s_a, - &s4_usb1_to_ddr, - &s4_hdcp22, - &s4_mmc_apb, - &s4_rsa, - &s4_cpu_debug, - &s4_vpu_intr, - &s4_demod, - &s4_sar_adc, - &s4_gic, - &s4_pwm_ab, - &s4_pwm_cd, - &s4_pwm_ef, - &s4_pwm_gh, - &s4_pwm_ij, - &s4_demod_core_clk_mux, - &s4_demod_core_clk_div, - &s4_demod_core_clk_gate, - &s4_adc_extclk_in_mux, - &s4_adc_extclk_in_div, - &s4_adc_extclk_in_gate, -}; - static const struct regmap_config clkc_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -3821,10 +3596,6 @@ static int meson_s4_periphs_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(regmap), "can't init regmap mmio region\n"); - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(s4_periphs_clk_regmaps); i++) - s4_periphs_clk_regmaps[i]->map = regmap; - for (i = 0; i < s4_periphs_clks.num; i++) { /* array might be sparse */ if (!s4_periphs_clks.hws[i]) diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index 911a590d206f..3d689d2f003e 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -794,33 +794,6 @@ static struct clk_hw *s4_pll_hw_clks[] = { [CLKID_MPLL3] = &s4_mpll3.hw, }; -static struct clk_regmap *const s4_pll_clk_regmaps[] = { - &s4_fixed_pll_dco, - &s4_fixed_pll, - &s4_fclk_div2, - &s4_fclk_div3, - &s4_fclk_div4, - &s4_fclk_div5, - &s4_fclk_div7, - &s4_fclk_div2p5, - &s4_gp0_pll_dco, - &s4_gp0_pll, - &s4_hifi_pll_dco, - &s4_hifi_pll, - &s4_hdmi_pll_dco, - &s4_hdmi_pll_od, - &s4_hdmi_pll, - &s4_mpll_50m, - &s4_mpll0_div, - &s4_mpll0, - &s4_mpll1_div, - &s4_mpll1, - &s4_mpll2_div, - &s4_mpll2, - &s4_mpll3_div, - &s4_mpll3, -}; - static const struct reg_sequence s4_init_regs[] = { { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 }, }; @@ -859,10 +832,6 @@ static int meson_s4_pll_probe(struct platform_device *pdev) return dev_err_probe(dev, ret, "Failed to init registers\n"); - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++) - s4_pll_clk_regmaps[i]->map = regmap; - /* Register clocks */ for (i = 0; i < s4_pll_clks.num; i++) { /* array might be sparse */ From 8a65268500b00ecee5402ef9f80618ff73f30707 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 23 Jun 2025 18:37:39 +0200 Subject: [PATCH 8/8] clk: amlogic: s4: remove unused data Following the removal of the clk_regmap clock table from the s4-peripherals clock controller driver, it appears some clocks are unused, which means these are not exported or even registered. In all likelihood, these clocks have not been tested. Remove the unused clocks for now. These can added back later when they have been properly tested. Reviewed-by: Chuan Liu Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-3-ff04918211cc@baylibre.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/s4-peripherals.c | 112 ----------------------------- 1 file changed, 112 deletions(-) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c index fd2d4d725f9e..c9400cf54c84 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3174,118 +3174,6 @@ static struct clk_regmap s4_gen_clk = { }, }; -static const struct clk_parent_data s4_adc_extclk_in_parent_data[] = { - { .fw_name = "xtal", }, - { .fw_name = "fclk_div4", }, - { .fw_name = "fclk_div3", }, - { .fw_name = "fclk_div5", }, - { .fw_name = "fclk_div7", }, - { .fw_name = "mpll2", }, - { .fw_name = "gp0_pll", }, - { .fw_name = "hifi_pll", }, -}; - -static struct clk_regmap s4_adc_extclk_in_mux = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_DEMOD_CLK_CTRL, - .mask = 0x7, - .shift = 25, - }, - .hw.init = &(struct clk_init_data){ - .name = "adc_extclk_in_mux", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_adc_extclk_in_parent_data, - .num_parents = ARRAY_SIZE(s4_adc_extclk_in_parent_data), - .flags = 0, - }, -}; - -static struct clk_regmap s4_adc_extclk_in_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_DEMOD_CLK_CTRL, - .shift = 16, - .width = 7, - }, - .hw.init = &(struct clk_init_data){ - .name = "adc_extclk_in_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_adc_extclk_in_mux.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_adc_extclk_in_gate = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_DEMOD_CLK_CTRL, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data){ - .name = "adc_extclk_in", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_adc_extclk_in_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_demod_core_clk_mux = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_DEMOD_CLK_CTRL, - .mask = 0x3, - .shift = 9, - }, - .hw.init = &(struct clk_init_data){ - .name = "demod_core_clk_mux", - .ops = &clk_regmap_mux_ops, - .parent_data = (const struct clk_parent_data []) { - { .fw_name = "xtal", }, - { .fw_name = "fclk_div7", }, - { .fw_name = "fclk_div4", }, - { .hw = &s4_adc_extclk_in_gate.hw } - }, - .num_parents = 4, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_demod_core_clk_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_DEMOD_CLK_CTRL, - .shift = 0, - .width = 7, - }, - .hw.init = &(struct clk_init_data){ - .name = "demod_core_clk_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_demod_core_clk_mux.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_demod_core_clk_gate = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_DEMOD_CLK_CTRL, - .bit_idx = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "demod_core_clk", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_demod_core_clk_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)