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ep93xx: Make syscon access functions private to SoC

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The syscon access functions are no longer used outside of the core
EP93xx code. Move their definitions into the SoC code.

Signed-off-by: Ryan Mallon <rmallon@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@iki.fi>
Acked-by: Hartley Sweeten <hsweeten@visionengravers.com>
This commit is contained in:
Ryan Mallon
2012-01-11 13:43:02 +11:00
parent 08932d8196
commit 999c53fb22
4 changed files with 15 additions and 16 deletions
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1
arch/arm/mach-ep93xx/clock.c
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@@ -25,6 +25,7 @@
#include <asm/div64.h> #include <asm/div64.h>
#include "soc.h"
struct clk { struct clk {
struct clk *parent; struct clk *parent;

2
arch/arm/mach-ep93xx/core.c
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@@ -205,7 +205,6 @@ void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
spin_unlock_irqrestore(&syscon_swlock, flags); spin_unlock_irqrestore(&syscon_swlock, flags);
} }
EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
{ {
@@ -222,7 +221,6 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
spin_unlock_irqrestore(&syscon_swlock, flags); spin_unlock_irqrestore(&syscon_swlock, flags);
} }
EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
/** /**
* ep93xx_chip_revision() - returns the EP93xx chip revision * ep93xx_chip_revision() - returns the EP93xx chip revision

14
arch/arm/mach-ep93xx/include/mach/platform.h
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@@ -21,20 +21,6 @@ struct ep93xx_eth_data
void ep93xx_map_io(void); void ep93xx_map_io(void);
void ep93xx_init_irq(void); void ep93xx_init_irq(void);
/* EP93xx System Controller software locked register write */
void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
static inline void ep93xx_devcfg_set_bits(unsigned int bits)
{
ep93xx_devcfg_set_clear(bits, 0x00);
}
static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
{
ep93xx_devcfg_set_clear(0x00, bits);
}
#define EP93XX_CHIP_REV_D0 3 #define EP93XX_CHIP_REV_D0 3
#define EP93XX_CHIP_REV_D1 4 #define EP93XX_CHIP_REV_D1 4
#define EP93XX_CHIP_REV_E0 5 #define EP93XX_CHIP_REV_E0 5

14
arch/arm/mach-ep93xx/soc.h
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@@ -104,4 +104,18 @@
#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000) #define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000) #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
/* EP93xx System Controller software locked register write */
void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
static inline void ep93xx_devcfg_set_bits(unsigned int bits)
{
ep93xx_devcfg_set_clear(bits, 0x00);
}
static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
{
ep93xx_devcfg_set_clear(0x00, bits);
}
#endif /* _EP93XX_SOC_H */ #endif /* _EP93XX_SOC_H */