Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (45 commits) [MIPS] Pb1200/DBAu1200: move platform code to its proper place [MIPS] Fix handling of trap and breakpoint instructions [MIPS] Pb1200: do register SMC 91C111 [MIPS] DBAu1200: fix bad SMC 91C111 resource size [NET] Kconfig: Rename MIKROTIK_RB500 -> MIKROTIK_RB532 [MIPS] IP27: Fix build bug due to missing include [MIPS] Fix some sparse warnings on traps.c and irq-msc01.c [MIPS] cevt-gt641xx: Kill unnecessary include [MIPS] DS1287: Add clockevent driver [MIPS] add DECstation I/O ASIC clocksource [MIPS] rbtx4938: minor cleanup [MIPS] Alchemy: kill unused PCI_IRQ_TABLE_LOOKUP macro [MIPS] rbtx4938: misc cleanups [MIPS] jmr3927: use generic txx9 gpio [MIPS] rbhma4500: use generic txx9 gpio [MIPS] generic txx9 gpio support [MIPS] make fallback gpio.h gpiolib-friendly [MIPS] unexport null_perf_irq() and make it static [MIPS] unexport rtc_mips_set_time() [MIPS] unexport copy_from_user_page() ...
This commit is contained in:
Linus Torvalds
18
include/asm-mips/cmp.h
Normal file
18
include/asm-mips/cmp.h
Normal file
@@ -0,0 +1,18 @@
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#ifndef _ASM_CMP_H
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#define _ASM_CMP_H
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/*
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* Definitions for CMP multitasking on MIPS cores
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*/
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struct task_struct;
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extern void cmp_smp_setup(void);
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extern void cmp_smp_finish(void);
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extern void cmp_boot_secondary(int cpu, struct task_struct *t);
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extern void cmp_init_secondary(void);
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extern void cmp_cpus_done(void);
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extern void cmp_prepare_cpus(unsigned int max_cpus);
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/* This is platform specific */
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extern void cmp_send_ipi(int cpu, unsigned int action);
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#endif /* _ASM_CMP_H */
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@@ -29,7 +29,7 @@
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#define PRID_COMP_ALCHEMY 0x030000
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#define PRID_COMP_SIBYTE 0x040000
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#define PRID_COMP_SANDCRAFT 0x050000
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#define PRID_COMP_PHILIPS 0x060000
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#define PRID_COMP_NXP 0x060000
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#define PRID_COMP_TOSHIBA 0x070000
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#define PRID_COMP_LSI 0x080000
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#define PRID_COMP_LEXRA 0x0b0000
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@@ -89,6 +89,7 @@
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#define PRID_IMP_34K 0x9500
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#define PRID_IMP_24KE 0x9600
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#define PRID_IMP_74K 0x9700
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#define PRID_IMP_1004K 0x9900
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#define PRID_IMP_LOONGSON1 0x4200
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#define PRID_IMP_LOONGSON2 0x6300
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@@ -194,9 +195,9 @@ enum cpu_type_enum {
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/*
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* MIPS32 class processors
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*/
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
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CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550,
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CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
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CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
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CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
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/*
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* MIPS64 class processors
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@@ -33,4 +33,6 @@ static inline u32 ioasic_read(unsigned int reg)
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extern void init_ioasic_irqs(int base);
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extern void dec_ioasic_clocksource_init(void);
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#endif /* __ASM_DEC_IOASIC_H */
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27
include/asm-mips/ds1287.h
Normal file
27
include/asm-mips/ds1287.h
Normal file
@@ -0,0 +1,27 @@
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/*
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* DS1287 timer functions.
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*
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* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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||||
* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ASM_DS1287_H
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#define __ASM_DS1287_H
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extern int ds1287_timer_state(void);
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extern void ds1287_set_base_clock(unsigned int clock);
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extern int ds1287_clockevent_init(int irq);
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#endif
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117
include/asm-mips/gcmpregs.h
Normal file
117
include/asm-mips/gcmpregs.h
Normal file
@@ -0,0 +1,117 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
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*
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* Multiprocessor Subsystem Register Definitions
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*
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*/
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#ifndef _ASM_GCMPREGS_H
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#define _ASM_GCMPREGS_H
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/* Offsets to major blocks within GCMP from GCMP base */
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#define GCMP_GCB_OFS 0x0000 /* Global Control Block */
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#define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */
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#define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */
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#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
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/* Offsets to individual GCMP registers from GCMP base */
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#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
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#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
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#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
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#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
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#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
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/* GCMP register access */
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#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
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#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
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#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
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#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
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/* Mask generation */
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#define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF)
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#define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits)
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#define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits)
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#define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits)
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/* GCB registers */
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#define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */
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#define GCMP_GCB_GC_NUMIOCU_SHF 8
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#define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4)
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#define GCMP_GCB_GC_NUMCORES_SHF 0
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#define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8)
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#define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */
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#define GCMP_GCB_GCMPB_GCMPBASE_SHF 15
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#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
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#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
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#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
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#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0
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#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1
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#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
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#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
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#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
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#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
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#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
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#define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8)
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#define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */
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#define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */
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#define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */
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#define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27
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#define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
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#define GCMP_GCB_GMEC_ERROR_INFO_SHF 0
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#define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27)
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#define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */
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#define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */
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#define GCMP_GCB_GMEO_ERROR_2ND_SHF 0
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#define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5)
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#define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */
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#define GCMP_GCB_GICBA_BASE_SHF 17
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#define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15)
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#define GCMP_GCB_GICBA_EN_SHF 0
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#define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1)
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/* GCB Regions */
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#define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */
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#define GCMP_GCB_CMxBASE_BASE_SHF 16
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#define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16)
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#define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */
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#define GCMP_GCB_CMxMASK_MASK_SHF 16
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#define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16)
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#define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0
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#define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
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#define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0
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#define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1
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#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
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#define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
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/* Core local/Core other control block registers */
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#define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */
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#define GCMP_CCB_RESETR_INRESET_SHF 0
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#define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16)
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#define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */
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#define GCMP_CCB_COHCTL_DOMAIN_SHF 0
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#define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8)
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#define GCMP_CCB_CFG_OFS 0x0010 /* Config */
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#define GCMP_CCB_CFG_IOCUTYPE_SHF 10
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#define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2)
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#define GCMP_CCB_CFG_IOCUTYPE_CPU 0
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#define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1
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#define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2
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#define GCMP_CCB_CFG_NUMVPE_SHF 0
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#define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10)
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#define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */
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#define GCMP_CCB_OTHER_CORENUM_SHF 16
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#define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16)
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#define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */
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#define GCMP_CCB_RESETBASE_BEV_SHF 12
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#define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20)
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#define GCMP_CCB_ID_OFS 0x0028 /* Identification */
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#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */
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#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
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#endif /* _ASM_GCMPREGS_H */
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487
include/asm-mips/gic.h
Normal file
487
include/asm-mips/gic.h
Normal file
@@ -0,0 +1,487 @@
|
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/*
|
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* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
|
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*
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* GIC Register Definitions
|
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*
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*/
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#ifndef _ASM_GICREGS_H
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#define _ASM_GICREGS_H
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#undef GICISBYTELITTLEENDIAN
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#define GICISWORDLITTLEENDIAN
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|
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/* Constants */
|
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#define GIC_POL_POS 1
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#define GIC_POL_NEG 0
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#define GIC_TRIG_EDGE 1
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#define GIC_TRIG_LEVEL 0
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#define GIC_NUM_INTRS 32
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#define MSK(n) ((1 << (n)) - 1)
|
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#define REG32(addr) (*(volatile unsigned int *) (addr))
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#define REG(base, offs) REG32((unsigned int)(base) + offs##_##OFS)
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#define REGP(base, phys) REG32((unsigned int)(base) + (phys))
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|
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/* Accessors */
|
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#define GIC_REG(segment, offset) \
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REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
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#define GIC_REG_ADDR(segment, offset) \
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REG32(_gic_base + segment##_##SECTION_OFS + offset)
|
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|
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#define GIC_ABS_REG(segment, offset) \
|
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(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
|
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#define GIC_REG_ABS_ADDR(segment, offset) \
|
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(_gic_base + segment##_##SECTION_OFS + offset)
|
||||
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#ifdef GICISBYTELITTLEENDIAN
|
||||
#define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data)
|
||||
#define GICWRITE(reg, data) (reg) = cpu_to_le32(data)
|
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#define GICBIS(reg, bits) \
|
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({unsigned int data; \
|
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GICREAD(reg, data); \
|
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data |= bits; \
|
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GICWRITE(reg, data); \
|
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})
|
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|
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#else
|
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#define GICREAD(reg, data) (data) = (reg)
|
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#define GICWRITE(reg, data) (reg) = (data)
|
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#define GICBIS(reg, bits) (reg) |= (bits)
|
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#endif
|
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|
||||
|
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/* GIC Address Space */
|
||||
#define SHARED_SECTION_OFS 0x0000
|
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#define SHARED_SECTION_SIZE 0x8000
|
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#define VPE_LOCAL_SECTION_OFS 0x8000
|
||||
#define VPE_LOCAL_SECTION_SIZE 0x4000
|
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#define VPE_OTHER_SECTION_OFS 0xc000
|
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#define VPE_OTHER_SECTION_SIZE 0x4000
|
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#define USM_VISIBLE_SECTION_OFS 0x10000
|
||||
#define USM_VISIBLE_SECTION_SIZE 0x10000
|
||||
|
||||
/* Register Map for Shared Section */
|
||||
#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
|
||||
|
||||
#define GIC_SH_CONFIG_OFS 0x0000
|
||||
|
||||
/* Shared Global Counter */
|
||||
#define GIC_SH_COUNTER_31_00_OFS 0x0010
|
||||
#define GIC_SH_COUNTER_63_32_OFS 0x0014
|
||||
|
||||
/* Interrupt Polarity */
|
||||
#define GIC_SH_POL_31_0_OFS 0x0100
|
||||
#define GIC_SH_POL_63_32_OFS 0x0104
|
||||
#define GIC_SH_POL_95_64_OFS 0x0108
|
||||
#define GIC_SH_POL_127_96_OFS 0x010c
|
||||
#define GIC_SH_POL_159_128_OFS 0x0110
|
||||
#define GIC_SH_POL_191_160_OFS 0x0114
|
||||
#define GIC_SH_POL_223_192_OFS 0x0118
|
||||
#define GIC_SH_POL_255_224_OFS 0x011c
|
||||
|
||||
/* Edge/Level Triggering */
|
||||
#define GIC_SH_TRIG_31_0_OFS 0x0180
|
||||
#define GIC_SH_TRIG_63_32_OFS 0x0184
|
||||
#define GIC_SH_TRIG_95_64_OFS 0x0188
|
||||
#define GIC_SH_TRIG_127_96_OFS 0x018c
|
||||
#define GIC_SH_TRIG_159_128_OFS 0x0190
|
||||
#define GIC_SH_TRIG_191_160_OFS 0x0194
|
||||
#define GIC_SH_TRIG_223_192_OFS 0x0198
|
||||
#define GIC_SH_TRIG_255_224_OFS 0x019c
|
||||
|
||||
/* Dual Edge Triggering */
|
||||
#define GIC_SH_DUAL_31_0_OFS 0x0200
|
||||
#define GIC_SH_DUAL_63_32_OFS 0x0204
|
||||
#define GIC_SH_DUAL_95_64_OFS 0x0208
|
||||
#define GIC_SH_DUAL_127_96_OFS 0x020c
|
||||
#define GIC_SH_DUAL_159_128_OFS 0x0210
|
||||
#define GIC_SH_DUAL_191_160_OFS 0x0214
|
||||
#define GIC_SH_DUAL_223_192_OFS 0x0218
|
||||
#define GIC_SH_DUAL_255_224_OFS 0x021c
|
||||
|
||||
/* Set/Clear corresponding bit in Edge Detect Register */
|
||||
#define GIC_SH_WEDGE_OFS 0x0280
|
||||
|
||||
/* Reset Mask - Disables Interrupt */
|
||||
#define GIC_SH_RMASK_31_0_OFS 0x0300
|
||||
#define GIC_SH_RMASK_63_32_OFS 0x0304
|
||||
#define GIC_SH_RMASK_95_64_OFS 0x0308
|
||||
#define GIC_SH_RMASK_127_96_OFS 0x030c
|
||||
#define GIC_SH_RMASK_159_128_OFS 0x0310
|
||||
#define GIC_SH_RMASK_191_160_OFS 0x0314
|
||||
#define GIC_SH_RMASK_223_192_OFS 0x0318
|
||||
#define GIC_SH_RMASK_255_224_OFS 0x031c
|
||||
|
||||
/* Set Mask (WO) - Enables Interrupt */
|
||||
#define GIC_SH_SMASK_31_0_OFS 0x0380
|
||||
#define GIC_SH_SMASK_63_32_OFS 0x0384
|
||||
#define GIC_SH_SMASK_95_64_OFS 0x0388
|
||||
#define GIC_SH_SMASK_127_96_OFS 0x038c
|
||||
#define GIC_SH_SMASK_159_128_OFS 0x0390
|
||||
#define GIC_SH_SMASK_191_160_OFS 0x0394
|
||||
#define GIC_SH_SMASK_223_192_OFS 0x0398
|
||||
#define GIC_SH_SMASK_255_224_OFS 0x039c
|
||||
|
||||
/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
|
||||
#define GIC_SH_MASK_31_0_OFS 0x0400
|
||||
#define GIC_SH_MASK_63_32_OFS 0x0404
|
||||
#define GIC_SH_MASK_95_64_OFS 0x0408
|
||||
#define GIC_SH_MASK_127_96_OFS 0x040c
|
||||
#define GIC_SH_MASK_159_128_OFS 0x0410
|
||||
#define GIC_SH_MASK_191_160_OFS 0x0414
|
||||
#define GIC_SH_MASK_223_192_OFS 0x0418
|
||||
#define GIC_SH_MASK_255_224_OFS 0x041c
|
||||
|
||||
/* Pending Global Interrupts (RO) */
|
||||
#define GIC_SH_PEND_31_0_OFS 0x0480
|
||||
#define GIC_SH_PEND_63_32_OFS 0x0484
|
||||
#define GIC_SH_PEND_95_64_OFS 0x0488
|
||||
#define GIC_SH_PEND_127_96_OFS 0x048c
|
||||
#define GIC_SH_PEND_159_128_OFS 0x0490
|
||||
#define GIC_SH_PEND_191_160_OFS 0x0494
|
||||
#define GIC_SH_PEND_223_192_OFS 0x0498
|
||||
#define GIC_SH_PEND_255_224_OFS 0x049c
|
||||
|
||||
#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
|
||||
|
||||
/* Maps Interrupt X to a Pin */
|
||||
#define GIC_SH_MAP_TO_PIN(intr) \
|
||||
(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
|
||||
|
||||
#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
|
||||
|
||||
/* Maps Interrupt X to a VPE */
|
||||
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
|
||||
(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
|
||||
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
|
||||
|
||||
/* Polarity : Reset Value is always 0 */
|
||||
#define GIC_SH_SET_POLARITY_OFS 0x0100
|
||||
#define GIC_SET_POLARITY(intr, pol) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
|
||||
|
||||
/* Triggering : Reset Value is always 0 */
|
||||
#define GIC_SH_SET_TRIGGER_OFS 0x0180
|
||||
#define GIC_SET_TRIGGER(intr, trig) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
|
||||
|
||||
/* Mask manipulation */
|
||||
#define GIC_SH_SMASK_OFS 0x0380
|
||||
#define GIC_SET_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
|
||||
|
||||
#define GIC_SH_RMASK_OFS 0x0300
|
||||
#define GIC_CLR_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
|
||||
|
||||
/* Register Map for Local Section */
|
||||
#define GIC_VPE_CTL_OFS 0x0000
|
||||
#define GIC_VPE_PEND_OFS 0x0004
|
||||
#define GIC_VPE_MASK_OFS 0x0008
|
||||
#define GIC_VPE_RMASK_OFS 0x000c
|
||||
#define GIC_VPE_SMASK_OFS 0x0010
|
||||
#define GIC_VPE_WD_MAP_OFS 0x0040
|
||||
#define GIC_VPE_COMPARE_MAP_OFS 0x0044
|
||||
#define GIC_VPE_TIMER_MAP_OFS 0x0048
|
||||
#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
|
||||
#define GIC_VPE_SWINT0_MAP_OFS 0x0054
|
||||
#define GIC_VPE_SWINT1_MAP_OFS 0x0058
|
||||
#define GIC_VPE_OTHER_ADDR_OFS 0x0080
|
||||
#define GIC_VPE_WD_CONFIG0_OFS 0x0090
|
||||
#define GIC_VPE_WD_COUNT0_OFS 0x0094
|
||||
#define GIC_VPE_WD_INITIAL0_OFS 0x0098
|
||||
#define GIC_VPE_COMPARE_LO_OFS 0x00a0
|
||||
#define GIC_VPE_COMPARE_HI 0x00a4
|
||||
|
||||
#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
|
||||
#define GIC_VPE_EIC_SS(intr) \
|
||||
(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
|
||||
|
||||
#define GIC_VPE_EIC_VEC_BASE 0x0800
|
||||
#define GIC_VPE_EIC_VEC(intr) \
|
||||
(GIC_VPE_EIC_VEC_BASE + (4 * intr))
|
||||
|
||||
#define GIC_VPE_TENABLE_NMI_OFS 0x1000
|
||||
#define GIC_VPE_TENABLE_YQ_OFS 0x1004
|
||||
#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
|
||||
#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
|
||||
|
||||
/* User Mode Visible Section Register Map */
|
||||
#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
|
||||
#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
|
||||
|
||||
#else /* CONFIG_CPU_BIG_ENDIAN */
|
||||
|
||||
#define GIC_SH_CONFIG_OFS 0x0000
|
||||
|
||||
/* Shared Global Counter */
|
||||
#define GIC_SH_COUNTER_31_00_OFS 0x0014
|
||||
#define GIC_SH_COUNTER_63_32_OFS 0x0010
|
||||
|
||||
/* Interrupt Polarity */
|
||||
#define GIC_SH_POL_31_0_OFS 0x0104
|
||||
#define GIC_SH_POL_63_32_OFS 0x0100
|
||||
#define GIC_SH_POL_95_64_OFS 0x010c
|
||||
#define GIC_SH_POL_127_96_OFS 0x0108
|
||||
#define GIC_SH_POL_159_128_OFS 0x0114
|
||||
#define GIC_SH_POL_191_160_OFS 0x0110
|
||||
#define GIC_SH_POL_223_192_OFS 0x011c
|
||||
#define GIC_SH_POL_255_224_OFS 0x0118
|
||||
|
||||
/* Edge/Level Triggering */
|
||||
#define GIC_SH_TRIG_31_0_OFS 0x0184
|
||||
#define GIC_SH_TRIG_63_32_OFS 0x0180
|
||||
#define GIC_SH_TRIG_95_64_OFS 0x018c
|
||||
#define GIC_SH_TRIG_127_96_OFS 0x0188
|
||||
#define GIC_SH_TRIG_159_128_OFS 0x0194
|
||||
#define GIC_SH_TRIG_191_160_OFS 0x0190
|
||||
#define GIC_SH_TRIG_223_192_OFS 0x019c
|
||||
#define GIC_SH_TRIG_255_224_OFS 0x0198
|
||||
|
||||
/* Dual Edge Triggering */
|
||||
#define GIC_SH_DUAL_31_0_OFS 0x0204
|
||||
#define GIC_SH_DUAL_63_32_OFS 0x0200
|
||||
#define GIC_SH_DUAL_95_64_OFS 0x020c
|
||||
#define GIC_SH_DUAL_127_96_OFS 0x0208
|
||||
#define GIC_SH_DUAL_159_128_OFS 0x0214
|
||||
#define GIC_SH_DUAL_191_160_OFS 0x0210
|
||||
#define GIC_SH_DUAL_223_192_OFS 0x021c
|
||||
#define GIC_SH_DUAL_255_224_OFS 0x0218
|
||||
|
||||
/* Set/Clear corresponding bit in Edge Detect Register */
|
||||
#define GIC_SH_WEDGE_OFS 0x0280
|
||||
|
||||
/* Reset Mask - Disables Interrupt */
|
||||
#define GIC_SH_RMASK_31_0_OFS 0x0304
|
||||
#define GIC_SH_RMASK_63_32_OFS 0x0300
|
||||
#define GIC_SH_RMASK_95_64_OFS 0x030c
|
||||
#define GIC_SH_RMASK_127_96_OFS 0x0308
|
||||
#define GIC_SH_RMASK_159_128_OFS 0x0314
|
||||
#define GIC_SH_RMASK_191_160_OFS 0x0310
|
||||
#define GIC_SH_RMASK_223_192_OFS 0x031c
|
||||
#define GIC_SH_RMASK_255_224_OFS 0x0318
|
||||
|
||||
/* Set Mask (WO) - Enables Interrupt */
|
||||
#define GIC_SH_SMASK_31_0_OFS 0x0384
|
||||
#define GIC_SH_SMASK_63_32_OFS 0x0380
|
||||
#define GIC_SH_SMASK_95_64_OFS 0x038c
|
||||
#define GIC_SH_SMASK_127_96_OFS 0x0388
|
||||
#define GIC_SH_SMASK_159_128_OFS 0x0394
|
||||
#define GIC_SH_SMASK_191_160_OFS 0x0390
|
||||
#define GIC_SH_SMASK_223_192_OFS 0x039c
|
||||
#define GIC_SH_SMASK_255_224_OFS 0x0398
|
||||
|
||||
/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
|
||||
#define GIC_SH_MASK_31_0_OFS 0x0404
|
||||
#define GIC_SH_MASK_63_32_OFS 0x0400
|
||||
#define GIC_SH_MASK_95_64_OFS 0x040c
|
||||
#define GIC_SH_MASK_127_96_OFS 0x0408
|
||||
#define GIC_SH_MASK_159_128_OFS 0x0414
|
||||
#define GIC_SH_MASK_191_160_OFS 0x0410
|
||||
#define GIC_SH_MASK_223_192_OFS 0x041c
|
||||
#define GIC_SH_MASK_255_224_OFS 0x0418
|
||||
|
||||
/* Pending Global Interrupts (RO) */
|
||||
#define GIC_SH_PEND_31_0_OFS 0x0484
|
||||
#define GIC_SH_PEND_63_32_OFS 0x0480
|
||||
#define GIC_SH_PEND_95_64_OFS 0x048c
|
||||
#define GIC_SH_PEND_127_96_OFS 0x0488
|
||||
#define GIC_SH_PEND_159_128_OFS 0x0494
|
||||
#define GIC_SH_PEND_191_160_OFS 0x0490
|
||||
#define GIC_SH_PEND_223_192_OFS 0x049c
|
||||
#define GIC_SH_PEND_255_224_OFS 0x0498
|
||||
|
||||
#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
|
||||
|
||||
/* Maps Interrupt X to a Pin */
|
||||
#define GIC_SH_MAP_TO_PIN(intr) \
|
||||
(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
|
||||
|
||||
#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
|
||||
|
||||
/*
|
||||
* Maps Interrupt X to a VPE. This is more complex than the LE case, as
|
||||
* odd and even registers need to be transposed. It does work - trust me!
|
||||
*/
|
||||
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
|
||||
(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
|
||||
(((((vpe) / 32) ^ 1) - 1) * 4))
|
||||
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
|
||||
|
||||
/* Polarity */
|
||||
#define GIC_SH_SET_POLARITY_OFS 0x0100
|
||||
#define GIC_SET_POLARITY(intr, pol) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
|
||||
|
||||
/* Triggering */
|
||||
#define GIC_SH_SET_TRIGGER_OFS 0x0180
|
||||
#define GIC_SET_TRIGGER(intr, trig) \
|
||||
GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
|
||||
|
||||
/* Mask manipulation */
|
||||
#define GIC_SH_SMASK_OFS 0x0380
|
||||
#define GIC_SET_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
|
||||
|
||||
#define GIC_SH_RMASK_OFS 0x0300
|
||||
#define GIC_CLR_INTR_MASK(intr, val) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))
|
||||
|
||||
/* Register Map for Local Section */
|
||||
#define GIC_VPE_CTL_OFS 0x0000
|
||||
#define GIC_VPE_PEND_OFS 0x0004
|
||||
#define GIC_VPE_MASK_OFS 0x0008
|
||||
#define GIC_VPE_RMASK_OFS 0x000c
|
||||
#define GIC_VPE_SMASK_OFS 0x0010
|
||||
#define GIC_VPE_WD_MAP_OFS 0x0040
|
||||
#define GIC_VPE_COMPARE_MAP_OFS 0x0044
|
||||
#define GIC_VPE_TIMER_MAP_OFS 0x0048
|
||||
#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
|
||||
#define GIC_VPE_SWINT0_MAP_OFS 0x0054
|
||||
#define GIC_VPE_SWINT1_MAP_OFS 0x0058
|
||||
#define GIC_VPE_OTHER_ADDR_OFS 0x0080
|
||||
#define GIC_VPE_WD_CONFIG0_OFS 0x0090
|
||||
#define GIC_VPE_WD_COUNT0_OFS 0x0094
|
||||
#define GIC_VPE_WD_INITIAL0_OFS 0x0098
|
||||
#define GIC_VPE_COMPARE_LO_OFS 0x00a4
|
||||
#define GIC_VPE_COMPARE_HI_OFS 0x00a0
|
||||
|
||||
#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
|
||||
#define GIC_VPE_EIC_SS(intr) \
|
||||
(GIC_EIC_SHADOW_SET_BASE + (4 * intr))
|
||||
|
||||
#define GIC_VPE_EIC_VEC_BASE 0x0800
|
||||
#define GIC_VPE_EIC_VEC(intr) \
|
||||
(GIC_VPE_EIC_VEC_BASE + (4 * intr))
|
||||
|
||||
#define GIC_VPE_TENABLE_NMI_OFS 0x1000
|
||||
#define GIC_VPE_TENABLE_YQ_OFS 0x1004
|
||||
#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
|
||||
#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
|
||||
|
||||
/* User Mode Visible Section Register Map */
|
||||
#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004
|
||||
#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000
|
||||
|
||||
#endif /* !LE */
|
||||
|
||||
/* Masks */
|
||||
#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
|
||||
#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
|
||||
|
||||
#define GIC_SH_CONFIG_COUNTBITS_SHF 24
|
||||
#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
|
||||
|
||||
#define GIC_SH_CONFIG_NUMINTRS_SHF 16
|
||||
#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
|
||||
|
||||
#define GIC_SH_CONFIG_NUMVPES_SHF 0
|
||||
#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
|
||||
|
||||
#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
|
||||
#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
|
||||
|
||||
#define GIC_MAP_TO_PIN_SHF 31
|
||||
#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
|
||||
#define GIC_MAP_TO_NMI_SHF 30
|
||||
#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
|
||||
#define GIC_MAP_TO_YQ_SHF 29
|
||||
#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
|
||||
#define GIC_MAP_SHF 0
|
||||
#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
|
||||
|
||||
/* GIC_VPE_CTL Masks */
|
||||
#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
|
||||
#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
|
||||
#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
|
||||
#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
|
||||
#define GIC_VPE_CTL_EIC_MODE_SHF 0
|
||||
#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
|
||||
|
||||
/* GIC_VPE_PEND Masks */
|
||||
#define GIC_VPE_PEND_WD_SHF 0
|
||||
#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
|
||||
#define GIC_VPE_PEND_CMP_SHF 1
|
||||
#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
|
||||
#define GIC_VPE_PEND_TIMER_SHF 2
|
||||
#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
|
||||
#define GIC_VPE_PEND_PERFCOUNT_SHF 3
|
||||
#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
|
||||
#define GIC_VPE_PEND_SWINT0_SHF 4
|
||||
#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
|
||||
#define GIC_VPE_PEND_SWINT1_SHF 5
|
||||
#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
|
||||
|
||||
/* GIC_VPE_RMASK Masks */
|
||||
#define GIC_VPE_RMASK_WD_SHF 0
|
||||
#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
|
||||
#define GIC_VPE_RMASK_CMP_SHF 1
|
||||
#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
|
||||
#define GIC_VPE_RMASK_TIMER_SHF 2
|
||||
#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
|
||||
#define GIC_VPE_RMASK_PERFCNT_SHF 3
|
||||
#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
|
||||
#define GIC_VPE_RMASK_SWINT0_SHF 4
|
||||
#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
|
||||
#define GIC_VPE_RMASK_SWINT1_SHF 5
|
||||
#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
|
||||
|
||||
/* GIC_VPE_SMASK Masks */
|
||||
#define GIC_VPE_SMASK_WD_SHF 0
|
||||
#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
|
||||
#define GIC_VPE_SMASK_CMP_SHF 1
|
||||
#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
|
||||
#define GIC_VPE_SMASK_TIMER_SHF 2
|
||||
#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
|
||||
#define GIC_VPE_SMASK_PERFCNT_SHF 3
|
||||
#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
|
||||
#define GIC_VPE_SMASK_SWINT0_SHF 4
|
||||
#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
|
||||
#define GIC_VPE_SMASK_SWINT1_SHF 5
|
||||
#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
|
||||
|
||||
/*
|
||||
* Set the Mapping of Interrupt X to a VPE.
|
||||
*/
|
||||
#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
|
||||
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
|
||||
GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
|
||||
|
||||
struct gic_pcpu_mask {
|
||||
DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
|
||||
};
|
||||
|
||||
struct gic_pending_regs {
|
||||
DECLARE_BITMAP(pending, GIC_NUM_INTRS);
|
||||
};
|
||||
|
||||
struct gic_intrmask_regs {
|
||||
DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt Meta-data specification. The ipiflag helps
|
||||
* in building ipi_map.
|
||||
*/
|
||||
struct gic_intr_map {
|
||||
unsigned int intrnum; /* Ext Intr Num */
|
||||
unsigned int cpunum; /* Directed to this CPU */
|
||||
unsigned int pin; /* Directed to this Pin */
|
||||
unsigned int polarity; /* Polarity : +/- */
|
||||
unsigned int trigtype; /* Trigger : Edge/Levl */
|
||||
unsigned int ipiflag; /* Is used for IPI ? */
|
||||
};
|
||||
|
||||
extern void gic_init(unsigned long gic_base_addr,
|
||||
unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
|
||||
unsigned int intrmap_size, unsigned int irqbase);
|
||||
|
||||
extern unsigned int gic_get_int(void);
|
||||
extern void gic_send_ipi(unsigned int intr);
|
||||
|
||||
#endif /* _ASM_GICREGS_H */
|
||||
@@ -273,7 +273,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
|
||||
* memory-like regions on I/O busses.
|
||||
*/
|
||||
#define ioremap_cachable(offset, size) \
|
||||
__ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
|
||||
__ioremap_mode((offset), (size), _page_cachable_default)
|
||||
|
||||
/*
|
||||
* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
|
||||
|
||||
@@ -99,8 +99,8 @@
|
||||
#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
|
||||
|
||||
/* DIPSW4 macro */
|
||||
#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0)
|
||||
#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
|
||||
#define jmr3927_dipsw1() (gpio_get_value(11) == 0)
|
||||
#define jmr3927_dipsw2() (gpio_get_value(10) == 0)
|
||||
#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
|
||||
#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
|
||||
|
||||
|
||||
@@ -314,6 +314,6 @@ struct tx3927_ccfg_reg {
|
||||
#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
|
||||
#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
|
||||
#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
|
||||
#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
|
||||
#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
|
||||
|
||||
#endif /* __ASM_TX3927_H */
|
||||
|
||||
@@ -22,18 +22,6 @@ struct txx927_sio_reg {
|
||||
volatile unsigned long rfifo;
|
||||
};
|
||||
|
||||
struct txx927_pio_reg {
|
||||
volatile unsigned long dout;
|
||||
volatile unsigned long din;
|
||||
volatile unsigned long dir;
|
||||
volatile unsigned long od;
|
||||
volatile unsigned long flag[2];
|
||||
volatile unsigned long pol;
|
||||
volatile unsigned long intc;
|
||||
volatile unsigned long maskcpu;
|
||||
volatile unsigned long maskext;
|
||||
};
|
||||
|
||||
/*
|
||||
* SIO
|
||||
*/
|
||||
|
||||
@@ -3,9 +3,8 @@
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Include file for Alchemy Semiconductor's Au1k CPU.
|
||||
*
|
||||
* Copyright 2000,2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
* Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
@@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
|
||||
|
||||
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
/* no CP0 timer irq */
|
||||
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
|
||||
#else
|
||||
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SDRAM Register Offsets
|
||||
*/
|
||||
@@ -1693,20 +1685,6 @@ enum soc_au1200_ints {
|
||||
#define IOMEM_RESOURCE_START 0x10000000
|
||||
#define IOMEM_RESOURCE_END 0xffffffff
|
||||
|
||||
/*
|
||||
* Borrowed from the PPC arch:
|
||||
* The following macro is used to lookup irqs in a standard table
|
||||
* format for those PPC systems that do not already have PCI
|
||||
* interrupts properly routed.
|
||||
*/
|
||||
/* FIXME - double check this from asm-ppc/pci-bridge.h */
|
||||
#define PCI_IRQ_TABLE_LOOKUP \
|
||||
({ long _ctl_ = -1; \
|
||||
if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
|
||||
_ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
|
||||
_ctl_; })
|
||||
|
||||
|
||||
#else /* Au1000 and Au1100 and Au1200 */
|
||||
|
||||
/* don't allow any legacy ports probing */
|
||||
|
||||
@@ -169,15 +169,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
|
||||
#define BCSR_INT_SD0INSERT 0x1000
|
||||
#define BCSR_INT_SD0EJECT 0x2000
|
||||
|
||||
#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300)
|
||||
#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT
|
||||
#define SMC91C111_PHYS_ADDR 0x19000300
|
||||
#define SMC91C111_INT DB1200_ETH_INT
|
||||
|
||||
#define AU1XXX_ATA_PHYS_ADDR (0x18800000)
|
||||
#define AU1XXX_ATA_REG_OFFSET (5)
|
||||
#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET)
|
||||
#define AU1XXX_ATA_INT DB1200_IDE_INT
|
||||
#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
|
||||
#define AU1XXX_ATA_RQSIZE 128
|
||||
#define IDE_PHYS_ADDR 0x18800000
|
||||
#define IDE_REG_SHIFT 5
|
||||
#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
|
||||
#define IDE_INT DB1200_IDE_INT
|
||||
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
|
||||
#define IDE_RQSIZE 128
|
||||
|
||||
#define NAND_PHYS_ADDR 0x20000000
|
||||
|
||||
|
||||
@@ -1,12 +1,18 @@
|
||||
#ifndef __ASM_MACH_GENERIC_GPIO_H
|
||||
#define __ASM_MACH_GENERIC_GPIO_H
|
||||
|
||||
#ifdef CONFIG_HAVE_GPIO_LIB
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
#else
|
||||
int gpio_request(unsigned gpio, const char *label);
|
||||
void gpio_free(unsigned gpio);
|
||||
int gpio_direction_input(unsigned gpio);
|
||||
int gpio_direction_output(unsigned gpio, int value);
|
||||
int gpio_get_value(unsigned gpio);
|
||||
void gpio_set_value(unsigned gpio, int value);
|
||||
#endif
|
||||
int gpio_to_irq(unsigned gpio);
|
||||
int irq_to_gpio(unsigned irq);
|
||||
|
||||
|
||||
@@ -54,4 +54,6 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
|
||||
.nr_balance_failed = 0, \
|
||||
}
|
||||
|
||||
#include <asm-generic/topology.h>
|
||||
|
||||
#endif /* _ASM_MACH_TOPOLOGY_H */
|
||||
|
||||
@@ -182,15 +182,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
|
||||
#define SET_VCC_VPP(VCC, VPP, SLOT)\
|
||||
((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
|
||||
|
||||
#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300)
|
||||
#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT
|
||||
#define SMC91C111_PHYS_ADDR 0x0D000300
|
||||
#define SMC91C111_INT PB1200_ETH_INT
|
||||
|
||||
#define AU1XXX_ATA_PHYS_ADDR (0x0C800000)
|
||||
#define AU1XXX_ATA_REG_OFFSET (5)
|
||||
#define AU1XXX_ATA_PHYS_LEN (16 << AU1XXX_ATA_REG_OFFSET)
|
||||
#define AU1XXX_ATA_INT PB1200_IDE_INT
|
||||
#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
|
||||
#define AU1XXX_ATA_RQSIZE 128
|
||||
#define IDE_PHYS_ADDR 0x0C800000
|
||||
#define IDE_REG_SHIFT 5
|
||||
#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
|
||||
#define IDE_INT PB1200_IDE_INT
|
||||
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
|
||||
#define IDE_RQSIZE 128
|
||||
|
||||
#define NAND_PHYS_ADDR 0x1C000000
|
||||
|
||||
|
||||
@@ -68,6 +68,7 @@
|
||||
#define MIPS_REVISION_CORID_CORE_FPGA3 9
|
||||
#define MIPS_REVISION_CORID_CORE_24K 10
|
||||
#define MIPS_REVISION_CORID_CORE_FPGA4 11
|
||||
#define MIPS_REVISION_CORID_CORE_FPGA5 12
|
||||
|
||||
/**** Artificial corid defines ****/
|
||||
/*
|
||||
|
||||
35
include/asm-mips/mips-boards/launch.h
Normal file
35
include/asm-mips/mips-boards/launch.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _ASSEMBLER_
|
||||
|
||||
struct cpulaunch {
|
||||
unsigned long pc;
|
||||
unsigned long gp;
|
||||
unsigned long sp;
|
||||
unsigned long a0;
|
||||
unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
#else
|
||||
|
||||
#define LOG2CPULAUNCH 5
|
||||
#define LAUNCH_PC 0
|
||||
#define LAUNCH_GP 4
|
||||
#define LAUNCH_SP 8
|
||||
#define LAUNCH_A0 12
|
||||
#define LAUNCH_FLAGS 28
|
||||
|
||||
#endif
|
||||
|
||||
#define LAUNCH_FREADY 1
|
||||
#define LAUNCH_FGO 2
|
||||
#define LAUNCH_FGONE 4
|
||||
|
||||
#define CPULAUNCH 0x00000f00
|
||||
#define NCPULAUNCH 8
|
||||
|
||||
/* Polling period in count cycles for secondary CPU's */
|
||||
#define LAUNCHPERIOD 10000
|
||||
@@ -51,6 +51,29 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
|
||||
return (unsigned long) ioremap(addr, 0x10000);
|
||||
}
|
||||
|
||||
/*
|
||||
* GCMP Specific definitions
|
||||
*/
|
||||
#define GCMP_BASE_ADDR 0x1fbf8000
|
||||
#define GCMP_ADDRSPACE_SZ (256 * 1024)
|
||||
|
||||
/*
|
||||
* GIC Specific definitions
|
||||
*/
|
||||
#define GIC_BASE_ADDR 0x1bdc0000
|
||||
#define GIC_ADDRSPACE_SZ (128 * 1024)
|
||||
|
||||
/*
|
||||
* MSC01 BIU Specific definitions
|
||||
* FIXME : These should be elsewhere ?
|
||||
*/
|
||||
#define MSC01_BIU_REG_BASE 0x1bc80000
|
||||
#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
|
||||
#define MSC01_SC_CFG_OFS 0x0110
|
||||
#define MSC01_SC_CFG_GICPRES_MSK 0x00000004
|
||||
#define MSC01_SC_CFG_GICPRES_SHF 2
|
||||
#define MSC01_SC_CFG_GICENA_SHF 3
|
||||
|
||||
/*
|
||||
* Malta RTC-device indirect register access.
|
||||
*/
|
||||
|
||||
@@ -39,7 +39,9 @@
|
||||
#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
|
||||
#define MIPSCPU_INT_MB1 3
|
||||
#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
|
||||
#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
|
||||
#define MIPSCPU_INT_MB2 4
|
||||
#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
|
||||
#define MIPSCPU_INT_MB3 5
|
||||
#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
|
||||
#define MIPSCPU_INT_MB4 6
|
||||
@@ -76,6 +78,31 @@
|
||||
#define MSC01E_INT_PERFCTR 10
|
||||
#define MSC01E_INT_CPUCTR 11
|
||||
|
||||
/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
|
||||
#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
|
||||
#define GIC_CPU_INT1 1 /* . */
|
||||
#define GIC_CPU_INT2 2 /* . */
|
||||
#define GIC_CPU_INT3 3 /* . */
|
||||
#define GIC_CPU_INT4 4 /* . */
|
||||
#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
|
||||
|
||||
#define GIC_EXT_INTR(x) x
|
||||
|
||||
/* Dummy data */
|
||||
#define X 0xdead
|
||||
|
||||
/* External Interrupts used for IPI */
|
||||
#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16
|
||||
#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17
|
||||
#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18
|
||||
#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19
|
||||
#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20
|
||||
#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21
|
||||
#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22
|
||||
#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23
|
||||
|
||||
#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void maltaint_init(void);
|
||||
#endif
|
||||
|
||||
36
include/asm-mips/mips-boards/maltasmp.h
Normal file
36
include/asm-mips/mips-boards/maltasmp.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* There are several SMP models supported
|
||||
* SMTC is mutually exclusive to other options (atm)
|
||||
*/
|
||||
#if defined(CONFIG_MIPS_MT_SMTC)
|
||||
#define malta_smtc 1
|
||||
#define malta_cmp 0
|
||||
#define malta_smvp 0
|
||||
#else
|
||||
#define malta_smtc 0
|
||||
#if defined(CONFIG_MIPS_CMP)
|
||||
extern int gcmp_present;
|
||||
#define malta_cmp gcmp_present
|
||||
#else
|
||||
#define malta_cmp 0
|
||||
#endif
|
||||
/* FIXME: should become COMFIG_MIPS_MT_SMVP */
|
||||
#if defined(CONFIG_MIPS_MT_SMP)
|
||||
#define malta_smvp 1
|
||||
#else
|
||||
#define malta_smvp 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mipsmtregs.h>
|
||||
|
||||
/* malta_smtc */
|
||||
#include <asm/smtc.h>
|
||||
#include <asm/smtc_ipi.h>
|
||||
|
||||
/* malta_cmp */
|
||||
#include <asm/cmp.h>
|
||||
|
||||
/* malta_smvp */
|
||||
#include <asm/smvp.h>
|
||||
@@ -197,8 +197,8 @@ static inline void __raw_evpe(void)
|
||||
" .set pop \n");
|
||||
}
|
||||
|
||||
/* Enable multiMT if previous suggested it should be.
|
||||
EMT_ENABLE to force */
|
||||
/* Enable virtual processor execution if previous suggested it should be.
|
||||
EVPE_ENABLE to force */
|
||||
|
||||
#define EVPE_ENABLE MVPCONTROL_EVP
|
||||
|
||||
@@ -238,8 +238,8 @@ static inline void __raw_emt(void)
|
||||
" .set reorder");
|
||||
}
|
||||
|
||||
/* enable multiVPE if previous suggested it should be.
|
||||
EVPE_ENABLE to force */
|
||||
/* enable multi-threaded execution if previous suggested it should be.
|
||||
EMT_ENABLE to force */
|
||||
|
||||
#define EMT_ENABLE VPECONTROL_TE
|
||||
|
||||
|
||||
@@ -107,7 +107,7 @@ static inline void pmd_clear(pmd_t *pmdp)
|
||||
pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||
#define pte_page(x) pfn_to_page(pte_pfn(x))
|
||||
#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
|
||||
static inline pte_t
|
||||
@@ -130,7 +130,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
|
||||
#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
|
||||
#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
|
||||
#endif
|
||||
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
|
||||
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
|
||||
|
||||
#define __pgd_offset(address) pgd_index(address)
|
||||
#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
|
||||
|
||||
@@ -32,14 +32,14 @@
|
||||
* unpredictable things. The code (when it is written) to deal with
|
||||
* this problem will be in the update_mmu_cache() code for the r4k.
|
||||
*/
|
||||
#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||
|
||||
#define _PAGE_PRESENT (1<<6) /* implemented in software */
|
||||
#define _PAGE_READ (1<<7) /* implemented in software */
|
||||
#define _PAGE_WRITE (1<<8) /* implemented in software */
|
||||
#define _PAGE_ACCESSED (1<<9) /* implemented in software */
|
||||
#define _PAGE_MODIFIED (1<<10) /* implemented in software */
|
||||
#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
|
||||
#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
|
||||
|
||||
#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
|
||||
#define _PAGE_GLOBAL (1<<0)
|
||||
@@ -47,15 +47,9 @@
|
||||
#define _PAGE_SILENT_READ (1<<1) /* synonym */
|
||||
#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
|
||||
#define _PAGE_SILENT_WRITE (1<<2)
|
||||
#define _CACHE_SHIFT 3
|
||||
#define _CACHE_MASK (7<<3)
|
||||
|
||||
/* MIPS32 defines only values 2 and 3. The rest are implementation
|
||||
* dependent.
|
||||
*/
|
||||
#define _CACHE_UNCACHED (2<<3)
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
|
||||
#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */
|
||||
|
||||
#else
|
||||
|
||||
#define _PAGE_PRESENT (1<<0) /* implemented in software */
|
||||
@@ -74,75 +68,72 @@
|
||||
#define _PAGE_SILENT_WRITE (1<<10)
|
||||
#define _CACHE_UNCACHED (1<<11)
|
||||
#define _CACHE_MASK (1<<11)
|
||||
#define _CACHE_CACHABLE_NONCOHERENT 0
|
||||
|
||||
#else
|
||||
|
||||
#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
|
||||
#define _PAGE_GLOBAL (1<<6)
|
||||
#define _PAGE_VALID (1<<7)
|
||||
#define _PAGE_SILENT_READ (1<<7) /* synonym */
|
||||
#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
|
||||
#define _PAGE_SILENT_WRITE (1<<8)
|
||||
#define _CACHE_SHIFT 9
|
||||
#define _CACHE_MASK (7<<9)
|
||||
|
||||
#ifdef CONFIG_CPU_SB1
|
||||
#endif
|
||||
#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
|
||||
|
||||
|
||||
/*
|
||||
* Cache attributes
|
||||
*/
|
||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
||||
|
||||
#define _CACHE_CACHABLE_NONCOHERENT 0
|
||||
|
||||
#elif defined(CONFIG_CPU_SB1)
|
||||
|
||||
/* No penalty for being coherent on the SB1, so just
|
||||
use it for "noncoherent" spaces, too. Shouldn't hurt. */
|
||||
|
||||
#define _CACHE_UNCACHED (2<<9)
|
||||
#define _CACHE_CACHABLE_COW (5<<9)
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (5<<9)
|
||||
#define _CACHE_UNCACHED_ACCELERATED (7<<9)
|
||||
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
|
||||
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
|
||||
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
|
||||
|
||||
#elif defined(CONFIG_CPU_RM9000)
|
||||
|
||||
#define _CACHE_WT (0 << 9)
|
||||
#define _CACHE_WTWA (1 << 9)
|
||||
#define _CACHE_UC_B (2 << 9)
|
||||
#define _CACHE_WB (3 << 9)
|
||||
#define _CACHE_CWBEA (4 << 9)
|
||||
#define _CACHE_CWB (5 << 9)
|
||||
#define _CACHE_UCNB (6 << 9)
|
||||
#define _CACHE_FPC (7 << 9)
|
||||
#define _CACHE_WT (0<<_CACHE_SHIFT)
|
||||
#define _CACHE_WTWA (1<<_CACHE_SHIFT)
|
||||
#define _CACHE_UC_B (2<<_CACHE_SHIFT)
|
||||
#define _CACHE_WB (3<<_CACHE_SHIFT)
|
||||
#define _CACHE_CWBEA (4<<_CACHE_SHIFT)
|
||||
#define _CACHE_CWB (5<<_CACHE_SHIFT)
|
||||
#define _CACHE_UCNB (6<<_CACHE_SHIFT)
|
||||
#define _CACHE_FPC (7<<_CACHE_SHIFT)
|
||||
|
||||
#define _CACHE_UNCACHED _CACHE_UC_B
|
||||
#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
|
||||
#define _CACHE_UNCACHED _CACHE_UC_B
|
||||
#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
|
||||
|
||||
#else
|
||||
|
||||
#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */
|
||||
#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */
|
||||
#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */
|
||||
#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */
|
||||
#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */
|
||||
#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */
|
||||
#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */
|
||||
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
|
||||
#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
|
||||
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
|
||||
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
|
||||
#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
|
||||
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
|
||||
#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
|
||||
#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
|
||||
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
|
||||
|
||||
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
|
||||
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
|
||||
|
||||
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
|
||||
|
||||
#ifdef CONFIG_MIPS_UNCACHED
|
||||
#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
|
||||
#elif defined(CONFIG_DMA_NONCOHERENT)
|
||||
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
|
||||
#elif defined(CONFIG_CPU_RM9000)
|
||||
#define PAGE_CACHABLE_DEFAULT _CACHE_CWB
|
||||
#else
|
||||
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
|
||||
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
|
||||
#else
|
||||
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
|
||||
#endif
|
||||
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
|
||||
|
||||
#endif /* _ASM_PGTABLE_BITS_H */
|
||||
|
||||
@@ -23,15 +23,15 @@ struct vm_area_struct;
|
||||
|
||||
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
|
||||
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
|
||||
PAGE_CACHABLE_DEFAULT)
|
||||
_page_cachable_default)
|
||||
#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
|
||||
PAGE_CACHABLE_DEFAULT)
|
||||
_page_cachable_default)
|
||||
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
|
||||
PAGE_CACHABLE_DEFAULT)
|
||||
_page_cachable_default)
|
||||
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
|
||||
_PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
|
||||
_PAGE_GLOBAL | _page_cachable_default)
|
||||
#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
|
||||
PAGE_CACHABLE_DEFAULT)
|
||||
_page_cachable_default)
|
||||
#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
|
||||
__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
|
||||
|
||||
@@ -40,23 +40,30 @@ struct vm_area_struct;
|
||||
* read. Also, write permissions imply read permissions. This is the closest
|
||||
* we can get by reasonable means..
|
||||
*/
|
||||
#define __P000 PAGE_NONE
|
||||
#define __P001 PAGE_READONLY
|
||||
#define __P010 PAGE_COPY
|
||||
#define __P011 PAGE_COPY
|
||||
#define __P100 PAGE_READONLY
|
||||
#define __P101 PAGE_READONLY
|
||||
#define __P110 PAGE_COPY
|
||||
#define __P111 PAGE_COPY
|
||||
|
||||
#define __S000 PAGE_NONE
|
||||
#define __S001 PAGE_READONLY
|
||||
#define __S010 PAGE_SHARED
|
||||
#define __S011 PAGE_SHARED
|
||||
#define __S100 PAGE_READONLY
|
||||
#define __S101 PAGE_READONLY
|
||||
#define __S110 PAGE_SHARED
|
||||
#define __S111 PAGE_SHARED
|
||||
/*
|
||||
* Dummy values to fill the table in mmap.c
|
||||
* The real values will be generated at runtime
|
||||
*/
|
||||
#define __P000 __pgprot(0)
|
||||
#define __P001 __pgprot(0)
|
||||
#define __P010 __pgprot(0)
|
||||
#define __P011 __pgprot(0)
|
||||
#define __P100 __pgprot(0)
|
||||
#define __P101 __pgprot(0)
|
||||
#define __P110 __pgprot(0)
|
||||
#define __P111 __pgprot(0)
|
||||
|
||||
#define __S000 __pgprot(0)
|
||||
#define __S001 __pgprot(0)
|
||||
#define __S010 __pgprot(0)
|
||||
#define __S011 __pgprot(0)
|
||||
#define __S100 __pgprot(0)
|
||||
#define __S101 __pgprot(0)
|
||||
#define __S110 __pgprot(0)
|
||||
#define __S111 __pgprot(0)
|
||||
|
||||
extern unsigned long _page_cachable_default;
|
||||
|
||||
/*
|
||||
* ZERO_PAGE is a global shared page that is always zero; used
|
||||
@@ -79,7 +86,7 @@ extern void paging_init(void);
|
||||
#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
|
||||
#define pmd_page_vaddr(pmd) pmd_val(pmd)
|
||||
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||
|
||||
#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
|
||||
#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
|
||||
@@ -182,7 +189,7 @@ extern pgd_t swapper_pg_dir[];
|
||||
* The following only work if pte_present() is true.
|
||||
* Undefined behaviour if not..
|
||||
*/
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||
static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
|
||||
static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
|
||||
static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
|
||||
@@ -311,7 +318,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
|
||||
*/
|
||||
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
|
||||
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
|
||||
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
|
||||
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
{
|
||||
pte.pte_low &= _PAGE_CHG_MASK;
|
||||
|
||||
30
include/asm-mips/r4k-timer.h
Normal file
30
include/asm-mips/r4k-timer.h
Normal file
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org)
|
||||
*/
|
||||
#ifndef __ASM_R4K_TYPES_H
|
||||
#define __ASM_R4K_TYPES_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#ifdef CONFIG_SYNC_R4K
|
||||
|
||||
extern void synchronise_count_master(void);
|
||||
extern void synchronise_count_slave(void);
|
||||
|
||||
#else
|
||||
|
||||
static inline void synchronise_count_master(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void synchronise_count_slave(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_R4K_TYPES_H */
|
||||
@@ -51,6 +51,7 @@ static inline void register_smp_ops(struct plat_smp_ops *ops)
|
||||
#endif /* !CONFIG_SMP */
|
||||
|
||||
extern struct plat_smp_ops up_smp_ops;
|
||||
extern struct plat_smp_ops cmp_smp_ops;
|
||||
extern struct plat_smp_ops vsmp_smp_ops;
|
||||
|
||||
#endif /* __ASM_SMP_OPS_H */
|
||||
|
||||
@@ -44,6 +44,7 @@ extern int mipsmt_build_cpu_map(int startslot);
|
||||
extern void mipsmt_prepare_cpus(void);
|
||||
extern void smtc_smp_finish(void);
|
||||
extern void smtc_boot_secondary(int cpu, struct task_struct *t);
|
||||
extern void smtc_cpus_done(void);
|
||||
|
||||
/*
|
||||
* Sharing the TLB between multiple VPEs means that the
|
||||
|
||||
19
include/asm-mips/smvp.h
Normal file
19
include/asm-mips/smvp.h
Normal file
@@ -0,0 +1,19 @@
|
||||
#ifndef _ASM_SMVP_H
|
||||
#define _ASM_SMVP_H
|
||||
|
||||
/*
|
||||
* Definitions for SMVP multitasking on MIPS MT cores
|
||||
*/
|
||||
struct task_struct;
|
||||
|
||||
extern void smvp_smp_setup(void);
|
||||
extern void smvp_smp_finish(void);
|
||||
extern void smvp_boot_secondary(int cpu, struct task_struct *t);
|
||||
extern void smvp_init_secondary(void);
|
||||
extern void smvp_smp_finish(void);
|
||||
extern void smvp_cpus_done(void);
|
||||
extern void smvp_prepare_cpus(unsigned int max_cpus);
|
||||
|
||||
/* This is platform specific */
|
||||
extern void smvp_send_ipi(int cpu, unsigned int action);
|
||||
#endif /* _ASM_SMVP_H */
|
||||
@@ -23,5 +23,7 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
|
||||
|
||||
extern void (*board_nmi_handler_setup)(void);
|
||||
extern void (*board_ejtag_handler_setup)(void);
|
||||
extern void (*board_bind_eic_interrupt)(int irq, int regset);
|
||||
extern void (*board_watchpoint_handler)(struct pt_regs *regs);
|
||||
|
||||
#endif /* _ASM_TRAPS_H */
|
||||
|
||||
@@ -67,44 +67,26 @@
|
||||
#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
|
||||
#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
|
||||
|
||||
#define rbtx4938_fpga_rev_ptr \
|
||||
((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
|
||||
#define rbtx4938_led_ptr \
|
||||
((volatile unsigned char *)RBTX4938_LED_ADDR)
|
||||
#define rbtx4938_dipsw_ptr \
|
||||
((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
|
||||
#define rbtx4938_bdipsw_ptr \
|
||||
((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
|
||||
#define rbtx4938_imask_ptr \
|
||||
((volatile unsigned char *)RBTX4938_IMASK_ADDR)
|
||||
#define rbtx4938_imask2_ptr \
|
||||
((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
|
||||
#define rbtx4938_intpol_ptr \
|
||||
((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
|
||||
#define rbtx4938_istat_ptr \
|
||||
((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
|
||||
#define rbtx4938_istat2_ptr \
|
||||
((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
|
||||
#define rbtx4938_imstat_ptr \
|
||||
((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
|
||||
#define rbtx4938_imstat2_ptr \
|
||||
((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
|
||||
#define rbtx4938_softint_ptr \
|
||||
((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
|
||||
#define rbtx4938_piosel_ptr \
|
||||
((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
|
||||
#define rbtx4938_spics_ptr \
|
||||
((volatile unsigned char *)RBTX4938_SPICS_ADDR)
|
||||
#define rbtx4938_sfpwr_ptr \
|
||||
((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
|
||||
#define rbtx4938_sfvol_ptr \
|
||||
((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
|
||||
#define rbtx4938_softreset_ptr \
|
||||
((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
|
||||
#define rbtx4938_softresetlock_ptr \
|
||||
((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
|
||||
#define rbtx4938_pcireset_ptr \
|
||||
((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
|
||||
#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
|
||||
#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
|
||||
#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
|
||||
#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
|
||||
#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
|
||||
#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
|
||||
#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
|
||||
#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
|
||||
#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
|
||||
#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
|
||||
#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
|
||||
#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
|
||||
#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
|
||||
#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
|
||||
#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
|
||||
#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
|
||||
#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
|
||||
#define rbtx4938_softresetlock_addr \
|
||||
((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
|
||||
#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
|
||||
|
||||
/*
|
||||
* IRQ mappings
|
||||
|
||||
@@ -13,8 +13,6 @@
|
||||
#ifndef __ASM_TX_BOARDS_TX4938_H
|
||||
#define __ASM_TX_BOARDS_TX4938_H
|
||||
|
||||
#include <asm/tx4938/tx4938_mips.h>
|
||||
|
||||
#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
|
||||
#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
|
||||
|
||||
@@ -54,28 +52,6 @@
|
||||
#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
|
||||
#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
|
||||
|
||||
#ifndef _LANGUAGE_ASSEMBLY
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
|
||||
|
||||
#define TX4938_RD08( reg ) (*(vu08*)(reg))
|
||||
#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD16( reg ) (*(vu16*)(reg))
|
||||
#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD32( reg ) (*(vu32*)(reg))
|
||||
#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD64( reg ) (*(vu64*)(reg))
|
||||
#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val))
|
||||
|
||||
#define TX4938_RD( reg ) TX4938_RD32( reg )
|
||||
#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define _CONST64(c) c
|
||||
#else
|
||||
@@ -261,18 +237,6 @@ struct tx4938_sio_reg {
|
||||
volatile unsigned long rfifo;
|
||||
};
|
||||
|
||||
struct tx4938_pio_reg {
|
||||
volatile unsigned long dout;
|
||||
volatile unsigned long din;
|
||||
volatile unsigned long dir;
|
||||
volatile unsigned long od;
|
||||
volatile unsigned long flag[2];
|
||||
volatile unsigned long pol;
|
||||
volatile unsigned long intc;
|
||||
volatile unsigned long maskcpu;
|
||||
volatile unsigned long maskext;
|
||||
};
|
||||
|
||||
struct tx4938_ndfmc_reg {
|
||||
endian_def_l2(unused0, dtr);
|
||||
endian_def_l2(unused1, mcr);
|
||||
@@ -642,7 +606,7 @@ struct tx4938_ccfg_reg {
|
||||
#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
|
||||
#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
|
||||
#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
|
||||
#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
|
||||
#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
|
||||
#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
|
||||
#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG)
|
||||
#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
|
||||
|
||||
@@ -1,54 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-mips/tx4938/tx4938_mips.h
|
||||
* Generic bitmask definitions
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
|
||||
#ifndef TX4938_TX4938_MIPS_H
|
||||
#define TX4938_TX4938_MIPS_H
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define reg_rd08(r) ((u8 )(*((vu8 *)(r))))
|
||||
#define reg_rd16(r) ((u16)(*((vu16*)(r))))
|
||||
#define reg_rd32(r) ((u32)(*((vu32*)(r))))
|
||||
#define reg_rd64(r) ((u64)(*((vu64*)(r))))
|
||||
|
||||
#define reg_wr08(r, v) ((*((vu8 *)(r)))=((u8 )(v)))
|
||||
#define reg_wr16(r, v) ((*((vu16*)(r)))=((u16)(v)))
|
||||
#define reg_wr32(r, v) ((*((vu32*)(r)))=((u32)(v)))
|
||||
#define reg_wr64(r, v) ((*((vu64*)(r)))=((u64)(v)))
|
||||
|
||||
typedef volatile __signed char vs8;
|
||||
typedef volatile unsigned char vu8;
|
||||
|
||||
typedef volatile __signed short vs16;
|
||||
typedef volatile unsigned short vu16;
|
||||
|
||||
typedef volatile __signed int vs32;
|
||||
typedef volatile unsigned int vu32;
|
||||
|
||||
typedef s8 s08;
|
||||
typedef vs8 vs08;
|
||||
|
||||
typedef u8 u08;
|
||||
typedef vu8 vu08;
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
|
||||
typedef volatile __signed__ long vs64;
|
||||
typedef volatile unsigned long vu64;
|
||||
|
||||
#else
|
||||
|
||||
typedef volatile __signed__ long long vs64;
|
||||
typedef volatile unsigned long long vu64;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
29
include/asm-mips/txx9pio.h
Normal file
29
include/asm-mips/txx9pio.h
Normal file
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* include/asm-mips/txx9pio.h
|
||||
* TX39/TX49 PIO controller definitions.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_TXX9PIO_H
|
||||
#define __ASM_TXX9PIO_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct txx9_pio_reg {
|
||||
__u32 dout;
|
||||
__u32 din;
|
||||
__u32 dir;
|
||||
__u32 od;
|
||||
__u32 flag[2];
|
||||
__u32 pol;
|
||||
__u32 intc;
|
||||
__u32 maskcpu;
|
||||
__u32 maskext;
|
||||
};
|
||||
|
||||
int txx9_gpio_init(unsigned long baseaddr,
|
||||
unsigned int base, unsigned int num);
|
||||
|
||||
#endif /* __ASM_TXX9PIO_H */
|
||||
Reference in New Issue
Block a user