Anders Berg 1d22924e1c
ARM: Add platform support for LSI AXM55xx SoC ...
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.
This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.
Signed-off-by: Anders Berg <anders.berg@lsi.com >
Acked-by: Linus Walleij <linus.walleij@linaro.org >
Signed-off-by: Arnd Bergmann <arnd@arndb.de >
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1d22924e1c
