23a71fd616
This patchset attempts to standardize the naming of dt-bindings documents based on the Broadcom vendor prefix of brcm. Although there are no guidelines currently present for how to name the dt-bindings document the "vendor,binding.txt" style is in use by some of the other vendors. Acked-by: Lee Jones <lee@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Rob Herring <robh@kernel.org>
38 lines
1.0 KiB
Plaintext
38 lines
1.0 KiB
Plaintext
* Interrupt Controller
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Properties:
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- compatible: "brcm,bcm3384-intc"
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Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs.
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- reg: Address/length pairs for each mask/status register set. Length must
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be 8. If multiple register sets are specified, the first set will
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handle IRQ offsets 0..31, the second set 32..63, and so on.
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- interrupt-controller: This is an interrupt controller.
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- #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge
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or polarity configuration is possible with this controller.
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- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or
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from another INTC.
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- interrupts: The IRQ on the parent controller.
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Example:
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periph_intc: periph_intc@14e00038 {
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compatible = "brcm,bcm3384-intc";
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/*
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* IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c
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* IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344
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*/
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reg = <0x14e00038 0x8 0x14e00340 0x8>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <4>;
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};
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