254056f3b1
When the cpu is powered down in a low power mode, the gic cpu interface may be reset, and when the cpu cluster is powered down, the gic distributor may also be reset. This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save and restore the gic cpu interface registers, and the CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save and restore the gic distributor registers. Original-author: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
/*
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* arch/arm/include/asm/hardware/gic.h
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*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_HARDWARE_GIC_H
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#define __ASM_ARM_HARDWARE_GIC_H
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#include <linux/compiler.h>
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#define GIC_CPU_CTRL 0x00
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#define GIC_CPU_PRIMASK 0x04
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#define GIC_CPU_BINPOINT 0x08
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#define GIC_CPU_INTACK 0x0c
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#define GIC_CPU_EOI 0x10
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#define GIC_CPU_RUNNINGPRI 0x14
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#define GIC_CPU_HIGHPRI 0x18
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#define GIC_DIST_CTRL 0x000
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#define GIC_DIST_CTR 0x004
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#define GIC_DIST_ENABLE_SET 0x100
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#define GIC_DIST_ENABLE_CLEAR 0x180
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#define GIC_DIST_PENDING_SET 0x200
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#define GIC_DIST_PENDING_CLEAR 0x280
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#define GIC_DIST_ACTIVE_BIT 0x300
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#define GIC_DIST_PRI 0x400
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#define GIC_DIST_TARGET 0x800
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#define GIC_DIST_CONFIG 0xc00
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#define GIC_DIST_SOFTINT 0xf00
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#ifndef __ASSEMBLY__
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extern void __iomem *gic_cpu_base_addr;
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extern struct irq_chip gic_arch_extn;
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void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
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void gic_secondary_init(unsigned int);
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void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
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void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
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void gic_enable_ppi(unsigned int);
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struct gic_chip_data {
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unsigned int irq_offset;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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#ifdef CONFIG_CPU_PM
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u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
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u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
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u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
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u32 __percpu *saved_ppi_enable;
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u32 __percpu *saved_ppi_conf;
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#endif
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unsigned int gic_irqs;
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};
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#endif
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#endif
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