Ben Widawsky a93e41618e
drm/i915: generalize pte vs. register BAR allocation ...
All gen6+ parts so far have 1 BAR which holds both the register space
and the GTT PTEs. Up until now, that was a 4MB BAR with half allocated
to each.
I have a strong hunch (wink, nod, wink) that future gens will also keep
a similar 50-50 split though the sizes may change. To help this along
change the code to obey the rule of half the total size instead of a
hard-coded 2MB.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
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a93e41618e