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linux/drivers/gpu/drm
Alexandre Courbot cfd044b028 drm/nouveau/falcon: fix base address of FBIF registers
All falcons have their FBIF registers starting at offset 0x600, with the
exception of the PMU and NVENC engines.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-07 17:05:13 +10:00
..
2017-02-23 12:10:12 +10:00
2017-02-23 12:10:12 +10:00
2017-02-23 12:10:12 +10:00
2017-01-26 10:45:31 +01:00
2017-01-26 10:45:14 +01:00
2016-12-30 11:43:40 +01:00