Andreas Färber 92c9e0c780
ARM: dts: zynq: Enable PL clocks for Parallella ...
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Cc: <stable@vger.kernel.org > # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de >
Acked-by: Michal Simek <michal.simek@xilinx.com >
Signed-off-by: Olof Johansson <olof@lixom.net >
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