mmc: host: Fix typos in comments across various files
This patch corrects several typos in comments within the mmc/host directory. No functional changes are introduced, only comment improvements for better readability. Detected using codespell. Signed-off-by: Yu Jiaoliang <yujiaoliang@vivo.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20240929093418.526901-1-yujiaoliang@vivo.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Ulf Hansson
parent
5bb798cfdf
commit
05edd60f0d
@@ -860,7 +860,7 @@ static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
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}
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/*
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* Configure given PDC buffer taking care of alignement issues.
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* Configure given PDC buffer taking care of alignment issues.
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* Update host->data_size and host->sg.
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*/
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static void atmci_pdc_set_single_buf(struct atmel_mci *host,
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@@ -543,7 +543,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
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cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
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}
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} else {
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/* Techincally, we should be getting all 48 bits of
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/* Technically, we should be getting all 48 bits of
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* the response (SD_RESP1 + SD_RESP2), but because
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* our response omits the CRC, our data ends up
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* being shifted 8 bits to the right. In this case,
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@@ -217,7 +217,7 @@ static int octeon_mmc_probe(struct platform_device *pdev)
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return PTR_ERR(base);
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host->dma_base = base;
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/*
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* To keep the register addresses shared we intentionaly use
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* To keep the register addresses shared we intentionally use
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* a negative offset here, first register used on Octeon therefore
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* starts at 0x20 (MIO_EMM_DMA_CFG).
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*/
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@@ -1182,7 +1182,7 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
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/*
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* Use the initial fifoth_val for PIO mode. If wm_algined
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* is set, we set watermark same as data size.
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* If next issued data may be transfered by DMA mode,
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* If next issued data may be transferred by DMA mode,
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* prev_blksz should be invalidated.
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*/
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if (host->wm_aligned)
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@@ -879,7 +879,7 @@ static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
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/*
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* The memory at the end of the controller used as bounce buffer for
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* the dram_access_quirk only accepts 32bit read/write access,
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* check the aligment and length of the data before starting the request.
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* check the alignment and length of the data before starting the request.
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*/
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if (host->dram_access_quirk && mrq->data) {
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mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
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@@ -77,7 +77,7 @@
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#define MCI_CPSM_INTERRUPT BIT(8)
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#define MCI_CPSM_PENDING BIT(9)
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#define MCI_CPSM_ENABLE BIT(10)
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/* Command register flag extenstions in the ST Micro versions */
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/* Command register flag extensions in the ST Micro versions */
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#define MCI_CPSM_ST_SDIO_SUSP BIT(11)
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#define MCI_CPSM_ST_ENCMD_COMPL BIT(12)
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#define MCI_CPSM_ST_NIEN BIT(13)
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@@ -1529,7 +1529,7 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
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writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
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} else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
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/*
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* ESDHC_STD_TUNING_EN may be configed in bootloader
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* ESDHC_STD_TUNING_EN may be configured in bootloader
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* or ROM code, so clear this bit here to make sure
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* the manual tuning can work.
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*/
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@@ -1631,7 +1631,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
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/*
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* If we have this property, then activate WP check.
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* Retrieveing and requesting the actual WP GPIO will happen
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* Retrieving and requesting the actual WP GPIO will happen
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* in the call to mmc_of_parse().
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*/
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if (of_property_read_bool(np, "wp-gpios"))
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@@ -2601,7 +2601,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
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sdhci_msm_handle_pwr_irq(host, 0);
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/*
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* Ensure that above writes are propogated before interrupt enablement
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* Ensure that above writes are propagated before interrupt enablement
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* in GIC.
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*/
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mb();
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