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Merge branch 'add-driver-support-for-eswin-eic7700-soc-ethernet-controller'

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Shangjuan Wei says:

====================
Add driver support for Eswin eic7700 SoC ethernet controller
====================

Link: https://patch.msgid.link/20251015113751.1114-1-weishangjuan@eswincomputing.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2025-10-16 16:07:24 -07:00
parent 7dbef65e54 ea77dbbdbc
commit 0c3cd7f044
4 changed files with 372 additions and 0 deletions
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127
Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml Normal file
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@@ -0,0 +1,127 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Eswin EIC7700 SOC Eth Controller
maintainers:
- Shuang Liang <liangshuang@eswincomputing.com>
- Zhi Li <lizhi2@eswincomputing.com>
- Shangjuan Wei <weishangjuan@eswincomputing.com>
description:
Platform glue layer implementation for STMMAC Ethernet driver.
select:
properties:
compatible:
contains:
enum:
- eswin,eic7700-qos-eth
required:
- compatible
allOf:
- $ref: snps,dwmac.yaml#
properties:
compatible:
items:
- const: eswin,eic7700-qos-eth
- const: snps,dwmac-5.20
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-names:
const: macirq
clocks:
items:
- description: AXI clock
- description: Configuration clock
- description: GMAC main clock
- description: Tx clock
clock-names:
items:
- const: axi
- const: cfg
- const: stmmaceth
- const: tx
resets:
maxItems: 1
reset-names:
items:
- const: stmmaceth
rx-internal-delay-ps:
enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
tx-internal-delay-ps:
enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
eswin,hsp-sp-csr:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- description: Phandle to HSP(High-Speed Peripheral) device
- description: Offset of phy control register for internal
or external clock selection
- description: Offset of AXI clock controller Low-Power request
register
- description: Offset of register controlling TX/RX clock delay
description: |
High-Speed Peripheral device needed to configure clock selection,
clock low-power mode and clock delay.
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- phy-mode
- resets
- reset-names
- rx-internal-delay-ps
- tx-internal-delay-ps
- eswin,hsp-sp-csr
unevaluatedProperties: false
examples:
- |
ethernet@50400000 {
compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
reg = <0x50400000 0x10000>;
clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
<&d0_clock 193>;
clock-names = "axi", "cfg", "stmmaceth", "tx";
interrupt-parent = <&plic>;
interrupts = <61>;
interrupt-names = "macirq";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
resets = <&reset 95>;
reset-names = "stmmaceth";
rx-internal-delay-ps = <200>;
tx-internal-delay-ps = <200>;
eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
snps,axi-config = <&stmmac_axi_setup>;
snps,aal;
snps,fixed-burst;
snps,tso;
stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <2>;
snps,wr_osr_lmt = <2>;
};
};

9
drivers/net/ethernet/stmicro/stmmac/Kconfig
View File

@@ -67,6 +67,15 @@ config DWMAC_ANARION
This selects the Anarion SoC glue layer support for the stmmac driver.
config DWMAC_EIC7700
tristate "Support for Eswin eic7700 ethernet driver"
depends on OF && HAS_DMA && ARCH_ESWIN || COMPILE_TEST
help
This driver supports the Eswin EIC7700 Ethernet controller,
which integrates Synopsys DesignWare QoS features. It enables
high-speed networking with DMA acceleration and is optimized
for embedded systems.
config DWMAC_INGENIC
tristate "Ingenic MAC support"
default MACH_INGENIC

1
drivers/net/ethernet/stmicro/stmmac/Makefile
View File

@@ -14,6 +14,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
# Ordering matters. Generic driver must be last.
obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
obj-$(CONFIG_DWMAC_ANARION) += dwmac-anarion.o
obj-$(CONFIG_DWMAC_EIC7700) += dwmac-eic7700.o
obj-$(CONFIG_DWMAC_INGENIC) += dwmac-ingenic.o
obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o
obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o

235
drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c Normal file
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@@ -0,0 +1,235 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Eswin DWC Ethernet linux driver
*
* Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.
*
* Authors:
* Zhi Li <lizhi2@eswincomputing.com>
* Shuang Liang <liangshuang@eswincomputing.com>
* Shangjuan Wei <weishangjuan@eswincomputing.com>
*/
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <linux/pm_runtime.h>
#include <linux/stmmac.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include "stmmac_platform.h"
/* eth_phy_ctrl_offset eth0:0x100 */
#define EIC7700_ETH_TX_CLK_SEL BIT(16)
#define EIC7700_ETH_PHY_INTF_SELI BIT(0)
/* eth_axi_lp_ctrl_offset eth0:0x108 */
#define EIC7700_ETH_CSYSREQ_VAL BIT(0)
/*
* TX/RX Clock Delay Bit Masks:
* - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit)
* - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit)
*/
#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8)
#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24)
#define EIC7700_MAX_DELAY_UNIT 0x7F
static const char * const eic7700_clk_names[] = {
"tx", "axi", "cfg",
};
struct eic7700_qos_priv {
struct plat_stmmacenet_data *plat_dat;
};
static int eic7700_clks_config(void *priv, bool enabled)
{
struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv;
struct plat_stmmacenet_data *plat = dwc->plat_dat;
int ret = 0;
if (enabled)
ret = clk_bulk_prepare_enable(plat->num_clks, plat->clks);
else
clk_bulk_disable_unprepare(plat->num_clks, plat->clks);
return ret;
}
static int eic7700_dwmac_init(struct platform_device *pdev, void *priv)
{
struct eic7700_qos_priv *dwc = priv;
return eic7700_clks_config(dwc, true);
}
static void eic7700_dwmac_exit(struct platform_device *pdev, void *priv)
{
struct eic7700_qos_priv *dwc = priv;
eic7700_clks_config(dwc, false);
}
static int eic7700_dwmac_suspend(struct device *dev, void *priv)
{
return pm_runtime_force_suspend(dev);
}
static int eic7700_dwmac_resume(struct device *dev, void *priv)
{
int ret;
ret = pm_runtime_force_resume(dev);
if (ret)
dev_err(dev, "%s failed: %d\n", __func__, ret);
return ret;
}
static int eic7700_dwmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat_dat;
struct stmmac_resources stmmac_res;
struct eic7700_qos_priv *dwc_priv;
struct regmap *eic7700_hsp_regmap;
u32 eth_axi_lp_ctrl_offset;
u32 eth_phy_ctrl_offset;
u32 eth_phy_ctrl_regset;
u32 eth_rxd_dly_offset;
u32 eth_dly_param = 0;
u32 delay_ps;
int i, ret;
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"failed to get resources\n");
plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
if (IS_ERR(plat_dat))
return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
"dt configuration failed\n");
dwc_priv = devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL);
if (!dwc_priv)
return -ENOMEM;
/* Read rx-internal-delay-ps and update rx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"rx-internal-delay-ps", &delay_ps)) {
u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
eth_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
eth_dly_param |= FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
} else {
return dev_err_probe(&pdev->dev, -EINVAL,
"missing required property rx-internal-delay-ps\n");
}
/* Read tx-internal-delay-ps and update tx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"tx-internal-delay-ps", &delay_ps)) {
u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
eth_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
eth_dly_param |= FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
} else {
return dev_err_probe(&pdev->dev, -EINVAL,
"missing required property tx-internal-delay-ps\n");
}
eic7700_hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"eswin,hsp-sp-csr");
if (IS_ERR(eic7700_hsp_regmap))
return dev_err_probe(&pdev->dev,
PTR_ERR(eic7700_hsp_regmap),
"Failed to get hsp-sp-csr regmap\n");
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
1, &eth_phy_ctrl_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_phy_ctrl_offset\n");
regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset,
&eth_phy_ctrl_regset);
eth_phy_ctrl_regset |=
(EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI);
regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset,
eth_phy_ctrl_regset);
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
2, &eth_axi_lp_ctrl_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_axi_lp_ctrl_offset\n");
regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset,
EIC7700_ETH_CSYSREQ_VAL);
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
3, &eth_rxd_dly_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_rxd_dly_offset\n");
regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset,
eth_dly_param);
plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
plat_dat->clks = devm_kcalloc(&pdev->dev,
plat_dat->num_clks,
sizeof(*plat_dat->clks),
GFP_KERNEL);
if (!plat_dat->clks)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(eic7700_clk_names); i++)
plat_dat->clks[i].id = eic7700_clk_names[i];
ret = devm_clk_bulk_get_optional(&pdev->dev,
plat_dat->num_clks,
plat_dat->clks);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Failed to get clocks\n");
plat_dat->clk_tx_i = stmmac_pltfr_find_clk(plat_dat, "tx");
plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
plat_dat->clks_config = eic7700_clks_config;
plat_dat->bsp_priv = dwc_priv;
dwc_priv->plat_dat = plat_dat;
plat_dat->init = eic7700_dwmac_init;
plat_dat->exit = eic7700_dwmac_exit;
plat_dat->suspend = eic7700_dwmac_suspend;
plat_dat->resume = eic7700_dwmac_resume;
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
}
static const struct of_device_id eic7700_dwmac_match[] = {
{ .compatible = "eswin,eic7700-qos-eth" },
{ }
};
MODULE_DEVICE_TABLE(of, eic7700_dwmac_match);
static struct platform_driver eic7700_dwmac_driver = {
.probe = eic7700_dwmac_probe,
.driver = {
.name = "eic7700-eth-dwmac",
.pm = &stmmac_pltfr_pm_ops,
.of_match_table = eic7700_dwmac_match,
},
};
module_platform_driver(eic7700_dwmac_driver);
MODULE_AUTHOR("Zhi Li <lizhi2@eswincomputing.com>");
MODULE_AUTHOR("Shuang Liang <liangshuang@eswincomputing.com>");
MODULE_AUTHOR("Shangjuan Wei <weishangjuan@eswincomputing.com>");
MODULE_DESCRIPTION("Eswin eic7700 qos ethernet driver");
MODULE_LICENSE("GPL");