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gpiolib: add support to register sparse pin range

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Add support to register for GPIO<->pin mapping using a list of non
consecutive pins. The core already supports sparse pin range (pins member
of struct pinctrl_gpio_range), but it was not possible to register one. If
pins is not NULL the core uses it, otherwise it assumes that a consecutive
pin range was registered and it uses pin_base.

The function gpiochip_add_pin_range() which allocates and fills the struct
pinctrl_gpio_range was renamed to gpiochip_add_pin_range_with_pins() and
the pins parameter was added.

Two new functions were added, gpiochip_add_pin_range() and
gpiochip_add_sparse_pin_range() to register a consecutive or sparse pins
range. Both use gpiochip_add_pin_range_with_pins().

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20250811-aaeon-up-board-pinctrl-support-v9-1-29f0cbbdfb30@bootlin.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Thomas Richard
2025-08-11 15:25:44 +02:00
committed by Bartosz Golaszewski
parent 8f5ae30d69
commit 181fe022ec
2 changed files with 68 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpio/gpiolib.c
View File

@@ -2349,11 +2349,13 @@ int gpiochip_add_pingroup_range(struct gpio_chip *gc,
EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
/**
* gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping
* gpiochip_add_pin_range_with_pins() - add a range for GPIO <-> pin mapping
* @gc: the gpiochip to add the range for
* @pinctl_name: the dev_name() of the pin controller to map to
* @gpio_offset: the start offset in the current gpio_chip number space
* @pin_offset: the start offset in the pin controller number space
* @pins: the list of non consecutive pins to accumulate in this range (if not
* NULL, pin_offset is ignored by pinctrl core)
* @npins: the number of pins from the offset of each pin space (GPIO and
* pin controller) to accumulate in this range
*
@@ -2365,9 +2367,12 @@ EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
* Returns:
* 0 on success, or a negative errno on failure.
*/
int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
unsigned int gpio_offset, unsigned int pin_offset,
unsigned int npins)
int gpiochip_add_pin_range_with_pins(struct gpio_chip *gc,
const char *pinctl_name,
unsigned int gpio_offset,
unsigned int pin_offset,
unsigned int const *pins,
unsigned int npins)
{
struct gpio_pin_range *pin_range;
struct gpio_device *gdev = gc->gpiodev;
@@ -2385,6 +2390,7 @@ int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
pin_range->range.name = gc->label;
pin_range->range.base = gdev->base + gpio_offset;
pin_range->range.pin_base = pin_offset;
pin_range->range.pins = pins;
pin_range->range.npins = npins;
pin_range->pctldev = pinctrl_find_and_add_gpio_range(pinctl_name,
&pin_range->range);
@@ -2394,16 +2400,21 @@ int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
kfree(pin_range);
return ret;
}
chip_dbg(gc, "created GPIO range %d->%d ==> %s PIN %d->%d\n",
gpio_offset, gpio_offset + npins - 1,
pinctl_name,
pin_offset, pin_offset + npins - 1);
if (pin_range->range.pins)
chip_dbg(gc, "created GPIO range %d->%d ==> %s %d sparse PIN range { %d, ... }",
gpio_offset, gpio_offset + npins - 1,
pinctl_name, npins, pins[0]);
else
chip_dbg(gc, "created GPIO range %d->%d ==> %s PIN %d->%d\n",
gpio_offset, gpio_offset + npins - 1,
pinctl_name,
pin_offset, pin_offset + npins - 1);
list_add_tail(&pin_range->node, &gdev->pin_ranges);
return 0;
}
EXPORT_SYMBOL_GPL(gpiochip_add_pin_range);
EXPORT_SYMBOL_GPL(gpiochip_add_pin_range_with_pins);
/**
* gpiochip_remove_pin_ranges() - remove all the GPIO <-> pin mappings

51
include/linux/gpio/driver.h
View File

@@ -772,16 +772,50 @@ struct gpio_pin_range {
#ifdef CONFIG_PINCTRL
int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
unsigned int gpio_offset, unsigned int pin_offset,
unsigned int npins);
int gpiochip_add_pin_range_with_pins(struct gpio_chip *gc,
const char *pinctl_name,
unsigned int gpio_offset,
unsigned int pin_offset,
unsigned int const *pins,
unsigned int npins);
int gpiochip_add_pingroup_range(struct gpio_chip *gc,
struct pinctrl_dev *pctldev,
unsigned int gpio_offset, const char *pin_group);
void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
static inline int
gpiochip_add_pin_range(struct gpio_chip *gc,
const char *pinctl_name,
unsigned int gpio_offset,
unsigned int pin_offset,
unsigned int npins)
{
return gpiochip_add_pin_range_with_pins(gc, pinctl_name, gpio_offset,
pin_offset, NULL, npins);
}
static inline int
gpiochip_add_sparse_pin_range(struct gpio_chip *gc,
const char *pinctl_name,
unsigned int gpio_offset,
unsigned int const *pins,
unsigned int npins)
{
return gpiochip_add_pin_range_with_pins(gc, pinctl_name, gpio_offset, 0,
pins, npins);
}
#else /* ! CONFIG_PINCTRL */
static inline int
gpiochip_add_pin_range_with_pins(struct gpio_chip *gc,
const char *pinctl_name,
unsigned int gpio_offset,
unsigned int pin_offset,
unsigned int npins)
{
return 0;
}
static inline int
gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
unsigned int gpio_offset, unsigned int pin_offset,
@@ -789,6 +823,17 @@ gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
{
return 0;
}
static inline int
gpiochip_add_sparse_pin_range(struct gpio_chip *gc,
const char *pinctl_name,
unsigned int gpio_offset,
unsigned int const *pins,
unsigned int npins)
{
return 0;
}
static inline int
gpiochip_add_pingroup_range(struct gpio_chip *gc,
struct pinctrl_dev *pctldev,