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Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

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Pull MIPS updates from Thomas Bogendoerfer:

 - Add support for multi-cluster configuration

 - Add quirks for enabling multi-cluster mode on EyeQ6

 - Add DTS clocks for ralink

 - Cleanup realtek DTS

 - Other cleanups and fixes

* tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (35 commits)
  MIPS: config: omega2+, vocore2: enable CLK_MTMIPS
  arch: mips: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX
  MIPS: cm: Fix warning if MIPS_CM is disabled
  MIPS: Fix Macro name
  MIPS: ds1287: Match ds1287_set_base_clock() function types
  MIPS: cevt-ds1287: Add missing ds1287.h include
  MIPS: dec: Declare which_prom() as static
  MIPS: Loongson2ef: Replace deprecated strncpy() with strscpy()
  mips: dts: ralink: mt7628a: update system controller node and its consumers
  mips: dts: ralink: mt7620a: update system controller node and its consumers
  mips: dts: ralink: rt3883: update system controller node and its consumers
  mips: dts: ralink: rt3050: update system controller node and its consumers
  mips: dts: ralink: rt2880: update system controller node and its consumers
  dt-bindings: clock: add clock definitions for Ralink SoCs
  MIPS: Use arch specific syscall name match function
  mips: dts: realtek: Add restart to Cisco SG220-26P
  mips: dts: realtek: Add RTL838x SoC peripherals
  mips: dts: realtek: Replace uart clock property
  mips: dts: realtek: Correct uart interrupt-parent
  mips: dts: realtek: Add SoC IRQ node for RTL838x
  ...
This commit is contained in:
Linus Torvalds
2025-03-29 12:47:09 -07:00
parent f90f2145b2 855912be0b
commit 1c83601b8f
51 changed files with 843 additions and 242 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
View File

@@ -18,6 +18,12 @@ description: |
These SoCs have an XTAL from where the cpu clock is
provided as well as derived clocks for the bus and the peripherals.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifiers could be found in:
[1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
properties:
compatible:
items:
@@ -38,7 +44,8 @@ properties:
'#clock-cells':
description:
The first cell indicates the clock number.
The first cell indicates the clock number, see [1] for available
clocks.
const: 1
'#reset-cells':
@@ -56,6 +63,8 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
syscon@0 {
compatible = "ralink,rt5350-sysc", "syscon";
reg = <0x0 0x100>;

57
Documentation/devicetree/bindings/mips/mti,mips-cm.yaml Normal file
View File

@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Coherence Manager
description:
The Coherence Manager (CM) is responsible for establishing the
global ordering of requests from all elements of the system and
sending the correct data back to the requester. It supports Cache
to Cache transfers.
https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf
https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf
maintainers:
- Jiaxun Yang <jiaxun.yang@flygoat.com>
properties:
compatible:
oneOf:
- const: mti,mips-cm
- const: mobileye,eyeq6-cm
description:
On EyeQ6 the HCI (Hardware Cache Initialization) information for
the L2 cache in multi-cluster configuration is broken.
reg:
description:
Base address and size of the Global Configuration Registers
referred to as CMGCR.They are the system programmer's interface
to the Coherency Manager. Their location in the memory map is
determined at core build time. In a functional system, the base
address is provided by the Coprocessor 0, but some
System-on-Chip (SoC) designs may not provide an accurate address
that needs to be described statically.
maxItems: 1
required:
- compatible
additionalProperties: false
examples:
- |
coherency-manager@1fbf8000 {
compatible = "mti,mips-cm";
reg = <0x1bde8000 0x8000>;
};
- |
coherency-manager {
compatible = "mobileye,eyeq6-cm";
};
...

2
arch/mips/boot/dts/ingenic/gcw0.dts
View File

@@ -91,7 +91,7 @@
"MIC1N", "Built-in Mic";
simple-audio-card,pin-switches = "Speaker", "Headphones";
simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_LOW>;
simple-audio-card,hp-det-gpios = <&gpf 21 GPIO_ACTIVE_LOW>;
simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>;
simple-audio-card,bitclock-master = <&dai_codec>;

2
arch/mips/boot/dts/ingenic/rs90.dts
View File

@@ -148,7 +148,7 @@
"Speaker", "OUTR";
simple-audio-card,pin-switches = "Speaker";
simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>;
simple-audio-card,hp-det-gpios = <&gpd 16 GPIO_ACTIVE_LOW>;
simple-audio-card,aux-devs = <&amp>;
simple-audio-card,bitclock-master = <&dai_codec>;

4
arch/mips/boot/dts/mobileye/eyeq6h.dtsi
View File

@@ -32,6 +32,10 @@
#interrupt-cells = <1>;
};
coherency-manager {
compatible = "mobileye,eyeq6-cm";
};
xtal: clock-30000000 {
compatible = "fixed-clock";
#clock-cells = <0>;

2
arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
View File

@@ -5,7 +5,7 @@
/dts-v1/;
/include/ "mt7628a.dtsi"
#include "mt7628a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

10
arch/mips/boot/dts/ralink/mt7620a.dtsi
View File

@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
sysc@0 {
compatible = "ralink,mt7620a-sysc";
sysc: syscon@0 {
compatible = "ralink,mt7620-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysc MT7620_CLK_UARTLITE>;
interrupt-parent = <&intc>;
interrupts = <12>;

2
arch/mips/boot/dts/ralink/mt7620a_eval.dts
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "mt7620a.dtsi"
#include "mt7620a.dtsi"
/ {
compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";

40
arch/mips/boot/dts/ralink/mt7628a.dtsi
View File

@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
/ {
#address-cells = <1>;
@@ -16,11 +17,6 @@
};
};
resetc: reset-controller {
compatible = "ralink,rt2880-reset";
#reset-cells = <1>;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@@ -36,9 +32,11 @@
#address-cells = <1>;
#size-cells = <1>;
sysc: system-controller@0 {
compatible = "ralink,mt7620a-sysc", "syscon";
sysc: syscon@0 {
compatible = "ralink,mt7628-sysc", "syscon";
reg = <0x0 0x60>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pinmux: pinmux@60 {
@@ -138,7 +136,7 @@
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x30>;
resets = <&resetc 8>;
resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
@@ -154,7 +152,7 @@
interrupt-controller;
#interrupt-cells = <1>;
resets = <&resetc 9>;
resets = <&sysc 9>;
reset-names = "intc";
interrupt-parent = <&cpuintc>;
@@ -190,7 +188,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_spi_spi>;
resets = <&resetc 18>;
clocks = <&sysc MT76X8_CLK_SPI1>;
resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
@@ -206,7 +206,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_i2c_i2c>;
resets = <&resetc 16>;
clocks = <&sysc MT76X8_CLK_I2C>;
resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
@@ -222,7 +224,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart0_uart>;
resets = <&resetc 12>;
clocks = <&sysc MT76X8_CLK_UART0>;
resets = <&sysc 12>;
reset-names = "uart0";
interrupt-parent = <&intc>;
@@ -238,7 +242,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart1_uart>;
resets = <&resetc 19>;
clocks = <&sysc MT76X8_CLK_UART1>;
resets = <&sysc 19>;
reset-names = "uart1";
interrupt-parent = <&intc>;
@@ -254,7 +260,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart2_uart>;
resets = <&resetc 20>;
clocks = <&sysc MT76X8_CLK_UART2>;
resets = <&sysc 20>;
reset-names = "uart2";
interrupt-parent = <&intc>;
@@ -271,7 +279,7 @@
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
resets = <&resetc 22 &resetc 25>;
resets = <&sysc 22 &sysc 25>;
reset-names = "host", "device";
};
@@ -290,6 +298,8 @@
compatible = "mediatek,mt7628-wmac";
reg = <0x10300000 0x100000>;
clocks = <&sysc MT76X8_CLK_WMAC>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;

2
arch/mips/boot/dts/ralink/omega2p.dts
View File

@@ -1,6 +1,6 @@
/dts-v1/;
/include/ "mt7628a.dtsi"
#include "mt7628a.dtsi"
/ {
compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc";

10
arch/mips/boot/dts/ralink/rt2880.dtsi
View File

@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
sysc@0 {
compatible = "ralink,rt2880-sysc";
sysc: syscon@0 {
compatible = "ralink,rt2880-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysc RT2880_CLK_UARTLITE>;
interrupt-parent = <&intc>;
interrupts = <8>;

2
arch/mips/boot/dts/ralink/rt2880_eval.dts
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "rt2880.dtsi"
#include "rt2880.dtsi"
/ {
compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";

10
arch/mips/boot/dts/ralink/rt3050.dtsi
View File

@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
sysc@0 {
compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
sysc: syscon@0 {
compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysc RT305X_CLK_UARTLITE>;
interrupt-parent = <&intc>;
interrupts = <12>;

10
arch/mips/boot/dts/ralink/rt3883.dtsi
View File

@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
sysc@0 {
compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
sysc: syscon@0 {
compatible = "ralink,rt3883-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
clocks = <&sysc RT3883_CLK_UARTLITE>;
interrupt-parent = <&intc>;
interrupts = <12>;

2
arch/mips/boot/dts/ralink/rt3883_eval.dts
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "rt3883.dtsi"
#include "rt3883.dtsi"
/ {
compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";

10
arch/mips/boot/dts/realtek/cisco_sg220-26.dts
View File

@@ -2,9 +2,10 @@
/dts-v1/;
#include "rtl83xx.dtsi"
#include "rtl838x.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Cisco SG220-26";
compatible = "cisco,sg220-26", "realtek,rtl8382-soc";
@@ -18,6 +19,13 @@
device_type = "memory";
reg = <0x0 0x8000000>;
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
priority = <192>;
open-source;
};
};
&uart0 {

111
arch/mips/boot/dts/realtek/rtl838x.dtsi
View File

@@ -1,6 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -9,8 +17,7 @@
device_type = "cpu";
compatible = "mips,mips4KEc";
reg = <0>;
clocks = <&baseclk 0>;
clock-names = "cpu";
clocks = <&baseclk>;
};
};
@@ -19,4 +26,104 @@
#clock-cells = <0>;
clock-frequency = <500000000>;
};
cpuintc: cpuintc {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
lx_clk: clock-lexra {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
soc@18000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x18000000 0x10000>;
spi0: spi@1200 {
compatible = "realtek,rtl8380-spi";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
};
uart0: serial@2000 {
compatible = "ns16550a";
reg = <0x2000 0x100>;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <31>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
status = "disabled";
};
uart1: serial@2100 {
compatible = "ns16550a";
reg = <0x2100 0x100>;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <30>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
status = "disabled";
};
intc: interrupt-controller@3000 {
compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
reg = <0x3000 0x20>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>, <4>, <5>, <6>;
};
watchdog: watchdog@3150 {
compatible = "realtek,rtl8380-wdt";
reg = <0x3150 0xc>;
realtek,reset-mode = "soc";
clocks = <&lx_clk>;
timeout-sec = <20>;
interrupt-parent = <&intc>;
interrupt-names = "phase1", "phase2";
interrupts = <19>, <18>;
};
gpio0: gpio@3500 {
compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
reg = <0x3500 0x1c>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <23>;
};
};
};

59
arch/mips/boot/dts/realtek/rtl83xx.dtsi
View File

@@ -1,59 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpuintc: cpuintc {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x18000000 0x10000>;
uart0: serial@2000 {
compatible = "ns16550a";
reg = <0x2000 0x100>;
clock-frequency = <200000000>;
interrupt-parent = <&cpuintc>;
interrupts = <31>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
status = "disabled";
};
uart1: serial@2100 {
compatible = "ns16550a";
reg = <0x2100 0x100>;
clock-frequency = <200000000>;
interrupt-parent = <&cpuintc>;
interrupts = <30>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
status = "disabled";
};
};
};

148
arch/mips/boot/dts/realtek/rtl930x.dtsi
View File

@@ -1,10 +1,23 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
#include "rtl83xx.dtsi"
/ {
compatible = "realtek,rtl9302-soc";
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpuintc: cpuintc {
compatible = "mti,cpu-interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -13,8 +26,7 @@
device_type = "cpu";
compatible = "mips,mips34Kc";
reg = <0>;
clocks = <&baseclk 0>;
clock-names = "cpu";
clocks = <&baseclk>;
};
};
@@ -58,64 +70,84 @@
status = "disabled";
};
};
};
&soc {
ranges = <0x0 0x18000000 0x20000>;
intc: interrupt-controller@3000 {
compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
reg = <0x3000 0x18>, <0x3018 0x18>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
};
spi0: spi@1200 {
compatible = "realtek,rtl8380-spi";
reg = <0x1200 0x100>;
soc: soc@18000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
};
#size-cells = <1>;
ranges = <0x0 0x18000000 0x20000>;
timer0: timer@3200 {
compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
<0x3230 0x10>, <0x3240 0x10>;
intc: interrupt-controller@3000 {
compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
reg = <0x3000 0x18>, <0x3018 0x18>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <7>, <8>, <9>, <10>, <11>;
clocks = <&lx_clk>;
};
interrupt-parent = <&cpuintc>;
interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
};
snand: spi@1a400 {
compatible = "realtek,rtl9301-snand";
reg = <0x1a400 0x44>;
interrupt-parent = <&intc>;
interrupts = <19>;
clocks = <&lx_clk>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
spi0: spi@1200 {
compatible = "realtek,rtl8380-spi";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
};
timer0: timer@3200 {
compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
<0x3230 0x10>, <0x3240 0x10>;
interrupt-parent = <&intc>;
interrupts = <7>, <8>, <9>, <10>, <11>;
clocks = <&lx_clk>;
};
snand: spi@1a400 {
compatible = "realtek,rtl9301-snand";
reg = <0x1a400 0x44>;
interrupt-parent = <&intc>;
interrupts = <19>;
clocks = <&lx_clk>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@2000 {
compatible = "ns16550a";
reg = <0x2000 0x100>;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <30>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
status = "disabled";
};
uart1: serial@2100 {
compatible = "ns16550a";
reg = <0x2100 0x100>;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <31>;
reg-io-width = <1>;
reg-shift = <2>;
fifo-size = <1>;
no-loopback-test;
status = "disabled";
};
};
};
&uart0 {
/delete-property/ clock-frequency;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <30>;
};
&uart1 {
/delete-property/ clock-frequency;
clocks = <&lx_clk>;
interrupt-parent = <&intc>;
interrupts = <31>;
};

1
arch/mips/configs/gpr_defconfig
View File

@@ -116,7 +116,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/ip22_defconfig
View File

@@ -161,7 +161,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/ip27_defconfig
View File

@@ -63,7 +63,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/malta_defconfig
View File

@@ -190,7 +190,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/malta_kvm_defconfig
View File

@@ -194,7 +194,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/malta_qemu_32r6_defconfig
View File

@@ -64,7 +64,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/maltaaprp_defconfig
View File

@@ -66,7 +66,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/maltasmvp_defconfig
View File

@@ -67,7 +67,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/maltasmvp_eva_defconfig
View File

@@ -68,7 +68,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/maltaup_defconfig
View File

@@ -65,7 +65,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/maltaup_xpa_defconfig
View File

@@ -191,7 +191,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/mtx1_defconfig
View File

@@ -162,7 +162,6 @@ CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_INGRESS=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/omega2p_defconfig
View File

@@ -61,6 +61,7 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_MMC=y
CONFIG_CLK_MTMIPS=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
CONFIG_PHY_RALINK_USB=y

1
arch/mips/configs/rb532_defconfig
View File

@@ -77,7 +77,6 @@ CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/rm200_defconfig
View File

@@ -143,7 +143,6 @@ CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m

1
arch/mips/configs/vocore2_defconfig
View File

@@ -61,6 +61,7 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_MMC=y
CONFIG_CLK_MTMIPS=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
CONFIG_PHY_RALINK_USB=y

2
arch/mips/dec/prom/init.c
View File

@@ -42,7 +42,7 @@ int (*__pmax_close)(int);
* Detect which PROM the DECSTATION has, and set the callback vectors
* appropriately.
*/
void __init which_prom(s32 magic, s32 *prom_vec)
static void __init which_prom(s32 magic, s32 *prom_vec)
{
/*
* No sign of the REX PROM's magic number means we assume a non-REX

2
arch/mips/include/asm/ds1287.h
View File

@@ -8,7 +8,7 @@
#define __ASM_DS1287_H
extern int ds1287_timer_state(void);
extern void ds1287_set_base_clock(unsigned int clock);
extern int ds1287_set_base_clock(unsigned int hz);
extern int ds1287_clockevent_init(int irq);
#endif

16
arch/mips/include/asm/ftrace.h
View File

@@ -91,4 +91,20 @@ void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra,
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_FUNCTION_TRACER */
#ifdef CONFIG_FTRACE_SYSCALLS
#ifndef __ASSEMBLY__
/*
* Some syscall entry functions on mips start with "__sys_" (fork and clone,
* for instance). We should also match the sys_ variant with those.
*/
#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
static inline bool arch_syscall_match_sym_name(const char *sym,
const char *name)
{
return !strcmp(sym, name) ||
(!strncmp(sym, "__sys_", 6) && !strcmp(sym + 6, name + 4));
}
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_FTRACE_SYSCALLS */
#endif /* _ASM_MIPS_FTRACE_H */

2
arch/mips/include/asm/mach-rc32434/pci.h
View File

@@ -167,7 +167,7 @@ struct pci_msu {
#define PCI_CFGA_DEV 0x0000f800
#define PCI_CFGA_DEV_INTERN 0
#define PCI_CFGA_BUS_BIT 16
#define PCI CFGA_BUS 0x00ff0000
#define PCI_CFGA_BUS 0x00ff0000
#define PCI_CFGA_BUS_TYPE0 0
#define PCI_CFGA_EN (1 << 31)

40
arch/mips/include/asm/mips-cm.h
View File

@@ -59,6 +59,16 @@ extern phys_addr_t mips_cm_l2sync_phys_base(void);
*/
extern int mips_cm_is64;
/*
* mips_cm_is_l2_hci_broken - determine if HCI is broken
*
* Some CM reports show that Hardware Cache Initialization is
* complete, but in reality it's not the case. They also incorrectly
* indicate that Hardware Cache Initialization is supported. This
* flags allows warning about this broken feature.
*/
extern bool mips_cm_is_l2_hci_broken;
/**
* mips_cm_error_report - Report CM cache errors
*/
@@ -97,6 +107,18 @@ static inline bool mips_cm_present(void)
#endif
}
/**
* mips_cm_update_property - update property from the device tree
*
* Retrieve the properties from the device tree if a CM node exist and
* update the internal variable based on this.
*/
#ifdef CONFIG_MIPS_CM
extern void mips_cm_update_property(void);
#else
static inline void mips_cm_update_property(void) {}
#endif
/**
* mips_cm_has_l2sync - determine whether an L2-only sync region is present
*
@@ -255,6 +277,12 @@ GCR_ACCESSOR_RW(32, 0x130, l2_config)
GCR_ACCESSOR_RO(32, 0x150, sys_config2)
#define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
/* GCR_L2-RAM_CONFIG - Configuration & status of L2 cache RAMs */
GCR_ACCESSOR_RW(64, 0x240, l2_ram_config)
#define CM_GCR_L2_RAM_CONFIG_PRESENT BIT(31)
#define CM_GCR_L2_RAM_CONFIG_HCI_DONE BIT(30)
#define CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED BIT(29)
/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
#define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
@@ -266,6 +294,18 @@ GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
#define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
#define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
/* GCR_L2_TAG_ADDR - Access addresses in L2 cache tags */
GCR_ACCESSOR_RW(64, 0x600, l2_tag_addr)
/* GCR_L2_TAG_STATE - Access L2 cache tag state */
GCR_ACCESSOR_RW(64, 0x608, l2_tag_state)
/* GCR_L2_DATA - Access data in L2 cache lines */
GCR_ACCESSOR_RW(64, 0x610, l2_data)
/* GCR_L2_ECC - Access ECC information from L2 cache lines */
GCR_ACCESSOR_RW(64, 0x618, l2_ecc)
/* GCR_L2SM_COP - L2 cache op state machine control */
GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
#define CM_GCR_L2SM_COP_PRESENT BIT(31)

7
arch/mips/include/asm/smp-cps.h
View File

@@ -22,7 +22,12 @@ struct core_boot_config {
struct vpe_boot_config *vpe_config;
};
extern struct core_boot_config *mips_cps_core_bootcfg;
struct cluster_boot_config {
unsigned long *core_power;
struct core_boot_config *core_config;
};
extern struct cluster_boot_config *mips_cps_cluster_bootcfg;
extern void mips_cps_core_boot(int cca, void __iomem *gcr_base);
extern void mips_cps_core_init(void);

3
arch/mips/kernel/asm-offsets.c
View File

@@ -410,6 +410,9 @@ void output_cps_defines(void)
{
COMMENT(" MIPS CPS offsets. ");
OFFSET(CLUSTERBOOTCFG_CORECONFIG, cluster_boot_config, core_config);
DEFINE(CLUSTERBOOTCFG_SIZE, sizeof(struct cluster_boot_config));
OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));

1
arch/mips/kernel/cevt-ds1287.c
View File

@@ -10,6 +10,7 @@
#include <linux/mc146818rtc.h>
#include <linux/irq.h>
#include <asm/ds1287.h>
#include <asm/time.h>
int ds1287_timer_state(void)

19
arch/mips/kernel/cps-vec.S
View File

@@ -19,6 +19,10 @@
#define GCR_CPC_BASE_OFS 0x0088
#define GCR_CL_COHERENCE_OFS 0x2008
#define GCR_CL_ID_OFS 0x2028
#define CM3_GCR_Cx_ID_CLUSTER_SHF 8
#define CM3_GCR_Cx_ID_CLUSTER_MSK (0xff << 8)
#define CM3_GCR_Cx_ID_CORENUM_SHF 0
#define CM3_GCR_Cx_ID_CORENUM_MSK (0xff << 0)
#define CPC_CL_VC_STOP_OFS 0x2020
#define CPC_CL_VC_RUN_OFS 0x2028
@@ -271,12 +275,21 @@ LEAF(mips_cps_core_init)
*/
LEAF(mips_cps_get_bootcfg)
/* Calculate a pointer to this cores struct core_boot_config */
PTR_LA v0, mips_cps_cluster_bootcfg
PTR_L v0, 0(v0)
lw t0, GCR_CL_ID_OFS(s1)
#ifdef CONFIG_CPU_MIPSR6
ext t1, t0, CM3_GCR_Cx_ID_CLUSTER_SHF, 8
li t2, CLUSTERBOOTCFG_SIZE
mul t1, t1, t2
PTR_ADDU \
v0, v0, t1
#endif
PTR_L v0, CLUSTERBOOTCFG_CORECONFIG(v0)
andi t0, t0, CM3_GCR_Cx_ID_CORENUM_MSK
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
PTR_LA t1, mips_cps_core_bootcfg
PTR_L t1, 0(t1)
PTR_ADDU v0, t0, t1
PTR_ADDU v0, v0, t0
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
li t9, 0

18
arch/mips/kernel/mips-cm.c
View File

@@ -5,6 +5,7 @@
*/
#include <linux/errno.h>
#include <linux/of.h>
#include <linux/percpu.h>
#include <linux/spinlock.h>
@@ -14,6 +15,7 @@
void __iomem *mips_gcr_base;
void __iomem *mips_cm_l2sync_base;
int mips_cm_is64;
bool mips_cm_is_l2_hci_broken;
static char *cm2_tr[8] = {
"mem", "gcr", "gic", "mmio",
@@ -237,6 +239,18 @@ static void mips_cm_probe_l2sync(void)
mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE);
}
void mips_cm_update_property(void)
{
struct device_node *cm_node;
cm_node = of_find_compatible_node(of_root, NULL, "mobileye,eyeq6-cm");
if (!cm_node)
return;
pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken");
mips_cm_is_l2_hci_broken = true;
of_node_put(cm_node);
}
int mips_cm_probe(void)
{
phys_addr_t addr;
@@ -308,7 +322,9 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core,
FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp);
if (cm_rev >= CM_REV_CM3_5) {
val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
if (cluster != cpu_cluster(&current_cpu_data))
val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
val |= CM_GCR_Cx_OTHER_GIC_EN;
val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster);
val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block);
} else {

35
arch/mips/kernel/pm-cps.c
View File

@@ -57,10 +57,7 @@ static DEFINE_PER_CPU_ALIGNED(u32*, ready_count);
/* Indicates online CPUs coupled with the current CPU */
static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled);
/*
* Used to synchronize entry to deep idle states. Actually per-core rather
* than per-CPU.
*/
/* Used to synchronize entry to deep idle states */
static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier);
/* Saved CPU state across the CPS_PM_POWER_GATED state */
@@ -104,17 +101,20 @@ static void coupled_barrier(atomic_t *a, unsigned online)
int cps_pm_enter_state(enum cps_pm_state state)
{
unsigned cpu = smp_processor_id();
unsigned int cluster = cpu_cluster(&current_cpu_data);
unsigned core = cpu_core(&current_cpu_data);
unsigned online, left;
cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
u32 *core_ready_count, *nc_core_ready_count;
void *nc_addr;
cps_nc_entry_fn entry;
struct cluster_boot_config *cluster_cfg;
struct core_boot_config *core_cfg;
struct vpe_boot_config *vpe_cfg;
atomic_t *barrier;
/* Check that there is an entry function for this state */
entry = per_cpu(nc_asm_enter, core)[state];
entry = per_cpu(nc_asm_enter, cpu)[state];
if (!entry)
return -EINVAL;
@@ -138,7 +138,8 @@ int cps_pm_enter_state(enum cps_pm_state state)
if (!mips_cps_smp_in_use())
return -EINVAL;
core_cfg = &mips_cps_core_bootcfg[core];
cluster_cfg = &mips_cps_cluster_bootcfg[cluster];
core_cfg = &cluster_cfg->core_config[core];
vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(&current_cpu_data)];
vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;
vpe_cfg->gp = (unsigned long)current_thread_info();
@@ -150,7 +151,7 @@ int cps_pm_enter_state(enum cps_pm_state state)
smp_mb__after_atomic();
/* Create a non-coherent mapping of the core ready_count */
core_ready_count = per_cpu(ready_count, core);
core_ready_count = per_cpu(ready_count, cpu);
nc_addr = kmap_noncoherent(virt_to_page(core_ready_count),
(unsigned long)core_ready_count);
nc_addr += ((unsigned long)core_ready_count & ~PAGE_MASK);
@@ -158,7 +159,8 @@ int cps_pm_enter_state(enum cps_pm_state state)
/* Ensure ready_count is zero-initialised before the assembly runs */
WRITE_ONCE(*nc_core_ready_count, 0);
coupled_barrier(&per_cpu(pm_barrier, core), online);
barrier = &per_cpu(pm_barrier, cpumask_first(&cpu_sibling_map[cpu]));
coupled_barrier(barrier, online);
/* Run the generated entry code */
left = entry(online, nc_core_ready_count);
@@ -629,12 +631,14 @@ out_err:
static int cps_pm_online_cpu(unsigned int cpu)
{
enum cps_pm_state state;
unsigned core = cpu_core(&cpu_data[cpu]);
unsigned int sibling, core;
void *entry_fn, *core_rc;
enum cps_pm_state state;
core = cpu_core(&cpu_data[cpu]);
for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
if (per_cpu(nc_asm_enter, core)[state])
if (per_cpu(nc_asm_enter, cpu)[state])
continue;
if (!test_bit(state, state_support))
continue;
@@ -646,16 +650,19 @@ static int cps_pm_online_cpu(unsigned int cpu)
clear_bit(state, state_support);
}
per_cpu(nc_asm_enter, core)[state] = entry_fn;
for_each_cpu(sibling, &cpu_sibling_map[cpu])
per_cpu(nc_asm_enter, sibling)[state] = entry_fn;
}
if (!per_cpu(ready_count, core)) {
if (!per_cpu(ready_count, cpu)) {
core_rc = kmalloc(sizeof(u32), GFP_KERNEL);
if (!core_rc) {
pr_err("Failed allocate core %u ready_count\n", core);
return -ENOMEM;
}
per_cpu(ready_count, core) = core_rc;
for_each_cpu(sibling, &cpu_sibling_map[cpu])
per_cpu(ready_count, sibling) = core_rc;
}
return 0;

290
arch/mips/kernel/smp-cps.c
View File

@@ -36,11 +36,55 @@ enum label_id {
UASM_L_LA(_not_nmi)
static DECLARE_BITMAP(core_power, NR_CPUS);
static u64 core_entry_reg;
static phys_addr_t cps_vec_pa;
struct core_boot_config *mips_cps_core_bootcfg;
struct cluster_boot_config *mips_cps_cluster_bootcfg;
static void power_up_other_cluster(unsigned int cluster)
{
u32 stat, seq_state;
unsigned int timeout;
mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0,
CM_GCR_Cx_OTHER_BLOCK_LOCAL);
stat = read_cpc_co_stat_conf();
mips_cm_unlock_other();
seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5)
return;
/* Set endianness & power up the CM */
mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN));
write_cpc_redir_pwrup_ctl(1);
mips_cm_unlock_other();
/* Wait for the CM to start up */
timeout = 1000;
mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0,
CM_GCR_Cx_OTHER_BLOCK_LOCAL);
while (1) {
stat = read_cpc_co_stat_conf();
seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5)
break;
if (timeout) {
mdelay(1);
timeout--;
} else {
pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n",
cluster, stat);
mdelay(1000);
}
}
mips_cm_unlock_other();
}
static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
{
@@ -178,6 +222,9 @@ static void __init cps_smp_setup(void)
pr_cont(",");
pr_cont("{");
if (mips_cm_revision() >= CM_REV_CM3_5)
power_up_other_cluster(cl);
ncores = mips_cps_numcores(cl);
for (c = 0; c < ncores; c++) {
core_vpes = core_vpe_count(cl, c);
@@ -205,8 +252,8 @@ static void __init cps_smp_setup(void)
/* Indicate present CPUs (CPU being synonymous with VPE) */
for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
set_cpu_possible(v, true);
set_cpu_present(v, true);
__cpu_number_map[v] = v;
__cpu_logical_map[v] = v;
}
@@ -214,9 +261,6 @@ static void __init cps_smp_setup(void)
/* Set a coherent default CCA (CWB) */
change_c0_config(CONF_CM_CMASK, 0x5);
/* Core 0 is powered up (we're running on it) */
bitmap_set(core_power, 0, 1);
/* Initialise core 0 */
mips_cps_core_init();
@@ -238,8 +282,10 @@ static void __init cps_smp_setup(void)
static void __init cps_prepare_cpus(unsigned int max_cpus)
{
unsigned ncores, core_vpes, c, cca;
unsigned int nclusters, ncores, core_vpes, c, cl, cca;
bool cca_unsuitable, cores_limited;
struct cluster_boot_config *cluster_bootcfg;
struct core_boot_config *core_bootcfg;
mips_mt_set_cpuoptions();
@@ -281,40 +327,62 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
setup_cps_vecs();
/* Allocate core boot configuration structs */
ncores = mips_cps_numcores(0);
mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
GFP_KERNEL);
if (!mips_cps_core_bootcfg) {
pr_err("Failed to allocate boot config for %u cores\n", ncores);
goto err_out;
}
/* Allocate cluster boot configuration structs */
nclusters = mips_cps_numclusters();
mips_cps_cluster_bootcfg = kcalloc(nclusters,
sizeof(*mips_cps_cluster_bootcfg),
GFP_KERNEL);
/* Allocate VPE boot configuration structs */
for (c = 0; c < ncores; c++) {
core_vpes = core_vpe_count(0, c);
mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
sizeof(*mips_cps_core_bootcfg[c].vpe_config),
GFP_KERNEL);
if (!mips_cps_core_bootcfg[c].vpe_config) {
pr_err("Failed to allocate %u VPE boot configs\n",
core_vpes);
if (nclusters > 1)
mips_cm_update_property();
for (cl = 0; cl < nclusters; cl++) {
/* Allocate core boot configuration structs */
ncores = mips_cps_numcores(cl);
core_bootcfg = kcalloc(ncores, sizeof(*core_bootcfg),
GFP_KERNEL);
if (!core_bootcfg)
goto err_out;
mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg;
mips_cps_cluster_bootcfg[cl].core_power =
kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long),
GFP_KERNEL);
/* Allocate VPE boot configuration structs */
for (c = 0; c < ncores; c++) {
core_vpes = core_vpe_count(cl, c);
core_bootcfg[c].vpe_config = kcalloc(core_vpes,
sizeof(*core_bootcfg[c].vpe_config),
GFP_KERNEL);
if (!core_bootcfg[c].vpe_config)
goto err_out;
}
}
/* Mark this CPU as booted */
atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask,
1 << cpu_vpe_id(&current_cpu_data));
/* Mark this CPU as powered up & booted */
cl = cpu_cluster(&current_cpu_data);
c = cpu_core(&current_cpu_data);
cluster_bootcfg = &mips_cps_cluster_bootcfg[cl];
core_bootcfg = &cluster_bootcfg->core_config[c];
bitmap_set(cluster_bootcfg->core_power, cpu_core(&current_cpu_data), 1);
atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(&current_cpu_data));
return;
err_out:
/* Clean up allocations */
if (mips_cps_core_bootcfg) {
for (c = 0; c < ncores; c++)
kfree(mips_cps_core_bootcfg[c].vpe_config);
kfree(mips_cps_core_bootcfg);
mips_cps_core_bootcfg = NULL;
if (mips_cps_cluster_bootcfg) {
for (cl = 0; cl < nclusters; cl++) {
cluster_bootcfg = &mips_cps_cluster_bootcfg[cl];
ncores = mips_cps_numcores(cl);
for (c = 0; c < ncores; c++) {
core_bootcfg = &cluster_bootcfg->core_config[c];
kfree(core_bootcfg->vpe_config);
}
kfree(mips_cps_cluster_bootcfg[c].core_config);
}
kfree(mips_cps_cluster_bootcfg);
mips_cps_cluster_bootcfg = NULL;
}
/* Effectively disable SMP by declaring CPUs not present */
@@ -325,13 +393,118 @@ err_out:
}
}
static void boot_core(unsigned int core, unsigned int vpe_id)
static void init_cluster_l2(void)
{
u32 stat, seq_state;
unsigned timeout;
u32 l2_cfg, l2sm_cop, result;
while (!mips_cm_is_l2_hci_broken) {
l2_cfg = read_gcr_redir_l2_ram_config();
/* If HCI is not supported, use the state machine below */
if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT))
break;
if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED))
break;
/* If the HCI_DONE bit is set, we're finished */
if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE)
return;
}
l2sm_cop = read_gcr_redir_l2sm_cop();
if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT),
"L2 init not supported on this system yet"))
return;
/* Clear L2 tag registers */
write_gcr_redir_l2_tag_state(0);
write_gcr_redir_l2_ecc(0);
/* Ensure the L2 tag writes complete before the state machine starts */
mb();
/* Wait for the L2 state machine to be idle */
do {
l2sm_cop = read_gcr_redir_l2sm_cop();
} while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING);
/* Start a store tag operation */
l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG;
l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE);
l2sm_cop |= CM_GCR_L2SM_COP_CMD_START;
write_gcr_redir_l2sm_cop(l2sm_cop);
/* Ensure the state machine starts before we poll for completion */
mb();
/* Wait for the operation to be complete */
do {
l2sm_cop = read_gcr_redir_l2sm_cop();
result = l2sm_cop & CM_GCR_L2SM_COP_RESULT;
result >>= __ffs(CM_GCR_L2SM_COP_RESULT);
} while (!result);
WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK,
"L2 state machine failed cache init with error %u\n", result);
}
static void boot_core(unsigned int cluster, unsigned int core,
unsigned int vpe_id)
{
struct cluster_boot_config *cluster_cfg;
u32 access, stat, seq_state;
unsigned int timeout, ncores;
cluster_cfg = &mips_cps_cluster_bootcfg[cluster];
ncores = mips_cps_numcores(cluster);
if ((cluster != cpu_cluster(&current_cpu_data)) &&
bitmap_empty(cluster_cfg->core_power, ncores)) {
power_up_other_cluster(cluster);
mips_cm_lock_other(cluster, core, 0,
CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
/* Ensure cluster GCRs are where we expect */
write_gcr_redir_base(read_gcr_base());
write_gcr_redir_cpc_base(read_gcr_cpc_base());
write_gcr_redir_gic_base(read_gcr_gic_base());
init_cluster_l2();
/* Mirror L2 configuration */
write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base());
write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control());
write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b());
/* Mirror ECC/parity setup */
write_gcr_redir_err_control(read_gcr_err_control());
/* Set BEV base */
write_gcr_redir_bev_base(core_entry_reg);
mips_cm_unlock_other();
}
if (cluster != cpu_cluster(&current_cpu_data)) {
mips_cm_lock_other(cluster, core, 0,
CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
/* Ensure the core can access the GCRs */
access = read_gcr_redir_access();
access |= BIT(core);
write_gcr_redir_access(access);
mips_cm_unlock_other();
} else {
/* Ensure the core can access the GCRs */
access = read_gcr_access();
access |= BIT(core);
write_gcr_access(access);
}
/* Select the appropriate core */
mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
/* Set its reset vector */
if (mips_cm_is64)
@@ -400,30 +573,42 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
mips_cm_unlock_other();
/* The core is now powered up */
bitmap_set(core_power, core, 1);
bitmap_set(cluster_cfg->core_power, core, 1);
/*
* Restore CM_PWRUP=0 so that the CM can power down if all the cores in
* the cluster do (eg. if they're all removed via hotplug.
*/
if (mips_cm_revision() >= CM_REV_CM3_5) {
mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
write_cpc_redir_pwrup_ctl(0);
mips_cm_unlock_other();
}
}
static void remote_vpe_boot(void *dummy)
{
unsigned int cluster = cpu_cluster(&current_cpu_data);
unsigned core = cpu_core(&current_cpu_data);
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
struct cluster_boot_config *cluster_cfg =
&mips_cps_cluster_bootcfg[cluster];
struct core_boot_config *core_cfg = &cluster_cfg->core_config[core];
mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
}
static int cps_boot_secondary(int cpu, struct task_struct *idle)
{
unsigned int cluster = cpu_cluster(&cpu_data[cpu]);
unsigned core = cpu_core(&cpu_data[cpu]);
unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
struct cluster_boot_config *cluster_cfg =
&mips_cps_cluster_bootcfg[cluster];
struct core_boot_config *core_cfg = &cluster_cfg->core_config[core];
struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
unsigned int remote;
int err;
/* We don't yet support booting CPUs in other clusters */
if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
return -ENOSYS;
vpe_cfg->pc = (unsigned long)&smp_bootstrap;
vpe_cfg->sp = __KSTK_TOS(idle);
vpe_cfg->gp = (unsigned long)task_thread_info(idle);
@@ -432,14 +617,15 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
preempt_disable();
if (!test_bit(core, core_power)) {
if (!test_bit(core, cluster_cfg->core_power)) {
/* Boot a VPE on a powered down core */
boot_core(core, vpe_id);
boot_core(cluster, core, vpe_id);
goto out;
}
if (cpu_has_vp) {
mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
mips_cm_lock_other(cluster, core, vpe_id,
CM_GCR_Cx_OTHER_BLOCK_LOCAL);
if (mips_cm_is64)
write_gcr_co_reset64_base(core_entry_reg);
else
@@ -576,12 +762,14 @@ static void cps_kexec_nonboot_cpu(void)
static int cps_cpu_disable(void)
{
unsigned cpu = smp_processor_id();
struct cluster_boot_config *cluster_cfg;
struct core_boot_config *core_cfg;
if (!cps_pm_support_state(CPS_PM_POWER_GATED))
return -EINVAL;
core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)];
cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(&current_cpu_data)];
core_cfg = &cluster_cfg->core_config[cpu_core(&current_cpu_data)];
atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
smp_mb__after_atomic();
set_cpu_online(cpu, false);
@@ -647,11 +835,15 @@ static void cps_cpu_die(unsigned int cpu) { }
static void cps_cleanup_dead_cpu(unsigned cpu)
{
unsigned int cluster = cpu_cluster(&cpu_data[cpu]);
unsigned core = cpu_core(&cpu_data[cpu]);
unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
ktime_t fail_time;
unsigned stat;
int err;
struct cluster_boot_config *cluster_cfg;
cluster_cfg = &mips_cps_cluster_bootcfg[cluster];
/*
* Now wait for the CPU to actually offline. Without doing this that
@@ -703,7 +895,7 @@ static void cps_cleanup_dead_cpu(unsigned cpu)
} while (1);
/* Indicate the core is powered off */
bitmap_clear(core_power, core, 1);
bitmap_clear(cluster_cfg->core_power, core, 1);
} else if (cpu_has_mipsmt) {
/*
* Have a CPU with access to the offlined CPUs registers wait

3
arch/mips/loongson2ef/common/machtype.c
View File

@@ -48,8 +48,7 @@ void __init prom_init_machtype(void)
return;
}
p += strlen("machtype=");
strncpy(str, p, MACHTYPE_LEN);
str[MACHTYPE_LEN] = '\0';
strscpy(str, p);
p = strstr(str, " ");
if (p)
*p = '\0';

1
arch/mips/sni/setup.c
View File

@@ -12,7 +12,6 @@
#include <linux/init.h>
#include <linux/export.h>
#include <linux/console.h>
#include <linux/fb.h>
#include <linux/screen_info.h>
#ifdef CONFIG_FW_ARC

6
drivers/clocksource/mips-gic-timer.c
View File

@@ -115,6 +115,9 @@ static void gic_update_frequency(void *data)
static int gic_starting_cpu(unsigned int cpu)
{
/* Ensure the GIC counter is running */
clear_gic_config(GIC_CONFIG_COUNTSTOP);
gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
return 0;
}
@@ -288,9 +291,6 @@ static int __init gic_clocksource_of_init(struct device_node *node)
pr_warn("Unable to register clock notifier\n");
}
/* And finally start the counter */
clear_gic_config(GIC_CONFIG_COUNTSTOP);
/*
* It's safe to use the MIPS GIC timer as a sched clock source only if
* its ticks are stable, which is true on either the platforms with

130
include/dt-bindings/clock/mediatek,mtmips-sysc.h Normal file
View File

@@ -0,0 +1,130 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
*/
#ifndef _DT_BINDINGS_CLK_MTMIPS_H
#define _DT_BINDINGS_CLK_MTMIPS_H
/* Ralink RT-2880 clocks */
#define RT2880_CLK_XTAL 0
#define RT2880_CLK_CPU 1
#define RT2880_CLK_BUS 2
#define RT2880_CLK_TIMER 3
#define RT2880_CLK_WATCHDOG 4
#define RT2880_CLK_UART 5
#define RT2880_CLK_I2C 6
#define RT2880_CLK_UARTLITE 7
#define RT2880_CLK_ETHERNET 8
#define RT2880_CLK_WMAC 9
/* Ralink RT-305X clocks */
#define RT305X_CLK_XTAL 0
#define RT305X_CLK_CPU 1
#define RT305X_CLK_BUS 2
#define RT305X_CLK_TIMER 3
#define RT305X_CLK_WATCHDOG 4
#define RT305X_CLK_UART 5
#define RT305X_CLK_I2C 6
#define RT305X_CLK_I2S 7
#define RT305X_CLK_SPI1 8
#define RT305X_CLK_SPI2 9
#define RT305X_CLK_UARTLITE 10
#define RT305X_CLK_ETHERNET 11
#define RT305X_CLK_WMAC 12
/* Ralink RT-3352 clocks */
#define RT3352_CLK_XTAL 0
#define RT3352_CLK_CPU 1
#define RT3352_CLK_PERIPH 2
#define RT3352_CLK_BUS 3
#define RT3352_CLK_TIMER 4
#define RT3352_CLK_WATCHDOG 5
#define RT3352_CLK_UART 6
#define RT3352_CLK_I2C 7
#define RT3352_CLK_I2S 8
#define RT3352_CLK_SPI1 9
#define RT3352_CLK_SPI2 10
#define RT3352_CLK_UARTLITE 11
#define RT3352_CLK_ETHERNET 12
#define RT3352_CLK_WMAC 13
/* Ralink RT-3883 clocks */
#define RT3883_CLK_XTAL 0
#define RT3883_CLK_CPU 1
#define RT3883_CLK_BUS 2
#define RT3883_CLK_PERIPH 3
#define RT3883_CLK_TIMER 4
#define RT3883_CLK_WATCHDOG 5
#define RT3883_CLK_UART 6
#define RT3883_CLK_I2C 7
#define RT3883_CLK_I2S 8
#define RT3883_CLK_SPI1 9
#define RT3883_CLK_SPI2 10
#define RT3883_CLK_UARTLITE 11
#define RT3883_CLK_ETHERNET 12
#define RT3883_CLK_WMAC 13
/* Ralink RT-5350 clocks */
#define RT5350_CLK_XTAL 0
#define RT5350_CLK_CPU 1
#define RT5350_CLK_BUS 2
#define RT5350_CLK_PERIPH 3
#define RT5350_CLK_TIMER 4
#define RT5350_CLK_WATCHDOG 5
#define RT5350_CLK_UART 6
#define RT5350_CLK_I2C 7
#define RT5350_CLK_I2S 8
#define RT5350_CLK_SPI1 9
#define RT5350_CLK_SPI2 10
#define RT5350_CLK_UARTLITE 11
#define RT5350_CLK_ETHERNET 12
#define RT5350_CLK_WMAC 13
/* Ralink MT-7620 clocks */
#define MT7620_CLK_XTAL 0
#define MT7620_CLK_PLL 1
#define MT7620_CLK_CPU 2
#define MT7620_CLK_PERIPH 3
#define MT7620_CLK_BUS 4
#define MT7620_CLK_BBPPLL 5
#define MT7620_CLK_SDHC 6
#define MT7620_CLK_TIMER 7
#define MT7620_CLK_WATCHDOG 8
#define MT7620_CLK_UART 9
#define MT7620_CLK_I2C 10
#define MT7620_CLK_I2S 11
#define MT7620_CLK_SPI1 12
#define MT7620_CLK_SPI2 13
#define MT7620_CLK_UARTLITE 14
#define MT7620_CLK_MMC 15
#define MT7620_CLK_WMAC 16
/* Ralink MT-76X8 clocks */
#define MT76X8_CLK_XTAL 0
#define MT76X8_CLK_CPU 1
#define MT76X8_CLK_BBPPLL 2
#define MT76X8_CLK_PCMI2S 3
#define MT76X8_CLK_PERIPH 4
#define MT76X8_CLK_BUS 5
#define MT76X8_CLK_SDHC 6
#define MT76X8_CLK_TIMER 7
#define MT76X8_CLK_WATCHDOG 8
#define MT76X8_CLK_I2C 9
#define MT76X8_CLK_I2S 10
#define MT76X8_CLK_SPI1 11
#define MT76X8_CLK_SPI2 12
#define MT76X8_CLK_UART0 13
#define MT76X8_CLK_UART1 14
#define MT76X8_CLK_UART2 15
#define MT76X8_CLK_MMC 16
#define MT76X8_CLK_WMAC 17
#endif /* _DT_BINDINGS_CLK_MTMIPS_H */