phy: cadence-torrent: Add PCIe multilink configuration for 100 MHz refclk
Add register sequences to support PCIe multilink configuration for 100MHz reference clock. Maximum two PCIe links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20250616064705.3225758-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Swapnil Jakhade
committed by
Vinod Koul
Vinod Koul
parent
47311eaa0a
commit
240ef19ad7
@@ -197,6 +197,7 @@
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#define RX_SDCAL1_INIT_TMR 0x004CU
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#define RX_SDCAL1_ITER_TMR 0x004DU
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#define RX_CDRLF_CNFG 0x0080U
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#define RX_CDRLF_CNFG2 0x0081U
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#define RX_CDRLF_CNFG3 0x0082U
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#define RX_SIGDET_HL_FILT_TMR 0x0090U
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#define RX_REE_GCSM1_CTRL 0x0108U
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@@ -204,6 +205,7 @@
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#define RX_REE_GCSM1_EQENM_PH2 0x010AU
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#define RX_REE_GCSM2_CTRL 0x0110U
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#define RX_REE_PERGCSM_CTRL 0x0118U
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#define RX_REE_PEAK_UTHR 0x0142U
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#define RX_REE_ATTEN_THR 0x0149U
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#define RX_REE_TAP1_CLIP 0x0171U
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#define RX_REE_TAP2TON_CLIP 0x0172U
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@@ -212,6 +214,7 @@
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#define RX_DIAG_DFE_CTRL 0x01E0U
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#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
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#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
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#define RX_DIAG_REE_DAC_CTRL 0x01E4U
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#define RX_DIAG_NQST_CTRL 0x01E5U
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#define RX_DIAG_SIGDET_TUNE 0x01E8U
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#define RX_DIAG_PI_RATE 0x01F4U
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@@ -3131,6 +3134,101 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev)
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cdns_torrent_clk_cleanup(cdns_phy);
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}
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/* Multi link PCIe configuration */
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static const struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = {
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{0x0002, PHY_PLL_CFG},
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{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
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};
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static const struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = {
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{0x0100, XCVR_DIAG_HSCLK_SEL},
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{0x0001, XCVR_DIAG_HSCLK_DIV},
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{0x0812, XCVR_DIAG_PLLDRC_CTRL}
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};
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static const struct cdns_torrent_vals ml_pcie_link_cmn_vals = {
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.reg_pairs = ml_pcie_link_cmn_regs,
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.num_regs = ARRAY_SIZE(ml_pcie_link_cmn_regs),
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};
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static const struct cdns_torrent_vals ml_pcie_xcvr_diag_ln_vals = {
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.reg_pairs = ml_pcie_xcvr_diag_ln_regs,
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.num_regs = ARRAY_SIZE(ml_pcie_xcvr_diag_ln_regs),
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};
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/* Multi link PCIe, 100 MHz Ref clk, no SSC */
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static const struct cdns_reg_pairs ml_pcie_100_no_ssc_cmn_regs[] = {
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{0x0003, CMN_PLL0_VCOCAL_TCTRL},
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{0x0003, CMN_PLL1_VCOCAL_TCTRL}
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};
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static const struct cdns_reg_pairs ml_pcie_100_no_ssc_rx_ln_regs[] = {
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{0x0019, RX_REE_TAP1_CLIP},
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{0x0019, RX_REE_TAP2TON_CLIP},
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{0x0008, RX_REE_PEAK_UTHR},
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{0x018E, RX_CDRLF_CNFG},
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{0x2E33, RX_CDRLF_CNFG2},
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{0x0001, RX_DIAG_ACYA},
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{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
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{0x0002, RX_DIAG_DFE_AMP_TUNE_3},
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{0x0005, RX_DIAG_REE_DAC_CTRL}
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};
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static const struct cdns_torrent_vals ml_pcie_100_no_ssc_cmn_vals = {
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.reg_pairs = ml_pcie_100_no_ssc_cmn_regs,
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.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_cmn_regs),
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};
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static const struct cdns_torrent_vals ml_pcie_100_no_ssc_rx_ln_vals = {
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.reg_pairs = ml_pcie_100_no_ssc_rx_ln_regs,
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.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_rx_ln_regs),
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};
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/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
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static const struct cdns_reg_pairs ml_pcie_100_int_ssc_cmn_regs[] = {
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{0x0004, CMN_PLL0_DSM_DIAG_M0},
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{0x0004, CMN_PLL1_DSM_DIAG_M0},
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{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
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{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
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{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
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{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
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{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
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{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
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{0x0064, CMN_PLL0_INTDIV_M0},
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{0x0050, CMN_PLL1_INTDIV_M0},
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{0x0002, CMN_PLL0_FRACDIVH_M0},
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{0x0002, CMN_PLL1_FRACDIVH_M0},
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{0x0044, CMN_PLL0_HIGH_THR_M0},
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{0x0036, CMN_PLL1_HIGH_THR_M0},
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{0x0002, CMN_PDIAG_PLL0_CTRL_M0},
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{0x0002, CMN_PDIAG_PLL1_CTRL_M0},
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{0x0001, CMN_PLL0_SS_CTRL1_M0},
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{0x0001, CMN_PLL1_SS_CTRL1_M0},
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{0x011B, CMN_PLL0_SS_CTRL2_M0},
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{0x011B, CMN_PLL1_SS_CTRL2_M0},
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{0x006E, CMN_PLL0_SS_CTRL3_M0},
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{0x0058, CMN_PLL1_SS_CTRL3_M0},
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{0x000E, CMN_PLL0_SS_CTRL4_M0},
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{0x0012, CMN_PLL1_SS_CTRL4_M0},
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{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
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{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
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{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
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{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
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{0x0003, CMN_PLL0_VCOCAL_TCTRL},
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{0x0003, CMN_PLL1_VCOCAL_TCTRL},
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{0x00C7, CMN_PLL0_LOCK_REFCNT_START},
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{0x00C7, CMN_PLL1_LOCK_REFCNT_START},
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{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
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{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
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{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
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{0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
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};
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static const struct cdns_torrent_vals ml_pcie_100_int_ssc_cmn_vals = {
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.reg_pairs = ml_pcie_100_int_ssc_cmn_regs,
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.num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_cmn_regs),
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};
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/* SGMII and QSGMII link configuration */
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static const struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = {
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{0x0002, PHY_PLL_CFG}
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@@ -4531,7 +4629,7 @@ static const struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
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.num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
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};
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/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
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/* For PCIe (with some other protocol), 100 MHz Ref clk, internal SSC */
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static const struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
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{0x0004, CMN_PLL0_DSM_DIAG_M0},
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{0x0004, CMN_PLL0_DSM_DIAG_M1},
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@@ -4670,6 +4768,7 @@ static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_link_cmn_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
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@@ -4706,6 +4805,7 @@ static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_xcvr_diag_ln_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
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{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
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@@ -4756,6 +4856,10 @@ static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
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@@ -4838,6 +4942,10 @@ static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
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@@ -4920,6 +5028,10 @@ static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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@@ -5038,6 +5150,10 @@ static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
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@@ -5154,6 +5270,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
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@@ -5236,6 +5356,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
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@@ -5318,6 +5442,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
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