Merge tag 'samsung-clk-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski: - Tesla FSD: Move number of clocks from DT binding headers to driver, because these are not an ABI and might change while finishing support for the hardware. - ExynosAutov920: Add clock controller drivers for PERIC1, MISC, HSI0 and HSI1. Context of patch depends on a fix from fixes branch, thus pull in my earlier pull request with fixes. - Google GS101: Do not disable UFS host controller clocks, ever, because gating them does not work well with UFS sleep/power savings. Downstream does not gate them via OS, but uses hardware feature - Automatic Clock Gating - which is not yet supported in upstream. - Exynos8895: New SoC with initial support for clock controllers: FSYS0/1, PERIC0/1, PERIS and TOP. * tag 'samsung-clk-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: Introduce Exynos8895 clock driver clk: samsung: clk-pll: Add support for pll_{1051x,1052x} dt-bindings: clock: samsung: Add Exynos8895 SoC clk: samsung: gs101: make all ufs related clocks critical clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions clk: samsung: Fix out-of-bound access of of_match_node() dt-bindings: clock: samsung: remove define with number of clocks for FSD clk: samsung: fsd: do not define number of clocks in bindings clk: samsung: Fix errors reported by checkpatch clk: samsung: Fix block comment style warnings reported by checkpatch
This commit is contained in:
Stephen Boyd
@@ -0,0 +1,239 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos8895 SoC clock controller
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maintainers:
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- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |
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Exynos8895 clock controller is comprised of several CMU units, generating
|
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. The root clock in that root tree
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is an external clock: OSCCLK (26 MHz). This external clock must be defined
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as a fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/samsung,exynos8895.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynos8895-cmu-fsys0
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- samsung,exynos8895-cmu-fsys1
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- samsung,exynos8895-cmu-peric0
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- samsung,exynos8895-cmu-peric1
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- samsung,exynos8895-cmu-peris
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- samsung,exynos8895-cmu-top
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clocks:
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minItems: 1
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maxItems: 16
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clock-names:
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minItems: 1
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maxItems: 16
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"#clock-cells":
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const: 1
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|
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- reg
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- "#clock-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-fsys0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS0 BUS clock (from CMU_TOP)
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- description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
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- description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
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- description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
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- description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: dpgtc
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- const: mmc
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- const: ufs
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- const: usbdrd30
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-fsys1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS1 BUS clock (from CMU_TOP)
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- description: CMU_FSYS1 PCIE clock (from CMU_TOP)
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- description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
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- description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: pcie
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- const: ufs
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- const: mmc
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|
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-peric0
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|
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_PERIC0 BUS clock (from CMU_TOP)
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- description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
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- description: CMU_PERIC0 USI00 clock (from CMU_TOP)
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- description: CMU_PERIC0 USI01 clock (from CMU_TOP)
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- description: CMU_PERIC0 USI02 clock (from CMU_TOP)
|
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- description: CMU_PERIC0 USI03 clock (from CMU_TOP)
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|
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: uart
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- const: usi0
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- const: usi1
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- const: usi2
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- const: usi3
|
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|
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- if:
|
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properties:
|
||||
compatible:
|
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contains:
|
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const: samsung,exynos8895-cmu-peric1
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|
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then:
|
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properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
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- description: CMU_PERIC1 BUS clock (from CMU_TOP)
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- description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
|
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- description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
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- description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
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- description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
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- description: CMU_PERIC1 USI04 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI05 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI06 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI07 clock (from CMU_TOP)
|
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- description: CMU_PERIC1 USI08 clock (from CMU_TOP)
|
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- description: CMU_PERIC1 USI09 clock (from CMU_TOP)
|
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- description: CMU_PERIC1 USI10 clock (from CMU_TOP)
|
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- description: CMU_PERIC1 USI11 clock (from CMU_TOP)
|
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- description: CMU_PERIC1 USI12 clock (from CMU_TOP)
|
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- description: CMU_PERIC1 USI13 clock (from CMU_TOP)
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|
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clock-names:
|
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items:
|
||||
- const: oscclk
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- const: bus
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- const: speedy
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- const: cam0
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- const: cam1
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- const: uart
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- const: usi4
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- const: usi5
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- const: usi6
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- const: usi7
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- const: usi8
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- const: usi9
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- const: usi10
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- const: usi11
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- const: usi12
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- const: usi13
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|
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- if:
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properties:
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||||
compatible:
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contains:
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const: samsung,exynos8895-cmu-peris
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|
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then:
|
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properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
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- description: CMU_PERIS BUS clock (from CMU_TOP)
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|
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clock-names:
|
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items:
|
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- const: oscclk
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- const: bus
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|
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- if:
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properties:
|
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compatible:
|
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contains:
|
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const: samsung,exynos8895-cmu-top
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|
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then:
|
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properties:
|
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clocks:
|
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items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
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- const: oscclk
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|
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additionalProperties: false
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|
||||
examples:
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- |
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#include <dt-bindings/clock/samsung,exynos8895.h>
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cmu_fsys1: clock-controller@11400000 {
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compatible = "samsung,exynos8895-cmu-fsys1";
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reg = <0x11400000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
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clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
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};
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...
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@@ -20,6 +20,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
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@@ -4,7 +4,7 @@
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* Author: Padmavathi Venna <padma.v@samsung.com>
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*
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* Common Clock Framework support for Audio Subsystem Clock Controller.
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*/
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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@@ -260,7 +260,7 @@ static const struct samsung_mux_clock mux_clks[] __initconst = {
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/* SRC_TOP0 */
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MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
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MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
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MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p, SRC_TOP0, 24, 1),
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MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
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MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
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MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
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@@ -5,7 +5,7 @@
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* Common Clock Framework support for all Exynos4 SoCs.
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*/
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*/
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#include <dt-bindings/clock/exynos4.h>
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#include <linux/slab.h>
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@@ -4,7 +4,7 @@
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* Author: Marek Szyprowski <m.szyprowski@samsung.com>
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*
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* Common Clock Framework support for Exynos4412 ISP module.
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*/
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*/
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#include <dt-bindings/clock/exynos4.h>
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#include <linux/slab.h>
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@@ -5,7 +5,7 @@
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* Common Clock Framework support for Exynos5250 SoC.
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*/
|
||||
*/
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#include <dt-bindings/clock/exynos5250.h>
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#include <linux/clk-provider.h>
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@@ -1458,7 +1458,7 @@ static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
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FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
|
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NULL, 0, 125000000),
|
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FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
|
||||
"phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
|
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"phyclk_mipi_dphy_4l_m_txbyte_clkhs", NULL,
|
||||
0, 187500000),
|
||||
FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
|
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NULL, 0, 24000000),
|
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@@ -1629,7 +1629,7 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
|
||||
mout_isp1_media_400_p,
|
||||
MUX_SEL_TOP_ISP10, 4, 1),
|
||||
MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
|
||||
MUX_SEL_TOP_ISP10, 8 , 1),
|
||||
MUX_SEL_TOP_ISP10, 8, 1),
|
||||
MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
|
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mout_isp1_media_266_p,
|
||||
MUX_SEL_TOP_ISP10, 16, 1),
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
* Author: Tarek Dakhran <t.dakhran@samsung.com>
|
||||
*
|
||||
* Common Clock Framework support for Exynos5410 SoC.
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5410.h>
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
* Chander Kashyap <k.chander@samsung.com>
|
||||
*
|
||||
* Common Clock Framework support for Exynos5420 SoC.
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/exynos5420.h>
|
||||
#include <linux/slab.h>
|
||||
@@ -295,8 +295,8 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
|
||||
/* list of all parent clocks */
|
||||
PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
|
||||
"mout_sclk_mpll", "mout_sclk_spll"};
|
||||
PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
|
||||
PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
|
||||
PNAME(mout_cpu_p) = {"mout_apll", "mout_mspll_cpu"};
|
||||
PNAME(mout_kfc_p) = {"mout_kpll", "mout_mspll_kfc"};
|
||||
PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
|
||||
PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
|
||||
PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
2803
drivers/clk/samsung/clk-exynos8895.c
Normal file
2803
drivers/clk/samsung/clk-exynos8895.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -19,6 +19,10 @@
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
|
||||
#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
|
||||
#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
|
||||
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
|
||||
#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
|
||||
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
|
||||
|
||||
/* ---- CMU_TOP ------------------------------------------------------------ */
|
||||
|
||||
@@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon
|
||||
"mout_shared5_pll", 1, 3, 0),
|
||||
FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
|
||||
"mout_shared5_pll", 1, 4, 0),
|
||||
FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",
|
||||
"oscclk", 1, 2, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info top_cmu_info __initconst = {
|
||||
@@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
|
||||
.clk_name = "noc",
|
||||
};
|
||||
|
||||
/* ---- CMU_PERIC1 --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
|
||||
#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
|
||||
|
||||
static const unsigned long peric1_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_I3C,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIC1 */
|
||||
PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
|
||||
PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };
|
||||
PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
|
||||
|
||||
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
|
||||
mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
|
||||
mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
|
||||
/* USI09 ~ USI17 */
|
||||
MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
|
||||
/* USI_I2C */
|
||||
MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
|
||||
/* USI_I3C */
|
||||
MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
|
||||
/* USI09 ~ USI17 */
|
||||
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
|
||||
"mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
|
||||
"mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
|
||||
"mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
|
||||
"mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",
|
||||
"mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",
|
||||
"mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",
|
||||
"mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
|
||||
"mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
|
||||
"mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
|
||||
0, 4),
|
||||
/* USI_I2C */
|
||||
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
|
||||
"mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
|
||||
/* USI_I3C */
|
||||
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",
|
||||
"mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
|
||||
.mux_clks = peric1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
|
||||
.div_clks = peric1_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
|
||||
.nr_clk_ids = CLKS_NR_PERIC1,
|
||||
.clk_regs = peric1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
|
||||
.clk_name = "noc",
|
||||
};
|
||||
|
||||
/* ---- CMU_MISC --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_MISC (0x10020000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
|
||||
#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
|
||||
#define CLK_CON_DIV_CLKCMU_OTP 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
|
||||
#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
|
||||
|
||||
static const unsigned long misc_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,
|
||||
CLK_CON_MUX_MUX_CLK_MISC_GIC,
|
||||
CLK_CON_DIV_CLKCMU_OTP,
|
||||
CLK_CON_DIV_DIV_CLK_MISC_NOCP,
|
||||
CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_MISC */
|
||||
PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };
|
||||
PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };
|
||||
|
||||
static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",
|
||||
mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),
|
||||
MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",
|
||||
mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock misc_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",
|
||||
"mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,
|
||||
0, 3),
|
||||
};
|
||||
|
||||
static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {
|
||||
FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",
|
||||
"oscclk", 1, 10, 0),
|
||||
FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",
|
||||
"oscclk", 1, 2, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info misc_cmu_info __initconst = {
|
||||
.mux_clks = misc_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
|
||||
.div_clks = misc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(misc_div_clks),
|
||||
.fixed_factor_clks = misc_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks),
|
||||
.nr_clk_ids = CLKS_NR_MISC,
|
||||
.clk_regs = misc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
|
||||
.clk_name = "noc",
|
||||
};
|
||||
|
||||
/* ---- CMU_HSI0 --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_HSI0 (0x16000000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
|
||||
#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
|
||||
|
||||
static const unsigned long hsi0_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
|
||||
CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_HSI0 */
|
||||
PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };
|
||||
|
||||
static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",
|
||||
mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",
|
||||
"mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
|
||||
0, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
|
||||
.mux_clks = hsi0_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
|
||||
.div_clks = hsi0_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
|
||||
.nr_clk_ids = CLKS_NR_HSI0,
|
||||
.clk_regs = hsi0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
|
||||
.clk_name = "noc",
|
||||
};
|
||||
|
||||
/* ---- CMU_HSI1 --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_HSI1 (0x16400000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
|
||||
#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
|
||||
#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
|
||||
#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
|
||||
|
||||
static const unsigned long hsi1_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
|
||||
PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
|
||||
PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,
|
||||
CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_HSI1 */
|
||||
PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
|
||||
PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
|
||||
PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
|
||||
PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
|
||||
|
||||
static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
|
||||
mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),
|
||||
MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",
|
||||
mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),
|
||||
MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",
|
||||
mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),
|
||||
MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",
|
||||
mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
|
||||
.mux_clks = hsi1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
|
||||
.nr_clk_ids = CLKS_NR_HSI1,
|
||||
.clk_regs = hsi1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
|
||||
.clk_name = "noc",
|
||||
};
|
||||
|
||||
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct samsung_cmu_info *info;
|
||||
@@ -1154,7 +1431,20 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
|
||||
{
|
||||
.compatible = "samsung,exynosautov920-cmu-peric0",
|
||||
.data = &peric0_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-peric1",
|
||||
.data = &peric1_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-misc",
|
||||
.data = &misc_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-hsi0",
|
||||
.data = &hsi0_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov920-cmu-hsi1",
|
||||
.data = &hsi1_cmu_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver exynosautov920_cmu_driver __refdata = {
|
||||
|
||||
@@ -82,6 +82,15 @@
|
||||
#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
|
||||
#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
|
||||
|
||||
/* NOTE: Must be equal to the last clock ID increased by one */
|
||||
#define CLKS_NR_CMU (GAT_CMU_FSYS0_SHARED0DIV4 + 1)
|
||||
#define CLKS_NR_PERIC (PERIC_DOUT_RGMII_CLK + 1)
|
||||
#define CLKS_NR_FSYS0 (FSYS0_DOUT_FSYS0_PERIBUS_GRP + 1)
|
||||
#define CLKS_NR_FSYS1 (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1)
|
||||
#define CLKS_NR_IMEM (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1)
|
||||
#define CLKS_NR_MFC (MFC_MFC_IPCLKPORT_ACLK + 1)
|
||||
#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_ACLK + 1)
|
||||
|
||||
static const unsigned long cmu_clk_regs[] __initconst = {
|
||||
PLL_LOCKTIME_PLL_SHARED0,
|
||||
PLL_LOCKTIME_PLL_SHARED1,
|
||||
@@ -300,7 +309,7 @@ static const struct samsung_cmu_info cmu_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(cmu_div_clks),
|
||||
.gate_clks = cmu_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(cmu_gate_clks),
|
||||
.nr_clk_ids = CMU_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CMU,
|
||||
.clk_regs = cmu_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cmu_clk_regs),
|
||||
};
|
||||
@@ -665,7 +674,7 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
|
||||
.fixed_clks = peric_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks),
|
||||
.nr_clk_ids = PERIC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_PERIC,
|
||||
.clk_regs = peric_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
|
||||
.clk_name = "dout_cmu_pll_shared0_div4",
|
||||
@@ -964,7 +973,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
|
||||
.fixed_clks = fsys0_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks),
|
||||
.nr_clk_ids = FSYS0_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS0,
|
||||
.clk_regs = fsys0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
|
||||
.clk_name = "dout_cmu_fsys0_shared1div4",
|
||||
@@ -1136,7 +1145,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
|
||||
.fixed_clks = fsys1_fixed_clks,
|
||||
.nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks),
|
||||
.nr_clk_ids = FSYS1_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_FSYS1,
|
||||
.clk_regs = fsys1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
|
||||
.clk_name = "dout_cmu_fsys1_shared0div4",
|
||||
@@ -1413,7 +1422,7 @@ static const struct samsung_cmu_info imem_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(imem_div_clks),
|
||||
.gate_clks = imem_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
|
||||
.nr_clk_ids = IMEM_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_IMEM,
|
||||
.clk_regs = imem_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
|
||||
};
|
||||
@@ -1538,7 +1547,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
|
||||
.gate_clks = mfc_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
|
||||
.nr_clk_ids = MFC_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_MFC,
|
||||
.clk_regs = mfc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
|
||||
};
|
||||
@@ -1742,7 +1751,7 @@ static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
|
||||
.nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
|
||||
.gate_clks = cam_csi_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
|
||||
.nr_clk_ids = CAM_CSI_NR_CLK,
|
||||
.nr_clk_ids = CLKS_NR_CAM_CSI,
|
||||
.clk_regs = cam_csi_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
|
||||
};
|
||||
|
||||
@@ -2775,11 +2775,11 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
|
||||
"gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
|
||||
21, 0, 0),
|
||||
21, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
|
||||
"gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
21, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
|
||||
"gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
|
||||
@@ -2806,7 +2806,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
|
||||
"gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
|
||||
21, 0, 0),
|
||||
21, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
|
||||
"gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
|
||||
@@ -2842,7 +2842,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
|
||||
"gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
|
||||
21, 0, 0),
|
||||
21, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
|
||||
"gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
||||
@@ -2850,7 +2850,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
|
||||
"gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
|
||||
21, 0, 0),
|
||||
21, CLK_IS_CRITICAL, 0),
|
||||
/* TODO: should have a driver for this */
|
||||
GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
|
||||
"gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",
|
||||
|
||||
@@ -1370,6 +1370,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
break;
|
||||
case pll_1417x:
|
||||
case pll_1418x:
|
||||
case pll_1051x:
|
||||
case pll_1052x:
|
||||
case pll_0818x:
|
||||
case pll_0822x:
|
||||
case pll_0516x:
|
||||
|
||||
@@ -43,6 +43,8 @@ enum samsung_pll_type {
|
||||
pll_0517x,
|
||||
pll_0518x,
|
||||
pll_531x,
|
||||
pll_1051x,
|
||||
pll_1052x,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
|
||||
*
|
||||
* Common Clock Framework support for all S3C64xx SoCs.
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
* Author: Padmavathi Venna <padma.v@samsung.com>
|
||||
*
|
||||
* Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
*
|
||||
* This file includes utility functions to register clocks to common
|
||||
* clock framework for Samsung platforms.
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
@@ -28,7 +28,6 @@
|
||||
#define DOUT_CMU_IMEM_ACLK 13
|
||||
#define DOUT_CMU_IMEM_DMACLK 14
|
||||
#define GAT_CMU_FSYS0_SHARED0DIV4 15
|
||||
#define CMU_NR_CLK 16
|
||||
|
||||
/* PERIC */
|
||||
#define PERIC_SCLK_UART0 1
|
||||
@@ -76,7 +75,6 @@
|
||||
#define PERIC_EQOS_PHYRXCLK_MUX 43
|
||||
#define PERIC_EQOS_PHYRXCLK 44
|
||||
#define PERIC_DOUT_RGMII_CLK 45
|
||||
#define PERIC_NR_CLK 46
|
||||
|
||||
/* FSYS0 */
|
||||
#define UFS0_MPHY_REFCLK_IXTAL24 1
|
||||
@@ -101,7 +99,6 @@
|
||||
#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
|
||||
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
|
||||
#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
|
||||
#define FSYS0_NR_CLK 23
|
||||
|
||||
/* FSYS1 */
|
||||
#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
|
||||
@@ -112,7 +109,6 @@
|
||||
#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
|
||||
#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
|
||||
#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
|
||||
#define FSYS1_NR_CLK 9
|
||||
|
||||
/* IMEM */
|
||||
#define IMEM_DMA0_IPCLKPORT_ACLK 1
|
||||
@@ -126,11 +122,9 @@
|
||||
#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
|
||||
#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
|
||||
#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
|
||||
#define IMEM_NR_CLK 12
|
||||
|
||||
/* MFC */
|
||||
#define MFC_MFC_IPCLKPORT_ACLK 1
|
||||
#define MFC_NR_CLK 2
|
||||
|
||||
/* CAM_CSI */
|
||||
#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
|
||||
@@ -145,6 +139,5 @@
|
||||
#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
|
||||
#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
|
||||
#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
|
||||
#define CAM_CSI_NR_CLK 13
|
||||
|
||||
#endif /*_DT_BINDINGS_CLOCK_FSD_H */
|
||||
|
||||
453
include/dt-bindings/clock/samsung,exynos8895.h
Normal file
453
include/dt-bindings/clock/samsung,exynos8895.h
Normal file
@@ -0,0 +1,453 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2024 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
* Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
*
|
||||
* Device Tree binding constants for Exynos8895 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS8895_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS8895_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_FOUT_SHARED2_PLL 3
|
||||
#define CLK_FOUT_SHARED3_PLL 4
|
||||
#define CLK_FOUT_SHARED4_PLL 5
|
||||
#define CLK_MOUT_PLL_SHARED0 6
|
||||
#define CLK_MOUT_PLL_SHARED1 7
|
||||
#define CLK_MOUT_PLL_SHARED2 8
|
||||
#define CLK_MOUT_PLL_SHARED3 9
|
||||
#define CLK_MOUT_PLL_SHARED4 10
|
||||
#define CLK_MOUT_CP2AP_MIF_CLK_USER 11
|
||||
#define CLK_MOUT_CMU_ABOX_CPUABOX 12
|
||||
#define CLK_MOUT_CMU_APM_BUS 13
|
||||
#define CLK_MOUT_CMU_BUS1_BUS 14
|
||||
#define CLK_MOUT_CMU_BUSC_BUS 15
|
||||
#define CLK_MOUT_CMU_BUSC_BUSPHSI2C 16
|
||||
#define CLK_MOUT_CMU_CAM_BUS 17
|
||||
#define CLK_MOUT_CMU_CAM_TPU0 18
|
||||
#define CLK_MOUT_CMU_CAM_TPU1 19
|
||||
#define CLK_MOUT_CMU_CAM_VRA 20
|
||||
#define CLK_MOUT_CMU_CIS_CLK0 21
|
||||
#define CLK_MOUT_CMU_CIS_CLK1 22
|
||||
#define CLK_MOUT_CMU_CIS_CLK2 23
|
||||
#define CLK_MOUT_CMU_CIS_CLK3 24
|
||||
#define CLK_MOUT_CMU_CORE_BUS 25
|
||||
#define CLK_MOUT_CMU_CPUCL0_SWITCH 26
|
||||
#define CLK_MOUT_CMU_CPUCL1_SWITCH 27
|
||||
#define CLK_MOUT_CMU_DBG_BUS 28
|
||||
#define CLK_MOUT_CMU_DCAM_BUS 29
|
||||
#define CLK_MOUT_CMU_DCAM_IMGD 30
|
||||
#define CLK_MOUT_CMU_DPU_BUS 31
|
||||
#define CLK_MOUT_CMU_DROOPDETECTOR 32
|
||||
#define CLK_MOUT_CMU_DSP_BUS 33
|
||||
#define CLK_MOUT_CMU_FSYS0_BUS 34
|
||||
#define CLK_MOUT_CMU_FSYS0_DPGTC 35
|
||||
#define CLK_MOUT_CMU_FSYS0_MMC_EMBD 36
|
||||
#define CLK_MOUT_CMU_FSYS0_UFS_EMBD 37
|
||||
#define CLK_MOUT_CMU_FSYS0_USBDRD30 38
|
||||
#define CLK_MOUT_CMU_FSYS1_BUS 39
|
||||
#define CLK_MOUT_CMU_FSYS1_MMC_CARD 40
|
||||
#define CLK_MOUT_CMU_FSYS1_PCIE 41
|
||||
#define CLK_MOUT_CMU_FSYS1_UFS_CARD 42
|
||||
#define CLK_MOUT_CMU_G2D_G2D 43
|
||||
#define CLK_MOUT_CMU_G2D_JPEG 44
|
||||
#define CLK_MOUT_CMU_HPM 45
|
||||
#define CLK_MOUT_CMU_IMEM_BUS 46
|
||||
#define CLK_MOUT_CMU_ISPHQ_BUS 47
|
||||
#define CLK_MOUT_CMU_ISPLP_BUS 48
|
||||
#define CLK_MOUT_CMU_IVA_BUS 49
|
||||
#define CLK_MOUT_CMU_MFC_BUS 50
|
||||
#define CLK_MOUT_CMU_MIF_SWITCH 51
|
||||
#define CLK_MOUT_CMU_PERIC0_BUS 52
|
||||
#define CLK_MOUT_CMU_PERIC0_UART_DBG 53
|
||||
#define CLK_MOUT_CMU_PERIC0_USI00 54
|
||||
#define CLK_MOUT_CMU_PERIC0_USI01 55
|
||||
#define CLK_MOUT_CMU_PERIC0_USI02 56
|
||||
#define CLK_MOUT_CMU_PERIC0_USI03 57
|
||||
#define CLK_MOUT_CMU_PERIC1_BUS 58
|
||||
#define CLK_MOUT_CMU_PERIC1_SPEEDY2 59
|
||||
#define CLK_MOUT_CMU_PERIC1_SPI_CAM0 60
|
||||
#define CLK_MOUT_CMU_PERIC1_SPI_CAM1 61
|
||||
#define CLK_MOUT_CMU_PERIC1_UART_BT 62
|
||||
#define CLK_MOUT_CMU_PERIC1_USI04 63
|
||||
#define CLK_MOUT_CMU_PERIC1_USI05 64
|
||||
#define CLK_MOUT_CMU_PERIC1_USI06 65
|
||||
#define CLK_MOUT_CMU_PERIC1_USI07 66
|
||||
#define CLK_MOUT_CMU_PERIC1_USI08 67
|
||||
#define CLK_MOUT_CMU_PERIC1_USI09 68
|
||||
#define CLK_MOUT_CMU_PERIC1_USI10 69
|
||||
#define CLK_MOUT_CMU_PERIC1_USI11 70
|
||||
#define CLK_MOUT_CMU_PERIC1_USI12 71
|
||||
#define CLK_MOUT_CMU_PERIC1_USI13 72
|
||||
#define CLK_MOUT_CMU_PERIS_BUS 73
|
||||
#define CLK_MOUT_CMU_SRDZ_BUS 74
|
||||
#define CLK_MOUT_CMU_SRDZ_IMGD 75
|
||||
#define CLK_MOUT_CMU_VPU_BUS 76
|
||||
#define CLK_DOUT_CMU_ABOX_CPUABOX 77
|
||||
#define CLK_DOUT_CMU_APM_BUS 78
|
||||
#define CLK_DOUT_CMU_BUS1_BUS 79
|
||||
#define CLK_DOUT_CMU_BUSC_BUS 80
|
||||
#define CLK_DOUT_CMU_BUSC_BUSPHSI2C 81
|
||||
#define CLK_DOUT_CMU_CAM_BUS 82
|
||||
#define CLK_DOUT_CMU_CAM_TPU0 83
|
||||
#define CLK_DOUT_CMU_CAM_TPU1 84
|
||||
#define CLK_DOUT_CMU_CAM_VRA 85
|
||||
#define CLK_DOUT_CMU_CIS_CLK0 86
|
||||
#define CLK_DOUT_CMU_CIS_CLK1 87
|
||||
#define CLK_DOUT_CMU_CIS_CLK2 88
|
||||
#define CLK_DOUT_CMU_CIS_CLK3 89
|
||||
#define CLK_DOUT_CMU_CORE_BUS 90
|
||||
#define CLK_DOUT_CMU_CPUCL0_SWITCH 91
|
||||
#define CLK_DOUT_CMU_CPUCL1_SWITCH 92
|
||||
#define CLK_DOUT_CMU_DBG_BUS 93
|
||||
#define CLK_DOUT_CMU_DCAM_BUS 94
|
||||
#define CLK_DOUT_CMU_DCAM_IMGD 95
|
||||
#define CLK_DOUT_CMU_DPU_BUS 96
|
||||
#define CLK_DOUT_CMU_DSP_BUS 97
|
||||
#define CLK_DOUT_CMU_FSYS0_BUS 98
|
||||
#define CLK_DOUT_CMU_FSYS0_DPGTC 99
|
||||
#define CLK_DOUT_CMU_FSYS0_MMC_EMBD 100
|
||||
#define CLK_DOUT_CMU_FSYS0_UFS_EMBD 101
|
||||
#define CLK_DOUT_CMU_FSYS0_USBDRD30 102
|
||||
#define CLK_DOUT_CMU_FSYS1_BUS 103
|
||||
#define CLK_DOUT_CMU_FSYS1_MMC_CARD 104
|
||||
#define CLK_DOUT_CMU_FSYS1_UFS_CARD 105
|
||||
#define CLK_DOUT_CMU_G2D_G2D 106
|
||||
#define CLK_DOUT_CMU_G2D_JPEG 107
|
||||
#define CLK_DOUT_CMU_G3D_SWITCH 108
|
||||
#define CLK_DOUT_CMU_HPM 109
|
||||
#define CLK_DOUT_CMU_IMEM_BUS 110
|
||||
#define CLK_DOUT_CMU_ISPHQ_BUS 111
|
||||
#define CLK_DOUT_CMU_ISPLP_BUS 112
|
||||
#define CLK_DOUT_CMU_IVA_BUS 113
|
||||
#define CLK_DOUT_CMU_MFC_BUS 114
|
||||
#define CLK_DOUT_CMU_MODEM_SHARED0 115
|
||||
#define CLK_DOUT_CMU_MODEM_SHARED1 116
|
||||
#define CLK_DOUT_CMU_PERIC0_BUS 117
|
||||
#define CLK_DOUT_CMU_PERIC0_UART_DBG 118
|
||||
#define CLK_DOUT_CMU_PERIC0_USI00 119
|
||||
#define CLK_DOUT_CMU_PERIC0_USI01 120
|
||||
#define CLK_DOUT_CMU_PERIC0_USI02 121
|
||||
#define CLK_DOUT_CMU_PERIC0_USI03 122
|
||||
#define CLK_DOUT_CMU_PERIC1_BUS 123
|
||||
#define CLK_DOUT_CMU_PERIC1_SPEEDY2 124
|
||||
#define CLK_DOUT_CMU_PERIC1_SPI_CAM0 125
|
||||
#define CLK_DOUT_CMU_PERIC1_SPI_CAM1 126
|
||||
#define CLK_DOUT_CMU_PERIC1_UART_BT 127
|
||||
#define CLK_DOUT_CMU_PERIC1_USI04 128
|
||||
#define CLK_DOUT_CMU_PERIC1_USI05 129
|
||||
#define CLK_DOUT_CMU_PERIC1_USI06 130
|
||||
#define CLK_DOUT_CMU_PERIC1_USI07 131
|
||||
#define CLK_DOUT_CMU_PERIC1_USI08 132
|
||||
#define CLK_DOUT_CMU_PERIC1_USI09 133
|
||||
#define CLK_DOUT_CMU_PERIC1_USI10 134
|
||||
#define CLK_DOUT_CMU_PERIC1_USI11 135
|
||||
#define CLK_DOUT_CMU_PERIC1_USI12 136
|
||||
#define CLK_DOUT_CMU_PERIC1_USI13 137
|
||||
#define CLK_DOUT_CMU_PERIS_BUS 138
|
||||
#define CLK_DOUT_CMU_SRDZ_BUS 139
|
||||
#define CLK_DOUT_CMU_SRDZ_IMGD 140
|
||||
#define CLK_DOUT_CMU_VPU_BUS 141
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV2 142
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV4 143
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV2 144
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV4 145
|
||||
#define CLK_DOUT_CMU_SHARED2_DIV2 146
|
||||
#define CLK_DOUT_CMU_SHARED3_DIV2 147
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV2 148
|
||||
#define CLK_DOUT_CMU_FSYS1_PCIE 149
|
||||
#define CLK_DOUT_CMU_CP2AP_MIF_CLK_DIV2 150
|
||||
#define CLK_DOUT_CMU_CMU_OTP 151
|
||||
#define CLK_GOUT_CMU_DROOPDETECTOR 152
|
||||
#define CLK_GOUT_CMU_MIF_SWITCH 153
|
||||
#define CLK_GOUT_CMU_ABOX_CPUABOX 154
|
||||
#define CLK_GOUT_CMU_APM_BUS 155
|
||||
#define CLK_GOUT_CMU_BUS1_BUS 156
|
||||
#define CLK_GOUT_CMU_BUSC_BUS 157
|
||||
#define CLK_GOUT_CMU_BUSC_BUSPHSI2C 158
|
||||
#define CLK_GOUT_CMU_CAM_BUS 159
|
||||
#define CLK_GOUT_CMU_CAM_TPU0 160
|
||||
#define CLK_GOUT_CMU_CAM_TPU1 161
|
||||
#define CLK_GOUT_CMU_CAM_VRA 162
|
||||
#define CLK_GOUT_CMU_CIS_CLK0 163
|
||||
#define CLK_GOUT_CMU_CIS_CLK1 164
|
||||
#define CLK_GOUT_CMU_CIS_CLK2 165
|
||||
#define CLK_GOUT_CMU_CIS_CLK3 166
|
||||
#define CLK_GOUT_CMU_CORE_BUS 167
|
||||
#define CLK_GOUT_CMU_CPUCL0_SWITCH 168
|
||||
#define CLK_GOUT_CMU_CPUCL1_SWITCH 169
|
||||
#define CLK_GOUT_CMU_DBG_BUS 170
|
||||
#define CLK_GOUT_CMU_DCAM_BUS 171
|
||||
#define CLK_GOUT_CMU_DCAM_IMGD 172
|
||||
#define CLK_GOUT_CMU_DPU_BUS 173
|
||||
#define CLK_GOUT_CMU_DSP_BUS 174
|
||||
#define CLK_GOUT_CMU_FSYS0_BUS 175
|
||||
#define CLK_GOUT_CMU_FSYS0_DPGTC 176
|
||||
#define CLK_GOUT_CMU_FSYS0_MMC_EMBD 177
|
||||
#define CLK_GOUT_CMU_FSYS0_UFS_EMBD 178
|
||||
#define CLK_GOUT_CMU_FSYS0_USBDRD30 179
|
||||
#define CLK_GOUT_CMU_FSYS1_BUS 180
|
||||
#define CLK_GOUT_CMU_FSYS1_MMC_CARD 181
|
||||
#define CLK_GOUT_CMU_FSYS1_PCIE 182
|
||||
#define CLK_GOUT_CMU_FSYS1_UFS_CARD 183
|
||||
#define CLK_GOUT_CMU_G2D_G2D 184
|
||||
#define CLK_GOUT_CMU_G2D_JPEG 185
|
||||
#define CLK_GOUT_CMU_G3D_SWITCH 186
|
||||
#define CLK_GOUT_CMU_HPM 187
|
||||
#define CLK_GOUT_CMU_IMEM_BUS 188
|
||||
#define CLK_GOUT_CMU_ISPHQ_BUS 189
|
||||
#define CLK_GOUT_CMU_ISPLP_BUS 190
|
||||
#define CLK_GOUT_CMU_IVA_BUS 191
|
||||
#define CLK_GOUT_CMU_MFC_BUS 192
|
||||
#define CLK_GOUT_CMU_MODEM_SHARED0 193
|
||||
#define CLK_GOUT_CMU_MODEM_SHARED1 194
|
||||
#define CLK_GOUT_CMU_PERIC0_BUS 195
|
||||
#define CLK_GOUT_CMU_PERIC0_UART_DBG 196
|
||||
#define CLK_GOUT_CMU_PERIC0_USI00 197
|
||||
#define CLK_GOUT_CMU_PERIC0_USI01 198
|
||||
#define CLK_GOUT_CMU_PERIC0_USI02 199
|
||||
#define CLK_GOUT_CMU_PERIC0_USI03 200
|
||||
#define CLK_GOUT_CMU_PERIC1_BUS 201
|
||||
#define CLK_GOUT_CMU_PERIC1_SPEEDY2 202
|
||||
#define CLK_GOUT_CMU_PERIC1_SPI_CAM0 203
|
||||
#define CLK_GOUT_CMU_PERIC1_SPI_CAM1 204
|
||||
#define CLK_GOUT_CMU_PERIC1_UART_BT 205
|
||||
#define CLK_GOUT_CMU_PERIC1_USI04 206
|
||||
#define CLK_GOUT_CMU_PERIC1_USI05 207
|
||||
#define CLK_GOUT_CMU_PERIC1_USI06 208
|
||||
#define CLK_GOUT_CMU_PERIC1_USI07 209
|
||||
#define CLK_GOUT_CMU_PERIC1_USI08 210
|
||||
#define CLK_GOUT_CMU_PERIC1_USI09 211
|
||||
#define CLK_GOUT_CMU_PERIC1_USI10 212
|
||||
#define CLK_GOUT_CMU_PERIC1_USI11 213
|
||||
#define CLK_GOUT_CMU_PERIC1_USI12 214
|
||||
#define CLK_GOUT_CMU_PERIC1_USI13 215
|
||||
#define CLK_GOUT_CMU_PERIS_BUS 216
|
||||
#define CLK_GOUT_CMU_SRDZ_BUS 217
|
||||
#define CLK_GOUT_CMU_SRDZ_IMGD 218
|
||||
#define CLK_GOUT_CMU_VPU_BUS 219
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_BUS_USER 1
|
||||
#define CLK_MOUT_PERIS_GIC 2
|
||||
#define CLK_GOUT_PERIS_CMU_PERIS_PCLK 3
|
||||
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 4
|
||||
#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS 5
|
||||
#define CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK 6
|
||||
#define CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK 7
|
||||
#define CLK_GOUT_PERIS_BUSIF_TMU_PCLK 8
|
||||
#define CLK_GOUT_PERIS_GIC_CLK 9
|
||||
#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK 10
|
||||
#define CLK_GOUT_PERIS_MCT_PCLK 11
|
||||
#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 12
|
||||
#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 13
|
||||
#define CLK_GOUT_PERIS_PMU_PERIS_PCLK 14
|
||||
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK 15
|
||||
#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK 16
|
||||
#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 17
|
||||
#define CLK_GOUT_PERIS_TZPC00_PCLK 18
|
||||
#define CLK_GOUT_PERIS_TZPC01_PCLK 19
|
||||
#define CLK_GOUT_PERIS_TZPC02_PCLK 20
|
||||
#define CLK_GOUT_PERIS_TZPC03_PCLK 21
|
||||
#define CLK_GOUT_PERIS_TZPC04_PCLK 22
|
||||
#define CLK_GOUT_PERIS_TZPC05_PCLK 23
|
||||
#define CLK_GOUT_PERIS_TZPC06_PCLK 24
|
||||
#define CLK_GOUT_PERIS_TZPC07_PCLK 25
|
||||
#define CLK_GOUT_PERIS_TZPC08_PCLK 26
|
||||
#define CLK_GOUT_PERIS_TZPC09_PCLK 27
|
||||
#define CLK_GOUT_PERIS_TZPC10_PCLK 28
|
||||
#define CLK_GOUT_PERIS_TZPC11_PCLK 29
|
||||
#define CLK_GOUT_PERIS_TZPC12_PCLK 30
|
||||
#define CLK_GOUT_PERIS_TZPC13_PCLK 31
|
||||
#define CLK_GOUT_PERIS_TZPC14_PCLK 32
|
||||
#define CLK_GOUT_PERIS_TZPC15_PCLK 33
|
||||
#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 34
|
||||
#define CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK 35
|
||||
#define CLK_GOUT_PERIS_XIU_P_PERIS_ACLK 36
|
||||
|
||||
/* CMU_FSYS0 */
|
||||
#define CLK_MOUT_FSYS0_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS0_DPGTC_USER 2
|
||||
#define CLK_MOUT_FSYS0_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS0_UFS_EMBD_USER 4
|
||||
#define CLK_MOUT_FSYS0_USBDRD30_USER 5
|
||||
#define CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK 6
|
||||
#define CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK 7
|
||||
#define CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK 8
|
||||
#define CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK 9
|
||||
#define CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK 10
|
||||
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK 11
|
||||
#define CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK 12
|
||||
#define CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK 13
|
||||
#define CLK_GOUT_FSYS0_DP_LINK_I_PCLK 14
|
||||
#define CLK_GOUT_FSYS0_ETR_MIU_I_ACLK 15
|
||||
#define CLK_GOUT_FSYS0_ETR_MIU_I_PCLK 16
|
||||
#define CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK 17
|
||||
#define CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK 18
|
||||
#define CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK 19
|
||||
#define CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK 20
|
||||
#define CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK 21
|
||||
#define CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK 22
|
||||
#define CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN 23
|
||||
#define CLK_GOUT_FSYS0_PMU_FSYS0_PCLK 24
|
||||
#define CLK_GOUT_FSYS0_BCM_FSYS0_ACLK 25
|
||||
#define CLK_GOUT_FSYS0_BCM_FSYS0_PCLK 26
|
||||
#define CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK 27
|
||||
#define CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK 28
|
||||
#define CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK 29
|
||||
#define CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO 30
|
||||
#define CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK 31
|
||||
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK 32
|
||||
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK 33
|
||||
#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK 34
|
||||
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK 35
|
||||
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK 36
|
||||
#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK 37
|
||||
#define CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK 38
|
||||
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK 39
|
||||
#define CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK 40
|
||||
#define CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK 41
|
||||
|
||||
/* CMU_FSYS1 */
|
||||
#define CLK_MOUT_FSYS1_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS1_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS1_PCIE_USER 3
|
||||
#define CLK_MOUT_FSYS1_UFS_CARD_USER 4
|
||||
#define CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN 5
|
||||
#define CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM 6
|
||||
#define CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK 7
|
||||
#define CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK 8
|
||||
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK 9
|
||||
#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK 10
|
||||
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK 11
|
||||
#define CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK 12
|
||||
#define CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK 13
|
||||
#define CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK 14
|
||||
#define CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK 15
|
||||
#define CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK 16
|
||||
#define CLK_GOUT_FSYS1_MMC_CARD_I_ACLK 17
|
||||
#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 18
|
||||
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0 19
|
||||
#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1 20
|
||||
#define CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK 21
|
||||
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0 22
|
||||
#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1 23
|
||||
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 24
|
||||
#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK 25
|
||||
#define CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL 26
|
||||
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0 27
|
||||
#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1 28
|
||||
#define CLK_GOUT_FSYS1_PMU_FSYS1_PCLK 29
|
||||
#define CLK_GOUT_FSYS1_BCM_FSYS1_ACLK 30
|
||||
#define CLK_GOUT_FSYS1_BCM_FSYS1_PCLK 31
|
||||
#define CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK 32
|
||||
#define CLK_GOUT_FSYS1_RTIC_I_ACLK 33
|
||||
#define CLK_GOUT_FSYS1_RTIC_I_PCLK 34
|
||||
#define CLK_GOUT_FSYS1_SSS_I_ACLK 35
|
||||
#define CLK_GOUT_FSYS1_SSS_I_PCLK 36
|
||||
#define CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK 37
|
||||
#define CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK 38
|
||||
#define CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK 39
|
||||
#define CLK_GOUT_FSYS1_UFS_CARD_I_ACLK 40
|
||||
#define CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO 41
|
||||
#define CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK 42
|
||||
#define CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK 43
|
||||
#define CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK 44
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC0_UART_DBG_USER 2
|
||||
#define CLK_MOUT_PERIC0_USI00_USER 3
|
||||
#define CLK_MOUT_PERIC0_USI01_USER 4
|
||||
#define CLK_MOUT_PERIC0_USI02_USER 5
|
||||
#define CLK_MOUT_PERIC0_USI03_USER 6
|
||||
#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 7
|
||||
#define CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK 8
|
||||
#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 9
|
||||
#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 10
|
||||
#define CLK_GOUT_PERIC0_PMU_PERIC0_PCLK 11
|
||||
#define CLK_GOUT_PERIC0_PWM_I_PCLK_S0 12
|
||||
#define CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK 13
|
||||
#define CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK 14
|
||||
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 15
|
||||
#define CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK 16
|
||||
#define CLK_GOUT_PERIC0_UART_DBG_PCLK 17
|
||||
#define CLK_GOUT_PERIC0_USI00_I_PCLK 18
|
||||
#define CLK_GOUT_PERIC0_USI00_I_SCLK_USI 19
|
||||
#define CLK_GOUT_PERIC0_USI01_I_PCLK 20
|
||||
#define CLK_GOUT_PERIC0_USI01_I_SCLK_USI 21
|
||||
#define CLK_GOUT_PERIC0_USI02_I_PCLK 22
|
||||
#define CLK_GOUT_PERIC0_USI02_I_SCLK_USI 23
|
||||
#define CLK_GOUT_PERIC0_USI03_I_PCLK 24
|
||||
#define CLK_GOUT_PERIC0_USI03_I_SCLK_USI 25
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC1_SPEEDY2_USER 2
|
||||
#define CLK_MOUT_PERIC1_SPI_CAM0_USER 3
|
||||
#define CLK_MOUT_PERIC1_SPI_CAM1_USER 4
|
||||
#define CLK_MOUT_PERIC1_UART_BT_USER 5
|
||||
#define CLK_MOUT_PERIC1_USI04_USER 6
|
||||
#define CLK_MOUT_PERIC1_USI05_USER 7
|
||||
#define CLK_MOUT_PERIC1_USI06_USER 8
|
||||
#define CLK_MOUT_PERIC1_USI07_USER 9
|
||||
#define CLK_MOUT_PERIC1_USI08_USER 10
|
||||
#define CLK_MOUT_PERIC1_USI09_USER 11
|
||||
#define CLK_MOUT_PERIC1_USI10_USER 12
|
||||
#define CLK_MOUT_PERIC1_USI11_USER 13
|
||||
#define CLK_MOUT_PERIC1_USI12_USER 14
|
||||
#define CLK_MOUT_PERIC1_USI13_USER 15
|
||||
#define CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK 16
|
||||
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK 17
|
||||
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK 18
|
||||
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK 19
|
||||
#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK 20
|
||||
#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 21
|
||||
#define CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK 22
|
||||
#define CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK 23
|
||||
#define CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK 24
|
||||
#define CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK 25
|
||||
#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 26
|
||||
#define CLK_GOUT_PERIC1_PMU_PERIC1_PCLK 27
|
||||
#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK 28
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK 29
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK 30
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK 31
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK 32
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK 33
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK 34
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK 35
|
||||
#define CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK 36
|
||||
#define CLK_GOUT_PERIC1_SPI_CAM0_PCLK 37
|
||||
#define CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK 38
|
||||
#define CLK_GOUT_PERIC1_SPI_CAM1_PCLK 39
|
||||
#define CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK 40
|
||||
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 41
|
||||
#define CLK_GOUT_PERIC1_UART_BT_EXT_UCLK 42
|
||||
#define CLK_GOUT_PERIC1_UART_BT_PCLK 43
|
||||
#define CLK_GOUT_PERIC1_USI04_I_PCLK 44
|
||||
#define CLK_GOUT_PERIC1_USI04_I_SCLK_USI 45
|
||||
#define CLK_GOUT_PERIC1_USI05_I_PCLK 46
|
||||
#define CLK_GOUT_PERIC1_USI05_I_SCLK_USI 47
|
||||
#define CLK_GOUT_PERIC1_USI06_I_PCLK 48
|
||||
#define CLK_GOUT_PERIC1_USI06_I_SCLK_USI 49
|
||||
#define CLK_GOUT_PERIC1_USI07_I_PCLK 50
|
||||
#define CLK_GOUT_PERIC1_USI07_I_SCLK_USI 51
|
||||
#define CLK_GOUT_PERIC1_USI08_I_PCLK 52
|
||||
#define CLK_GOUT_PERIC1_USI08_I_SCLK_USI 53
|
||||
#define CLK_GOUT_PERIC1_USI09_I_PCLK 54
|
||||
#define CLK_GOUT_PERIC1_USI09_I_SCLK_USI 55
|
||||
#define CLK_GOUT_PERIC1_USI10_I_PCLK 56
|
||||
#define CLK_GOUT_PERIC1_USI10_I_SCLK_USI 57
|
||||
#define CLK_GOUT_PERIC1_USI11_I_PCLK 58
|
||||
#define CLK_GOUT_PERIC1_USI11_I_SCLK_USI 59
|
||||
#define CLK_GOUT_PERIC1_USI12_I_PCLK 60
|
||||
#define CLK_GOUT_PERIC1_USI12_I_SCLK_USI 61
|
||||
#define CLK_GOUT_PERIC1_USI13_I_PCLK 62
|
||||
#define CLK_GOUT_PERIC1_USI13_I_SCLK_USI 63
|
||||
#define CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK 64
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS8895_H */
|
||||
@@ -160,6 +160,7 @@
|
||||
#define DOUT_CLKCMU_SNW_NOC 144
|
||||
#define DOUT_CLKCMU_SSP_NOC 145
|
||||
#define DOUT_CLKCMU_TAA_NOC 146
|
||||
#define DOUT_TCXO_DIV2 147
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_IP_USER 1
|
||||
@@ -188,4 +189,50 @@
|
||||
#define CLK_DOUT_PERIC0_USI_I2C 23
|
||||
#define CLK_DOUT_PERIC0_I3C 24
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_IP_USER 1
|
||||
#define CLK_MOUT_PERIC1_NOC_USER 2
|
||||
#define CLK_MOUT_PERIC1_USI09_USI 3
|
||||
#define CLK_MOUT_PERIC1_USI10_USI 4
|
||||
#define CLK_MOUT_PERIC1_USI11_USI 5
|
||||
#define CLK_MOUT_PERIC1_USI12_USI 6
|
||||
#define CLK_MOUT_PERIC1_USI13_USI 7
|
||||
#define CLK_MOUT_PERIC1_USI14_USI 8
|
||||
#define CLK_MOUT_PERIC1_USI15_USI 9
|
||||
#define CLK_MOUT_PERIC1_USI16_USI 10
|
||||
#define CLK_MOUT_PERIC1_USI17_USI 11
|
||||
#define CLK_MOUT_PERIC1_USI_I2C 12
|
||||
#define CLK_MOUT_PERIC1_I3C 13
|
||||
|
||||
#define CLK_DOUT_PERIC1_USI09_USI 14
|
||||
#define CLK_DOUT_PERIC1_USI10_USI 15
|
||||
#define CLK_DOUT_PERIC1_USI11_USI 16
|
||||
#define CLK_DOUT_PERIC1_USI12_USI 17
|
||||
#define CLK_DOUT_PERIC1_USI13_USI 18
|
||||
#define CLK_DOUT_PERIC1_USI14_USI 19
|
||||
#define CLK_DOUT_PERIC1_USI15_USI 20
|
||||
#define CLK_DOUT_PERIC1_USI16_USI 21
|
||||
#define CLK_DOUT_PERIC1_USI17_USI 22
|
||||
#define CLK_DOUT_PERIC1_USI_I2C 23
|
||||
#define CLK_DOUT_PERIC1_I3C 24
|
||||
|
||||
/* CMU_MISC */
|
||||
#define CLK_MOUT_MISC_NOC_USER 1
|
||||
#define CLK_MOUT_MISC_GIC 2
|
||||
|
||||
#define CLK_DOUT_MISC_OTP 3
|
||||
#define CLK_DOUT_MISC_NOCP 4
|
||||
#define CLK_DOUT_MISC_OSC_DIV2 5
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_MOUT_HSI0_NOC_USER 1
|
||||
|
||||
#define CLK_DOUT_HSI0_PCIE_APB 2
|
||||
|
||||
/* CMU_HSI1 */
|
||||
#define CLK_MOUT_HSI1_MMC_CARD_USER 1
|
||||
#define CLK_MOUT_HSI1_NOC_USER 2
|
||||
#define CLK_MOUT_HSI1_USBDRD_USER 3
|
||||
#define CLK_MOUT_HSI1_USBDRD 4
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
|
||||
|
||||
Reference in New Issue
Block a user