Merge tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:
- Tesla FSD: Expose CSI clocks to consumers (DTS)
- Exynos990:
- Few fixes for fixed factor clocks, register widths and proper PLL
parents
- Add four more clocks for the DPU and HSI0 clock for USB
- Add PERIC0 and PERIC1 clock controllers (CMU), responsible for
providing clocks to serial engines
- Add seven clock controllers for the new Axis ARTPEC-8 SoC. The SoC
shares all main blocks, including the clock controllers, with Samsung
SoC, so same drivers and bindings are used.
- Cleanups: switch to clk_ops::determine_rate()
* tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
clk: samsung: exynos990: Add missing USB clock registers to HSI0
clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
dt-bindings: clock: Add ARTPEC-8 clock controller
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
clk: samsung: pll: convert from round_rate() to determine_rate()
clk: samsung: cpu: convert from round_rate() to determine_rate()
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
dt-bindings: clock: Add CAM_CSI clock macro for FSD
This commit is contained in:
Stephen Boyd
213
Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
Normal file
213
Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
Normal file
@@ -0,0 +1,213 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Axis ARTPEC-8 SoC clock controller
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maintainers:
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- Jesper Nilsson <jesper.nilsson@axis.com>
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description: |
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ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
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units, generating clocks for different domains. Those CMU units are modeled
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as separate device tree nodes, and might depend on each other.
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The root clock in that root tree is an external clock: OSCCLK (25 MHz).
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This external clock must be defined as a fixed-rate clock in dts.
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CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_CMU.
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|
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/axis,artpec8-clk.h' header.
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|
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properties:
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compatible:
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enum:
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- axis,artpec8-cmu-cmu
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- axis,artpec8-cmu-bus
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- axis,artpec8-cmu-core
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- axis,artpec8-cmu-cpucl
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- axis,artpec8-cmu-fsys
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- axis,artpec8-cmu-imem
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- axis,artpec8-cmu-peri
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reg:
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maxItems: 1
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||||
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clocks:
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minItems: 1
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 5
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||||
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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|
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allOf:
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-cmu
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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clock-names:
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items:
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- const: fin_pll
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|
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-bus
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then:
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properties:
|
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_BUS BUS clock (from CMU_CMU)
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- description: CMU_BUS DLP clock (from CMU_CMU)
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|
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clock-names:
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items:
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- const: fin_pll
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- const: bus
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- const: dlp
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-core
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_CORE main clock (from CMU_CMU)
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- description: CMU_CORE DLP clock (from CMU_CMU)
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clock-names:
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items:
|
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- const: fin_pll
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- const: main
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- const: dlp
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-cpucl
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_CPUCL switch clock (from CMU_CMU)
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|
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clock-names:
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items:
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- const: fin_pll
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- const: switch
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-fsys
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then:
|
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properties:
|
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clocks:
|
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items:
|
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- description: External reference clock (25 MHz)
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- description: CMU_FSYS SCAN0 clock (from CMU_CMU)
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- description: CMU_FSYS SCAN1 clock (from CMU_CMU)
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- description: CMU_FSYS BUS clock (from CMU_CMU)
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- description: CMU_FSYS IP clock (from CMU_CMU)
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|
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clock-names:
|
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items:
|
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- const: fin_pll
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- const: scan0
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- const: scan1
|
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- const: bus
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- const: ip
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|
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-imem
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then:
|
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properties:
|
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clocks:
|
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items:
|
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- description: External reference clock (25 MHz)
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- description: CMU_IMEM ACLK clock (from CMU_CMU)
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- description: CMU_IMEM JPEG clock (from CMU_CMU)
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clock-names:
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||||
items:
|
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- const: fin_pll
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- const: aclk
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- const: jpeg
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|
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- if:
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properties:
|
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compatible:
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const: axis,artpec8-cmu-peri
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|
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then:
|
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_PERI IP clock (from CMU_CMU)
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- description: CMU_PERI AUDIO clock (from CMU_CMU)
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- description: CMU_PERI DISP clock (from CMU_CMU)
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|
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clock-names:
|
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items:
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- const: fin_pll
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- const: ip
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- const: audio
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- const: disp
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additionalProperties: false
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examples:
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# Clock controller node for CMU_FSYS
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- |
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#include <dt-bindings/clock/axis,artpec8-clk.h>
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cmu_fsys: clock-controller@16c10000 {
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compatible = "axis,artpec8-cmu-fsys";
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reg = <0x16c10000 0x4000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
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<&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
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clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
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};
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...
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@@ -30,6 +30,8 @@ description: |
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properties:
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compatible:
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enum:
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- samsung,exynos990-cmu-peric1
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- samsung,exynos990-cmu-peric0
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- samsung,exynos990-cmu-hsi0
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- samsung,exynos990-cmu-peris
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- samsung,exynos990-cmu-top
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@@ -56,6 +58,28 @@ required:
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- reg
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allOf:
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- if:
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||||
properties:
|
||||
compatible:
|
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contains:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-peric1
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- samsung,exynos990-cmu-peric0
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|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
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||||
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
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||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
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- const: bus
|
||||
- const: ip
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||||
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||||
- if:
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properties:
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||||
compatible:
|
||||
|
||||
@@ -13,6 +13,7 @@ obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o
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obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
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obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5420.o
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obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-artpec8.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
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obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
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obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
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|
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1044
drivers/clk/samsung/clk-artpec8.c
Normal file
1044
drivers/clk/samsung/clk-artpec8.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -567,12 +567,14 @@ static int exynos850_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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/* -------------------------------------------------------------------------- */
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/* Common round rate callback usable for all types of CPU clocks */
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static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate)
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static int exynos_cpuclk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_hw *parent = clk_hw_get_parent(hw);
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*prate = clk_hw_round_rate(parent, drate);
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return *prate;
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req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
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req->rate = req->best_parent_rate;
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return 0;
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}
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/* Common recalc rate callback usable for all types of CPU clocks */
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@@ -591,7 +593,7 @@ static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
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static const struct clk_ops exynos_cpuclk_clk_ops = {
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.recalc_rate = exynos_cpuclk_recalc_rate,
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.round_rate = exynos_cpuclk_round_rate,
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.determine_rate = exynos_cpuclk_determine_rate,
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};
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/*
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File diff suppressed because it is too large
Load Diff
@@ -89,7 +89,7 @@
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#define CLKS_NR_FSYS1 (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1)
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#define CLKS_NR_IMEM (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1)
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#define CLKS_NR_MFC (MFC_MFC_IPCLKPORT_ACLK + 1)
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#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_ACLK + 1)
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#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_PCLK + 1)
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static const unsigned long cmu_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_SHARED0,
|
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@@ -1646,7 +1646,7 @@ static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst
|
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};
|
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|
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static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
|
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PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
|
||||
PLL(pll_142xx, CAM_CSI_PLL, "fout_pll_cam_csi", "fin_pll",
|
||||
PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
|
||||
};
|
||||
|
||||
@@ -1682,51 +1682,51 @@ static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
|
||||
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
|
||||
GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI0_0_IPCLKPORT_I_PCLK, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
|
||||
GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI0_1_IPCLKPORT_I_PCLK, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
|
||||
GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI0_2_IPCLKPORT_I_PCLK, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
|
||||
GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI0_3_IPCLKPORT_I_PCLK, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
|
||||
GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI1_0_IPCLKPORT_I_PCLK, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
|
||||
GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI1_1_IPCLKPORT_I_PCLK, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
|
||||
GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI1_2_IPCLKPORT_I_PCLK, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
|
||||
GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI1_3_IPCLKPORT_I_PCLK, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
|
||||
GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI2_0_IPCLKPORT_I_PCLK, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
|
||||
GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI2_1_IPCLKPORT_I_PCLK, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
|
||||
GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI2_2_IPCLKPORT_I_PCLK, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
|
||||
GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GATE(CAM_CSI2_3_IPCLKPORT_I_PCLK, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
|
||||
GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
|
||||
"dout_cam_csi_busd",
|
||||
|
||||
@@ -49,8 +49,8 @@ static const struct samsung_pll_rate_table *samsung_get_pll_settings(
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static long samsung_pll_round_rate(struct clk_hw *hw,
|
||||
unsigned long drate, unsigned long *prate)
|
||||
static int samsung_pll_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct samsung_clk_pll *pll = to_clk_pll(hw);
|
||||
const struct samsung_pll_rate_table *rate_table = pll->rate_table;
|
||||
@@ -58,12 +58,17 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
|
||||
|
||||
/* Assuming rate_table is in descending order */
|
||||
for (i = 0; i < pll->rate_count; i++) {
|
||||
if (drate >= rate_table[i].rate)
|
||||
return rate_table[i].rate;
|
||||
if (req->rate >= rate_table[i].rate) {
|
||||
req->rate = rate_table[i].rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* return minimum supported value */
|
||||
return rate_table[i - 1].rate;
|
||||
req->rate = rate_table[i - 1].rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool pll_early_timeout = true;
|
||||
@@ -273,7 +278,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
}
|
||||
|
||||
/* Set PLL lock time. */
|
||||
if (pll->type == pll_142xx)
|
||||
if (pll->type == pll_142xx || pll->type == pll_1017x)
|
||||
writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
|
||||
pll->lock_reg);
|
||||
else
|
||||
@@ -298,7 +303,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
static const struct clk_ops samsung_pll35xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll35xx_recalc_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.set_rate = samsung_pll35xx_set_rate,
|
||||
.enable = samsung_pll3xxx_enable,
|
||||
.disable = samsung_pll3xxx_disable,
|
||||
@@ -411,7 +416,7 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
static const struct clk_ops samsung_pll36xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll36xx_recalc_rate,
|
||||
.set_rate = samsung_pll36xx_set_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.enable = samsung_pll3xxx_enable,
|
||||
.disable = samsung_pll3xxx_disable,
|
||||
};
|
||||
@@ -514,7 +519,7 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
static const struct clk_ops samsung_pll0822x_clk_ops = {
|
||||
.recalc_rate = samsung_pll0822x_recalc_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.set_rate = samsung_pll0822x_set_rate,
|
||||
.enable = samsung_pll3xxx_enable,
|
||||
.disable = samsung_pll3xxx_disable,
|
||||
@@ -612,7 +617,7 @@ static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
static const struct clk_ops samsung_pll0831x_clk_ops = {
|
||||
.recalc_rate = samsung_pll0831x_recalc_rate,
|
||||
.set_rate = samsung_pll0831x_set_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.enable = samsung_pll3xxx_enable,
|
||||
.disable = samsung_pll3xxx_disable,
|
||||
};
|
||||
@@ -735,7 +740,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
static const struct clk_ops samsung_pll45xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll45xx_recalc_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.set_rate = samsung_pll45xx_set_rate,
|
||||
};
|
||||
|
||||
@@ -880,7 +885,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
static const struct clk_ops samsung_pll46xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll46xx_recalc_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.set_rate = samsung_pll46xx_set_rate,
|
||||
};
|
||||
|
||||
@@ -1093,7 +1098,7 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
static const struct clk_ops samsung_pll2550xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll2550xx_recalc_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.set_rate = samsung_pll2550xx_set_rate,
|
||||
};
|
||||
|
||||
@@ -1185,7 +1190,7 @@ static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
static const struct clk_ops samsung_pll2650x_clk_ops = {
|
||||
.recalc_rate = samsung_pll2650x_recalc_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.set_rate = samsung_pll2650x_set_rate,
|
||||
};
|
||||
|
||||
@@ -1277,7 +1282,7 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
static const struct clk_ops samsung_pll2650xx_clk_ops = {
|
||||
.recalc_rate = samsung_pll2650xx_recalc_rate,
|
||||
.set_rate = samsung_pll2650xx_set_rate,
|
||||
.round_rate = samsung_pll_round_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
|
||||
@@ -1325,6 +1330,125 @@ static const struct clk_ops samsung_pll531x_clk_ops = {
|
||||
.recalc_rate = samsung_pll531x_recalc_rate,
|
||||
};
|
||||
|
||||
/*
|
||||
* PLL1031x Clock Type
|
||||
*/
|
||||
#define PLL1031X_LOCK_FACTOR (500)
|
||||
|
||||
#define PLL1031X_MDIV_MASK (0x3ff)
|
||||
#define PLL1031X_PDIV_MASK (0x3f)
|
||||
#define PLL1031X_SDIV_MASK (0x7)
|
||||
#define PLL1031X_MDIV_SHIFT (16)
|
||||
#define PLL1031X_PDIV_SHIFT (8)
|
||||
#define PLL1031X_SDIV_SHIFT (0)
|
||||
|
||||
#define PLL1031X_KDIV_MASK (0xffff)
|
||||
#define PLL1031X_KDIV_SHIFT (0)
|
||||
#define PLL1031X_MFR_MASK (0x3f)
|
||||
#define PLL1031X_MRR_MASK (0x1f)
|
||||
#define PLL1031X_MFR_SHIFT (16)
|
||||
#define PLL1031X_MRR_SHIFT (24)
|
||||
|
||||
static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll *pll = to_clk_pll(hw);
|
||||
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3;
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con0 = readl_relaxed(pll->con_reg);
|
||||
pll_con3 = readl_relaxed(pll->con_reg + 0xc);
|
||||
mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK;
|
||||
kdiv = (pll_con3 & PLL1031X_KDIV_MASK);
|
||||
|
||||
fvco *= (mdiv << PLL1031X_MDIV_SHIFT) + kdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
fvco >>= PLL1031X_MDIV_SHIFT;
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3,
|
||||
const struct samsung_pll_rate_table *rate)
|
||||
{
|
||||
u32 old_mdiv, old_pdiv, old_kdiv;
|
||||
|
||||
old_mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
|
||||
old_pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
|
||||
old_kdiv = (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK;
|
||||
|
||||
return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv ||
|
||||
old_kdiv != rate->kdiv);
|
||||
}
|
||||
|
||||
static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct samsung_clk_pll *pll = to_clk_pll(hw);
|
||||
const struct samsung_pll_rate_table *rate;
|
||||
u32 con0, con3;
|
||||
|
||||
/* Get required rate settings from table */
|
||||
rate = samsung_get_pll_settings(pll, drate);
|
||||
if (!rate) {
|
||||
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
|
||||
drate, clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
con0 = readl_relaxed(pll->con_reg);
|
||||
con3 = readl_relaxed(pll->con_reg + 0xc);
|
||||
|
||||
if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) {
|
||||
/* If only s change, change just s value only */
|
||||
con0 &= ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT);
|
||||
con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT;
|
||||
writel_relaxed(con0, pll->con_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set PLL lock time. */
|
||||
writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
|
||||
|
||||
/* Set PLL M, P, and S values. */
|
||||
con0 &= ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) |
|
||||
(PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) |
|
||||
(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT));
|
||||
|
||||
con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) |
|
||||
(rate->pdiv << PLL1031X_PDIV_SHIFT) |
|
||||
(rate->sdiv << PLL1031X_SDIV_SHIFT);
|
||||
|
||||
/* Set PLL K, MFR and MRR values. */
|
||||
con3 = readl_relaxed(pll->con_reg + 0xc);
|
||||
con3 &= ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) |
|
||||
(PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) |
|
||||
(PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT));
|
||||
con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) |
|
||||
(rate->mfr << PLL1031X_MFR_SHIFT) |
|
||||
(rate->mrr << PLL1031X_MRR_SHIFT);
|
||||
|
||||
/* Write configuration to PLL */
|
||||
writel_relaxed(con0, pll->con_reg);
|
||||
writel_relaxed(con3, pll->con_reg + 0xc);
|
||||
|
||||
/* Wait for PLL lock if the PLL is enabled */
|
||||
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll1031x_clk_ops = {
|
||||
.recalc_rate = samsung_pll1031x_recalc_rate,
|
||||
.determine_rate = samsung_pll_determine_rate,
|
||||
.set_rate = samsung_pll1031x_set_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops samsung_pll1031x_clk_min_ops = {
|
||||
.recalc_rate = samsung_pll1031x_recalc_rate,
|
||||
};
|
||||
|
||||
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_pll_clock *pll_clk)
|
||||
{
|
||||
@@ -1373,6 +1497,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
case pll_1451x:
|
||||
case pll_1452x:
|
||||
case pll_142xx:
|
||||
case pll_1017x:
|
||||
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
|
||||
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
|
||||
if (!pll->rate_table)
|
||||
@@ -1468,6 +1593,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
case pll_4311:
|
||||
init.ops = &samsung_pll531x_clk_ops;
|
||||
break;
|
||||
case pll_1031x:
|
||||
if (!pll->rate_table)
|
||||
init.ops = &samsung_pll1031x_clk_min_ops;
|
||||
else
|
||||
init.ops = &samsung_pll1031x_clk_ops;
|
||||
break;
|
||||
default:
|
||||
pr_warn("%s: Unknown pll type for pll clk %s\n",
|
||||
__func__, pll_clk->name);
|
||||
|
||||
@@ -49,6 +49,8 @@ enum samsung_pll_type {
|
||||
pll_0718x,
|
||||
pll_0732x,
|
||||
pll_4311,
|
||||
pll_1017x,
|
||||
pll_1031x,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
||||
169
include/dt-bindings/clock/axis,artpec8-clk.h
Normal file
169
include/dt-bindings/clock/axis,artpec8-clk.h
Normal file
@@ -0,0 +1,169 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
|
||||
* https://www.samsung.com
|
||||
* Copyright (c) 2025 Axis Communications AB.
|
||||
* https://www.axis.com
|
||||
*
|
||||
* Device Tree binding constants for ARTPEC-8 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
|
||||
#define _DT_BINDINGS_CLOCK_ARTPEC8_H
|
||||
|
||||
/* CMU_CMU */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_DOUT_SHARED0_DIV2 2
|
||||
#define CLK_DOUT_SHARED0_DIV3 3
|
||||
#define CLK_DOUT_SHARED0_DIV4 4
|
||||
#define CLK_FOUT_SHARED1_PLL 5
|
||||
#define CLK_DOUT_SHARED1_DIV2 6
|
||||
#define CLK_DOUT_SHARED1_DIV3 7
|
||||
#define CLK_DOUT_SHARED1_DIV4 8
|
||||
#define CLK_FOUT_AUDIO_PLL 9
|
||||
#define CLK_DOUT_CMU_BUS 10
|
||||
#define CLK_DOUT_CMU_BUS_DLP 11
|
||||
#define CLK_DOUT_CMU_CDC_CORE 12
|
||||
#define CLK_DOUT_CMU_OTP 13
|
||||
#define CLK_DOUT_CMU_CORE_MAIN 14
|
||||
#define CLK_DOUT_CMU_CORE_DLP 15
|
||||
#define CLK_DOUT_CMU_CPUCL_SWITCH 16
|
||||
#define CLK_DOUT_CMU_DLP_CORE 17
|
||||
#define CLK_DOUT_CMU_FSYS_BUS 18
|
||||
#define CLK_DOUT_CMU_FSYS_IP 19
|
||||
#define CLK_DOUT_CMU_FSYS_SCAN0 20
|
||||
#define CLK_DOUT_CMU_FSYS_SCAN1 21
|
||||
#define CLK_DOUT_CMU_GPU_3D 22
|
||||
#define CLK_DOUT_CMU_GPU_2D 23
|
||||
#define CLK_DOUT_CMU_IMEM_ACLK 24
|
||||
#define CLK_DOUT_CMU_IMEM_JPEG 25
|
||||
#define CLK_DOUT_CMU_MIF_SWITCH 26
|
||||
#define CLK_DOUT_CMU_MIF_BUSP 27
|
||||
#define CLK_DOUT_CMU_PERI_DISP 28
|
||||
#define CLK_DOUT_CMU_PERI_IP 29
|
||||
#define CLK_DOUT_CMU_PERI_AUDIO 30
|
||||
#define CLK_DOUT_CMU_RSP_CORE 31
|
||||
#define CLK_DOUT_CMU_TRFM_CORE 32
|
||||
#define CLK_DOUT_CMU_VCA_ACE 33
|
||||
#define CLK_DOUT_CMU_VCA_OD 34
|
||||
#define CLK_DOUT_CMU_VIO_CORE 35
|
||||
#define CLK_DOUT_CMU_VIO_AUDIO 36
|
||||
#define CLK_DOUT_CMU_VIP0_CORE 37
|
||||
#define CLK_DOUT_CMU_VIP1_CORE 38
|
||||
#define CLK_DOUT_CMU_VPP_CORE 39
|
||||
|
||||
/* CMU_BUS */
|
||||
#define CLK_MOUT_BUS_ACLK_USER 1
|
||||
#define CLK_MOUT_BUS_DLP_USER 2
|
||||
#define CLK_DOUT_BUS_PCLK 3
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_ACLK_USER 1
|
||||
#define CLK_MOUT_CORE_DLP_USER 2
|
||||
#define CLK_DOUT_CORE_PCLK 3
|
||||
|
||||
/* CMU_CPUCL */
|
||||
#define CLK_FOUT_CPUCL_PLL 1
|
||||
#define CLK_MOUT_CPUCL_PLL 2
|
||||
#define CLK_MOUT_CPUCL_SWITCH_USER 3
|
||||
#define CLK_DOUT_CPUCL_CPU 4
|
||||
#define CLK_DOUT_CPUCL_CLUSTER_ACLK 5
|
||||
#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG 6
|
||||
#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK 7
|
||||
#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 8
|
||||
#define CLK_DOUT_CPUCL_PCLK 9
|
||||
#define CLK_DOUT_CPUCL_CMUREF 10
|
||||
#define CLK_DOUT_CPUCL_DBG 11
|
||||
#define CLK_DOUT_CPUCL_PCLKDBG 12
|
||||
#define CLK_GOUT_CPUCL_CLUSTER_CPU 13
|
||||
#define CLK_GOUT_CPUCL_SHORTSTOP 14
|
||||
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 15
|
||||
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 16
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_FOUT_FSYS_PLL 1
|
||||
#define CLK_MOUT_FSYS_SCAN0_USER 2
|
||||
#define CLK_MOUT_FSYS_SCAN1_USER 3
|
||||
#define CLK_MOUT_FSYS_BUS_USER 4
|
||||
#define CLK_MOUT_FSYS_MMC_USER 5
|
||||
#define CLK_DOUT_FSYS_PCIE_PIPE 6
|
||||
#define CLK_DOUT_FSYS_ADC 7
|
||||
#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8
|
||||
#define CLK_DOUT_FSYS_EQOS_INT125 9
|
||||
#define CLK_DOUT_FSYS_OTP_MEM 10
|
||||
#define CLK_DOUT_FSYS_SCLK_UART 11
|
||||
#define CLK_DOUT_FSYS_EQOS_25 12
|
||||
#define CLK_DOUT_FSYS_EQOS_2p5 13
|
||||
#define CLK_DOUT_FSYS_BUS300 14
|
||||
#define CLK_DOUT_FSYS_BUS_QSPI 15
|
||||
#define CLK_DOUT_FSYS_MMC_CARD0 16
|
||||
#define CLK_DOUT_FSYS_MMC_CARD1 17
|
||||
#define CLK_DOUT_SCAN_CLK_FSYS_125 18
|
||||
#define CLK_DOUT_FSYS_QSPI 19
|
||||
#define CLK_DOUT_FSYS_SFMC_NAND 20
|
||||
#define CLK_DOUT_FSYS_SCAN_CLK_MMC 21
|
||||
#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 22
|
||||
#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 23
|
||||
#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK 24
|
||||
#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK 25
|
||||
#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK 26
|
||||
#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK 27
|
||||
#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0 28
|
||||
#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 29
|
||||
#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG 30
|
||||
#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 31
|
||||
#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK 32
|
||||
#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I 33
|
||||
#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I 34
|
||||
#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5 35
|
||||
#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND 36
|
||||
#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN 37
|
||||
#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK 38
|
||||
#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN 39
|
||||
#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK 40
|
||||
#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN 41
|
||||
#define CLK_GOUT_FSYS_UART0_PCLK 42
|
||||
#define CLK_GOUT_FSYS_UART0_SCLK_UART 43
|
||||
#define CLK_GOUT_FSYS_BUS_QSPI 44
|
||||
#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK 45
|
||||
#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK 46
|
||||
|
||||
/* CMU_IMEM */
|
||||
#define CLK_MOUT_IMEM_ACLK_USER 1
|
||||
#define CLK_MOUT_IMEM_GIC_CA53 2
|
||||
#define CLK_MOUT_IMEM_GIC_CA5 3
|
||||
#define CLK_MOUT_IMEM_JPEG_USER 4
|
||||
#define CLK_GOUT_IMEM_MCT_PCLK 5
|
||||
#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 6
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_MOUT_PERI_IP_USER 1
|
||||
#define CLK_MOUT_PERI_AUDIO_USER 2
|
||||
#define CLK_MOUT_PERI_I2S0 3
|
||||
#define CLK_MOUT_PERI_I2S1 4
|
||||
#define CLK_MOUT_PERI_DISP_USER 5
|
||||
#define CLK_DOUT_PERI_SPI 6
|
||||
#define CLK_DOUT_PERI_UART1 7
|
||||
#define CLK_DOUT_PERI_UART2 8
|
||||
#define CLK_DOUT_PERI_PCLK 9
|
||||
#define CLK_DOUT_PERI_I2S0 10
|
||||
#define CLK_DOUT_PERI_I2S1 11
|
||||
#define CLK_DOUT_PERI_DSIM 12
|
||||
#define CLK_GOUT_PERI_UART1_PCLK 13
|
||||
#define CLK_GOUT_PERI_UART1_SCLK_UART 14
|
||||
#define CLK_GOUT_PERI_UART2_PCLK 15
|
||||
#define CLK_GOUT_PERI_UART2_SCLK_UART 16
|
||||
#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 17
|
||||
#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 18
|
||||
#define CLK_GOUT_PERI_SPI0_PCLK 19
|
||||
#define CLK_GOUT_PERI_SPI0_SCLK_SPI 20
|
||||
#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 21
|
||||
#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST 22
|
||||
#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST 23
|
||||
#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK 24
|
||||
#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK 25
|
||||
#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK 26
|
||||
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 27
|
||||
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 28
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */
|
||||
@@ -139,5 +139,18 @@
|
||||
#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
|
||||
#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
|
||||
#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
|
||||
#define CAM_CSI_PLL 13
|
||||
#define CAM_CSI0_0_IPCLKPORT_I_PCLK 14
|
||||
#define CAM_CSI0_1_IPCLKPORT_I_PCLK 15
|
||||
#define CAM_CSI0_2_IPCLKPORT_I_PCLK 16
|
||||
#define CAM_CSI0_3_IPCLKPORT_I_PCLK 17
|
||||
#define CAM_CSI1_0_IPCLKPORT_I_PCLK 18
|
||||
#define CAM_CSI1_1_IPCLKPORT_I_PCLK 19
|
||||
#define CAM_CSI1_2_IPCLKPORT_I_PCLK 20
|
||||
#define CAM_CSI1_3_IPCLKPORT_I_PCLK 21
|
||||
#define CAM_CSI2_0_IPCLKPORT_I_PCLK 22
|
||||
#define CAM_CSI2_1_IPCLKPORT_I_PCLK 23
|
||||
#define CAM_CSI2_2_IPCLKPORT_I_PCLK 24
|
||||
#define CAM_CSI2_3_IPCLKPORT_I_PCLK 25
|
||||
|
||||
#endif /*_DT_BINDINGS_CLOCK_FSD_H */
|
||||
|
||||
@@ -208,6 +208,10 @@
|
||||
#define CLK_GOUT_CMU_SSP_BUS 197
|
||||
#define CLK_GOUT_CMU_TNR_BUS 198
|
||||
#define CLK_GOUT_CMU_VRA_BUS 199
|
||||
#define CLK_MOUT_CMU_CMUREF 200
|
||||
#define CLK_MOUT_CMU_DPU_BUS 201
|
||||
#define CLK_MOUT_CMU_CLK_CMUREF 202
|
||||
#define CLK_DOUT_CMU_CLK_CMUREF 203
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_MOUT_HSI0_BUS_USER 1
|
||||
@@ -232,6 +236,183 @@
|
||||
#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK 20
|
||||
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
|
||||
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
|
||||
#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK 23
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC0_UART_DBG 2
|
||||
#define CLK_MOUT_PERIC0_USI00_USI_USER 3
|
||||
#define CLK_MOUT_PERIC0_USI01_USI_USER 4
|
||||
#define CLK_MOUT_PERIC0_USI02_USI_USER 5
|
||||
#define CLK_MOUT_PERIC0_USI03_USI_USER 6
|
||||
#define CLK_MOUT_PERIC0_USI04_USI_USER 7
|
||||
#define CLK_MOUT_PERIC0_USI05_USI_USER 8
|
||||
#define CLK_MOUT_PERIC0_USI13_USI_USER 9
|
||||
#define CLK_MOUT_PERIC0_USI14_USI_USER 10
|
||||
#define CLK_MOUT_PERIC0_USI15_USI_USER 11
|
||||
#define CLK_MOUT_PERIC0_USI_I2C_USER 12
|
||||
#define CLK_DOUT_PERIC0_UART_DBG 13
|
||||
#define CLK_DOUT_PERIC0_USI00_USI 14
|
||||
#define CLK_DOUT_PERIC0_USI01_USI 15
|
||||
#define CLK_DOUT_PERIC0_USI02_USI 16
|
||||
#define CLK_DOUT_PERIC0_USI03_USI 17
|
||||
#define CLK_DOUT_PERIC0_USI04_USI 18
|
||||
#define CLK_DOUT_PERIC0_USI05_USI 19
|
||||
#define CLK_DOUT_PERIC0_USI13_USI 20
|
||||
#define CLK_DOUT_PERIC0_USI14_USI 21
|
||||
#define CLK_DOUT_PERIC0_USI15_USI 22
|
||||
#define CLK_DOUT_PERIC0_USI_I2C 23
|
||||
#define CLK_GOUT_PERIC0_CMU_PCLK 24
|
||||
#define CLK_GOUT_PERIC0_OSCCLK_CLK 25
|
||||
#define CLK_GOUT_PERIC0_D_TZPC_PCLK 26
|
||||
#define CLK_GOUT_PERIC0_GPIO_PCLK 27
|
||||
#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 28
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 29
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 30
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 31
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 32
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 33
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 34
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 35
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 36
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 37
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 38
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 39
|
||||
#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 40
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_10 41
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_11 42
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_12 43
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_13 44
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_14 45
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_15 46
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_4 47
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_5 48
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_6 49
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_7 50
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_8 51
|
||||
#define CLK_GOUT_PERIC0_TOP0_PCLK_9 52
|
||||
#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 53
|
||||
#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 54
|
||||
#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 55
|
||||
#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 56
|
||||
#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 57
|
||||
#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 58
|
||||
#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 59
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_0 60
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_15 61
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_3 62
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_4 63
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_5 64
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_6 65
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_7 66
|
||||
#define CLK_GOUT_PERIC0_TOP1_PCLK_8 67
|
||||
#define CLK_GOUT_PERIC0_BUSP_CLK 68
|
||||
#define CLK_GOUT_PERIC0_UART_DBG_CLK 69
|
||||
#define CLK_GOUT_PERIC0_USI00_USI_CLK 70
|
||||
#define CLK_GOUT_PERIC0_USI01_USI_CLK 71
|
||||
#define CLK_GOUT_PERIC0_USI02_USI_CLK 72
|
||||
#define CLK_GOUT_PERIC0_USI03_USI_CLK 73
|
||||
#define CLK_GOUT_PERIC0_USI04_USI_CLK 74
|
||||
#define CLK_GOUT_PERIC0_USI05_USI_CLK 75
|
||||
#define CLK_GOUT_PERIC0_USI13_USI_CLK 76
|
||||
#define CLK_GOUT_PERIC0_USI14_USI_CLK 77
|
||||
#define CLK_GOUT_PERIC0_USI15_USI_CLK 78
|
||||
#define CLK_GOUT_PERIC0_USI_I2C_CLK 79
|
||||
#define CLK_GOUT_PERIC0_SYSREG_PCLK 80
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_BUS_USER 1
|
||||
#define CLK_MOUT_PERIC1_UART_BT_USER 2
|
||||
#define CLK_MOUT_PERIC1_USI06_USI_USER 3
|
||||
#define CLK_MOUT_PERIC1_USI07_USI_USER 4
|
||||
#define CLK_MOUT_PERIC1_USI08_USI_USER 5
|
||||
#define CLK_MOUT_PERIC1_USI09_USI_USER 6
|
||||
#define CLK_MOUT_PERIC1_USI10_USI_USER 7
|
||||
#define CLK_MOUT_PERIC1_USI11_USI_USER 8
|
||||
#define CLK_MOUT_PERIC1_USI12_USI_USER 9
|
||||
#define CLK_MOUT_PERIC1_USI18_USI_USER 10
|
||||
#define CLK_MOUT_PERIC1_USI16_USI_USER 11
|
||||
#define CLK_MOUT_PERIC1_USI17_USI_USER 12
|
||||
#define CLK_MOUT_PERIC1_USI_I2C_USER 13
|
||||
#define CLK_DOUT_PERIC1_UART_BT 14
|
||||
#define CLK_DOUT_PERIC1_USI06_USI 15
|
||||
#define CLK_DOUT_PERIC1_USI07_USI 16
|
||||
#define CLK_DOUT_PERIC1_USI08_USI 17
|
||||
#define CLK_DOUT_PERIC1_USI18_USI 18
|
||||
#define CLK_DOUT_PERIC1_USI12_USI 19
|
||||
#define CLK_DOUT_PERIC1_USI09_USI 20
|
||||
#define CLK_DOUT_PERIC1_USI10_USI 21
|
||||
#define CLK_DOUT_PERIC1_USI11_USI 22
|
||||
#define CLK_DOUT_PERIC1_USI16_USI 23
|
||||
#define CLK_DOUT_PERIC1_USI17_USI 24
|
||||
#define CLK_DOUT_PERIC1_USI_I2C 25
|
||||
#define CLK_GOUT_PERIC1_CMU_PCLK 26
|
||||
#define CLK_GOUT_PERIC1_UART_BT_CLK 27
|
||||
#define CLK_GOUT_PERIC1_USI12_USI_CLK 28
|
||||
#define CLK_GOUT_PERIC1_USI18_USI_CLK 29
|
||||
#define CLK_GOUT_PERIC1_D_TZPC_PCLK 30
|
||||
#define CLK_GOUT_PERIC1_GPIO_PCLK 31
|
||||
#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 32
|
||||
#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 33
|
||||
#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 34
|
||||
#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 35
|
||||
#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 36
|
||||
#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 37
|
||||
#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 38
|
||||
#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 39
|
||||
#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 40
|
||||
#define CLK_GOUT_PERIC1_TOP0_PCLK_10 41
|
||||
#define CLK_GOUT_PERIC1_TOP0_PCLK_11 42
|
||||
#define CLK_GOUT_PERIC1_TOP0_PCLK_12 43
|
||||
#define CLK_GOUT_PERIC1_TOP0_PCLK_13 44
|
||||
#define CLK_GOUT_PERIC1_TOP0_PCLK_14 45
|
||||
#define CLK_GOUT_PERIC1_TOP0_PCLK_15 46
|
||||
#define CLK_GOUT_PERIC1_TOP0_PCLK_4 47
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 48
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 49
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 50
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 51
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 52
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 53
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 54
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 55
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 56
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 57
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 58
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 59
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 60
|
||||
#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 61
|
||||
#define CLK_GOUT_PERIC1_TOP1_PCLK_0 62
|
||||
#define CLK_GOUT_PERIC1_TOP1_PCLK_1 63
|
||||
#define CLK_GOUT_PERIC1_TOP1_PCLK_10 64
|
||||
#define CLK_GOUT_PERIC1_TOP1_PCLK_12 65
|
||||
#define CLK_GOUT_PERIC1_TOP1_PCLK_13 66
|
||||
#define CLK_GOUT_PERIC1_TOP1_PCLK_14 67
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#define CLK_GOUT_PERIC1_TOP1_PCLK_15 68
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#define CLK_GOUT_PERIC1_TOP1_PCLK_2 69
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#define CLK_GOUT_PERIC1_TOP1_PCLK_3 70
|
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#define CLK_GOUT_PERIC1_TOP1_PCLK_4 71
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#define CLK_GOUT_PERIC1_TOP1_PCLK_5 72
|
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#define CLK_GOUT_PERIC1_TOP1_PCLK_6 73
|
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#define CLK_GOUT_PERIC1_TOP1_PCLK_7 74
|
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#define CLK_GOUT_PERIC1_TOP1_PCLK_9 75
|
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#define CLK_GOUT_PERIC1_BUSP_CLK 76
|
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#define CLK_GOUT_PERIC1_OSCCLK_CLK 77
|
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#define CLK_GOUT_PERIC1_USI06_USI_CLK 78
|
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#define CLK_GOUT_PERIC1_USI07_USI_CLK 79
|
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#define CLK_GOUT_PERIC1_USI08_USI_CLK 80
|
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#define CLK_GOUT_PERIC1_USI09_USI_CLK 81
|
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#define CLK_GOUT_PERIC1_USI10_USI_CLK 82
|
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#define CLK_GOUT_PERIC1_USI11_USI_CLK 83
|
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#define CLK_GOUT_PERIC1_USI16_USI_CLK 84
|
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#define CLK_GOUT_PERIC1_USI17_USI_CLK 85
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#define CLK_GOUT_PERIC1_USI_I2C_CLK 86
|
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#define CLK_GOUT_PERIC1_SYSREG_PCLK 87
|
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#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 88
|
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#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 89
|
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#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 90
|
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#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91
|
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#define CLK_GOUT_PERIC1_XIU_P_ACLK 92
|
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|
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/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_BUS_USER 1
|
||||
|
||||
Reference in New Issue
Block a user