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dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units

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Add clock management unit bindings for PERIC0 and PERIC1 blocks
which provide clocks for USI, I2C and UART peripherals.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Denzeel Oliva
2025-09-04 14:07:11 +00:00
committed by Krzysztof Kozlowski
parent f00a5dc817
commit 43bd82eb33
2 changed files with 200 additions and 0 deletions
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24
Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
View File

@@ -30,6 +30,8 @@ description: |
properties:
compatible:
enum:
- samsung,exynos990-cmu-peric1
- samsung,exynos990-cmu-peric0
- samsung,exynos990-cmu-hsi0
- samsung,exynos990-cmu-peris
- samsung,exynos990-cmu-top
@@ -56,6 +58,28 @@ required:
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos990-cmu-peric1
- samsung,exynos990-cmu-peric0
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: ip
- if:
properties:
compatible:

176
include/dt-bindings/clock/samsung,exynos990.h
View File

@@ -238,6 +238,182 @@
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK 23
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_BUS_USER 1
#define CLK_MOUT_PERIC0_UART_DBG 2
#define CLK_MOUT_PERIC0_USI00_USI_USER 3
#define CLK_MOUT_PERIC0_USI01_USI_USER 4
#define CLK_MOUT_PERIC0_USI02_USI_USER 5
#define CLK_MOUT_PERIC0_USI03_USI_USER 6
#define CLK_MOUT_PERIC0_USI04_USI_USER 7
#define CLK_MOUT_PERIC0_USI05_USI_USER 8
#define CLK_MOUT_PERIC0_USI13_USI_USER 9
#define CLK_MOUT_PERIC0_USI14_USI_USER 10
#define CLK_MOUT_PERIC0_USI15_USI_USER 11
#define CLK_MOUT_PERIC0_USI_I2C_USER 12
#define CLK_DOUT_PERIC0_UART_DBG 13
#define CLK_DOUT_PERIC0_USI00_USI 14
#define CLK_DOUT_PERIC0_USI01_USI 15
#define CLK_DOUT_PERIC0_USI02_USI 16
#define CLK_DOUT_PERIC0_USI03_USI 17
#define CLK_DOUT_PERIC0_USI04_USI 18
#define CLK_DOUT_PERIC0_USI05_USI 19
#define CLK_DOUT_PERIC0_USI13_USI 20
#define CLK_DOUT_PERIC0_USI14_USI 21
#define CLK_DOUT_PERIC0_USI15_USI 22
#define CLK_DOUT_PERIC0_USI_I2C 23
#define CLK_GOUT_PERIC0_CMU_PCLK 24
#define CLK_GOUT_PERIC0_OSCCLK_CLK 25
#define CLK_GOUT_PERIC0_D_TZPC_PCLK 26
#define CLK_GOUT_PERIC0_GPIO_PCLK 27
#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 28
#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 29
#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 30
#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 31
#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 32
#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 33
#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 34
#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 35
#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 36
#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 37
#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 38
#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 39
#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 40
#define CLK_GOUT_PERIC0_TOP0_PCLK_10 41
#define CLK_GOUT_PERIC0_TOP0_PCLK_11 42
#define CLK_GOUT_PERIC0_TOP0_PCLK_12 43
#define CLK_GOUT_PERIC0_TOP0_PCLK_13 44
#define CLK_GOUT_PERIC0_TOP0_PCLK_14 45
#define CLK_GOUT_PERIC0_TOP0_PCLK_15 46
#define CLK_GOUT_PERIC0_TOP0_PCLK_4 47
#define CLK_GOUT_PERIC0_TOP0_PCLK_5 48
#define CLK_GOUT_PERIC0_TOP0_PCLK_6 49
#define CLK_GOUT_PERIC0_TOP0_PCLK_7 50
#define CLK_GOUT_PERIC0_TOP0_PCLK_8 51
#define CLK_GOUT_PERIC0_TOP0_PCLK_9 52
#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 53
#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 54
#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 55
#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 56
#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 57
#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 58
#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 59
#define CLK_GOUT_PERIC0_TOP1_PCLK_0 60
#define CLK_GOUT_PERIC0_TOP1_PCLK_15 61
#define CLK_GOUT_PERIC0_TOP1_PCLK_3 62
#define CLK_GOUT_PERIC0_TOP1_PCLK_4 63
#define CLK_GOUT_PERIC0_TOP1_PCLK_5 64
#define CLK_GOUT_PERIC0_TOP1_PCLK_6 65
#define CLK_GOUT_PERIC0_TOP1_PCLK_7 66
#define CLK_GOUT_PERIC0_TOP1_PCLK_8 67
#define CLK_GOUT_PERIC0_BUSP_CLK 68
#define CLK_GOUT_PERIC0_UART_DBG_CLK 69
#define CLK_GOUT_PERIC0_USI00_USI_CLK 70
#define CLK_GOUT_PERIC0_USI01_USI_CLK 71
#define CLK_GOUT_PERIC0_USI02_USI_CLK 72
#define CLK_GOUT_PERIC0_USI03_USI_CLK 73
#define CLK_GOUT_PERIC0_USI04_USI_CLK 74
#define CLK_GOUT_PERIC0_USI05_USI_CLK 75
#define CLK_GOUT_PERIC0_USI13_USI_CLK 76
#define CLK_GOUT_PERIC0_USI14_USI_CLK 77
#define CLK_GOUT_PERIC0_USI15_USI_CLK 78
#define CLK_GOUT_PERIC0_USI_I2C_CLK 79
#define CLK_GOUT_PERIC0_SYSREG_PCLK 80
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
#define CLK_MOUT_PERIC1_UART_BT_USER 2
#define CLK_MOUT_PERIC1_USI06_USI_USER 3
#define CLK_MOUT_PERIC1_USI07_USI_USER 4
#define CLK_MOUT_PERIC1_USI08_USI_USER 5
#define CLK_MOUT_PERIC1_USI09_USI_USER 6
#define CLK_MOUT_PERIC1_USI10_USI_USER 7
#define CLK_MOUT_PERIC1_USI11_USI_USER 8
#define CLK_MOUT_PERIC1_USI12_USI_USER 9
#define CLK_MOUT_PERIC1_USI18_USI_USER 10
#define CLK_MOUT_PERIC1_USI16_USI_USER 11
#define CLK_MOUT_PERIC1_USI17_USI_USER 12
#define CLK_MOUT_PERIC1_USI_I2C_USER 13
#define CLK_DOUT_PERIC1_UART_BT 14
#define CLK_DOUT_PERIC1_USI06_USI 15
#define CLK_DOUT_PERIC1_USI07_USI 16
#define CLK_DOUT_PERIC1_USI08_USI 17
#define CLK_DOUT_PERIC1_USI18_USI 18
#define CLK_DOUT_PERIC1_USI12_USI 19
#define CLK_DOUT_PERIC1_USI09_USI 20
#define CLK_DOUT_PERIC1_USI10_USI 21
#define CLK_DOUT_PERIC1_USI11_USI 22
#define CLK_DOUT_PERIC1_USI16_USI 23
#define CLK_DOUT_PERIC1_USI17_USI 24
#define CLK_DOUT_PERIC1_USI_I2C 25
#define CLK_GOUT_PERIC1_CMU_PCLK 26
#define CLK_GOUT_PERIC1_UART_BT_CLK 27
#define CLK_GOUT_PERIC1_USI12_USI_CLK 28
#define CLK_GOUT_PERIC1_USI18_USI_CLK 29
#define CLK_GOUT_PERIC1_D_TZPC_PCLK 30
#define CLK_GOUT_PERIC1_GPIO_PCLK 31
#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 32
#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 33
#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 34
#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 35
#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 36
#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 37
#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 38
#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 39
#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 40
#define CLK_GOUT_PERIC1_TOP0_PCLK_10 41
#define CLK_GOUT_PERIC1_TOP0_PCLK_11 42
#define CLK_GOUT_PERIC1_TOP0_PCLK_12 43
#define CLK_GOUT_PERIC1_TOP0_PCLK_13 44
#define CLK_GOUT_PERIC1_TOP0_PCLK_14 45
#define CLK_GOUT_PERIC1_TOP0_PCLK_15 46
#define CLK_GOUT_PERIC1_TOP0_PCLK_4 47
#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 48
#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 49
#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 50
#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 51
#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 52
#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 53
#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 54
#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 55
#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 56
#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 57
#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 58
#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 59
#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 60
#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 61
#define CLK_GOUT_PERIC1_TOP1_PCLK_0 62
#define CLK_GOUT_PERIC1_TOP1_PCLK_1 63
#define CLK_GOUT_PERIC1_TOP1_PCLK_10 64
#define CLK_GOUT_PERIC1_TOP1_PCLK_12 65
#define CLK_GOUT_PERIC1_TOP1_PCLK_13 66
#define CLK_GOUT_PERIC1_TOP1_PCLK_14 67
#define CLK_GOUT_PERIC1_TOP1_PCLK_15 68
#define CLK_GOUT_PERIC1_TOP1_PCLK_2 69
#define CLK_GOUT_PERIC1_TOP1_PCLK_3 70
#define CLK_GOUT_PERIC1_TOP1_PCLK_4 71
#define CLK_GOUT_PERIC1_TOP1_PCLK_5 72
#define CLK_GOUT_PERIC1_TOP1_PCLK_6 73
#define CLK_GOUT_PERIC1_TOP1_PCLK_7 74
#define CLK_GOUT_PERIC1_TOP1_PCLK_9 75
#define CLK_GOUT_PERIC1_BUSP_CLK 76
#define CLK_GOUT_PERIC1_OSCCLK_CLK 77
#define CLK_GOUT_PERIC1_USI06_USI_CLK 78
#define CLK_GOUT_PERIC1_USI07_USI_CLK 79
#define CLK_GOUT_PERIC1_USI08_USI_CLK 80
#define CLK_GOUT_PERIC1_USI09_USI_CLK 81
#define CLK_GOUT_PERIC1_USI10_USI_CLK 82
#define CLK_GOUT_PERIC1_USI11_USI_CLK 83
#define CLK_GOUT_PERIC1_USI16_USI_CLK 84
#define CLK_GOUT_PERIC1_USI17_USI_CLK 85
#define CLK_GOUT_PERIC1_USI_I2C_CLK 86
#define CLK_GOUT_PERIC1_SYSREG_PCLK 87
#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 88
#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 89
#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 90
#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91
#define CLK_GOUT_PERIC1_XIU_P_ACLK 92
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2