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mtd: intel-dg: align 64bit read and write

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GSC NVM controller HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.

Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Link: https://lore.kernel.org/r/20250617145159.3803852-6-alexander.usyskin@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Alexander Usyskin
2025-06-17 17:51:55 +03:00
committed by Rodrigo Vivi
parent 044c8be05a
commit 4b93f5fc3b
1 changed files with 35 additions and 0 deletions
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35
drivers/mtd/devices/mtd_intel_dg.c
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@@ -246,6 +246,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region,
len_s -= to_shift;
}
if (!IS_ALIGNED(to, sizeof(u64)) &&
((to ^ (to + len_s)) & GENMASK(31, 10))) {
/*
* Workaround reads/writes across 1k-aligned addresses
* (start u32 before 1k, end u32 after)
* as this fails on hardware.
*/
u32 data;
memcpy(&data, &buf[0], sizeof(u32));
idg_nvm_write32(nvm, to, data);
if (idg_nvm_error(nvm))
return -EIO;
buf += sizeof(u32);
to += sizeof(u32);
len_s -= sizeof(u32);
}
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data;
@@ -303,6 +321,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region,
from += from_shift;
}
if (!IS_ALIGNED(from, sizeof(u64)) &&
((from ^ (from + len_s)) & GENMASK(31, 10))) {
/*
* Workaround reads/writes across 1k-aligned addresses
* (start u32 before 1k, end u32 after)
* as this fails on hardware.
*/
u32 data = idg_nvm_read32(nvm, from);
if (idg_nvm_error(nvm))
return -EIO;
memcpy(&buf[0], &data, sizeof(data));
len_s -= sizeof(u32);
buf += sizeof(u32);
from += sizeof(u32);
}
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data = idg_nvm_read64(nvm, from + i);