drm/amdgpu: Add support for querying the max ibs in a submission. (v3)
This info would be used by radv to figure out when we need to split a submission into multiple submissions. radv currently has a limit of 192 which seems to work for most gfx submissions, but is way too high for e.g. compute or sdma. Userspace is available at https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3 v3: Completely rewrote based on suggestion of making it a separate query. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
c30ddcece3
commit
4f18b9a671
@@ -1140,6 +1140,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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kfree(caps);
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return r;
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}
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case AMDGPU_INFO_MAX_IBS: {
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uint32_t max_ibs[AMDGPU_HW_IP_NUM];
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for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
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max_ibs[i] = amdgpu_ring_max_ibs(i);
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return copy_to_user(out, max_ibs,
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min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
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}
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default:
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DRM_DEBUG_KMS("Invalid request %d\n", info->query);
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return -EINVAL;
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@@ -876,6 +876,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
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/* Subquery id: Encode */
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#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
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/* Query the max number of IBs per gang per submission */
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#define AMDGPU_INFO_MAX_IBS 0x22
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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