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phy: qcom: m31-eusb2: Fix the error log while enabling clock

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While enabling clock, we incorrectly log 'ref clk' as 'cfg ahb clk'
Fix this since the devicetree bindings mentions it as ref clock.

Signed-off-by: Prashanth K <prashanth.k@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250826105254.3758803-1-prashanth.k@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Prashanth K
2025-08-26 16:22:54 +05:30
committed by Vinod Koul
parent 0c5375b060
commit 616fe247bd
1 changed files with 1 additions and 1 deletions
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2
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
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@@ -196,7 +196,7 @@ static int m31eusb2_phy_init(struct phy *uphy)
ret = clk_prepare_enable(phy->clk);
if (ret) {
dev_err(&uphy->dev, "failed to enable cfg ahb clock, %d\n", ret);
dev_err(&uphy->dev, "failed to enable ref clock, %d\n", ret);
goto disable_repeater;
}