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Parvathi Pudi says:

====================
PRU-ICSSM Ethernet Driver

The Programmable Real-Time Unit Industrial Communication Sub-system (PRU-ICSS)
is available on the TI SOCs in two flavors: Gigabit ICSS (ICSSG) and the older
Megabit ICSS (ICSSM).

Support for ICSSG Dual-EMAC mode has already been mainlined [1] and the
fundamental components/drivers such as PRUSS driver, Remoteproc driver,
PRU-ICSS INTC, and PRU-ICSS IEP drivers are already available in the mainline
Linux kernel. The current set of patch series builds on top of these components
and introduces changes to support the Dual-EMAC using ICSSM on the TI AM57xx,
AM437x and AM335x devices.

AM335x, AM437x and AM57xx devices may have either one or two PRU-ICSS instances
with two 32-bit RISC PRU cores. Each PRU core has (a) dedicated Ethernet interface
(MII, MDIO), timers, capture modules, and serial communication interfaces, and
(b) dedicated data and instruction RAM as well as shared RAM for inter PRU
communication within the PRU-ICSS.

These patches add support for basic RX and TX  functionality over PRU Ethernet
ports in Dual-EMAC mode.

Further, note that these are the initial set of patches for a single instance of
PRU-ICSS Ethernet.  Additional features such as Ethtool support, VLAN Filtering,
Multicast Filtering, Promiscuous mode, Storm prevention, Interrupt coalescing,
Linux PTP (ptp4l) Ordinary clock and Switch mode support for AM335x, AM437x
and AM57x along with support for a second instance of  PRU-ICSS on AM57x
will be posted subsequently.

The patches presented in this series have gone through the patch verification
tools and no warnings or errors are reported. Sample test logs obtained from AM33x,
AM43x and AM57x verifying the functionality on Linux next kernel are available here:

[Interface up Testing](https://gist.github.com/ParvathiPudi/59ca0087dc7bed0f83a3b0e6db27d39c)

[Ping Testing](https://gist.github.com/ParvathiPudi/bcd39aa7006f6176d8c5b71a23d0928b)

[Iperf Testing](https://gist.github.com/ParvathiPudi/9bb4fa42410fbc757a93f65ecb45e4f3)

[1] https://lore.kernel.org/all/20230106121046.886863-1-danishanwar@ti.com/
[2] https://lore.kernel.org/all/20250108125937.10604-1-basharath@couthit.com/
====================

Link: https://patch.msgid.link/20250912104741.528721-1-parvathi@couthit.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2025-09-14 13:00:56 -07:00
parent 1611666834 7d4b52174d
commit 617d53f74b
12 changed files with 2761 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/net/ti,icss-iep.yaml
View File

@@ -8,6 +8,8 @@ title: Texas Instruments ICSS Industrial Ethernet Peripheral (IEP) module
maintainers:
- Md Danish Anwar <danishanwar@ti.com>
- Parvathi Pudi <parvathi@couthit.com>
- Basharath Hussain Khaja <basharath@couthit.com>
properties:
compatible:
@@ -17,9 +19,11 @@ properties:
- ti,am642-icss-iep
- ti,j721e-icss-iep
- const: ti,am654-icss-iep
- const: ti,am654-icss-iep
- enum:
- ti,am654-icss-iep
- ti,am5728-icss-iep
- ti,am4376-icss-iep
- ti,am3356-icss-iep
reg:
maxItems: 1

233
Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml Normal file
View File

@@ -0,0 +1,233 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,icssm-prueth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments ICSSM PRUSS Ethernet
maintainers:
- Roger Quadros <rogerq@ti.com>
- Andrew F. Davis <afd@ti.com>
- Parvathi Pudi <parvathi@couthit.com>
- Basharath Hussain Khaja <basharath@couthit.com>
description:
Ethernet based on the Programmable Real-Time Unit and Industrial
Communication Subsystem.
properties:
compatible:
enum:
- ti,am57-prueth # for AM57x SoC family
- ti,am4376-prueth # for AM43x SoC family
- ti,am3359-prueth # for AM33x SoC family
sram:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to OCMC SRAM node
ti,mii-rt:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the MII_RT peripheral for ICSS
ti,iep:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to IEP (Industrial Ethernet Peripheral) for ICSS
ti,ecap:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to Enhanced Capture (eCAP) event for ICSS
interrupts:
items:
- description: High priority Rx Interrupt specifier.
- description: Low priority Rx Interrupt specifier.
interrupt-names:
items:
- const: rx_hp
- const: rx_lp
ethernet-ports:
type: object
additionalProperties: false
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
^ethernet-port@[0-1]$:
type: object
description: ICSSM PRUETH external ports
$ref: ethernet-controller.yaml#
unevaluatedProperties: false
properties:
reg:
items:
- enum: [0, 1]
description: ICSSM PRUETH port number
interrupts:
maxItems: 3
interrupt-names:
items:
- const: rx
- const: emac_ptp_tx
- const: hsr_ptp_tx
required:
- reg
anyOf:
- required:
- ethernet-port@0
- required:
- ethernet-port@1
required:
- compatible
- sram
- ti,mii-rt
- ti,iep
- ti,ecap
- ethernet-ports
- interrupts
- interrupt-names
allOf:
- $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
unevaluatedProperties: false
examples:
- |
/* Dual-MAC Ethernet application node on PRU-ICSS2 */
pruss2_eth: pruss2-eth {
compatible = "ti,am57-prueth";
ti,prus = <&pru2_0>, <&pru2_1>;
sram = <&ocmcram1>;
ti,mii-rt = <&pruss2_mii_rt>;
ti,iep = <&pruss2_iep>;
ti,ecap = <&pruss2_ecap>;
interrupts = <20 2 2>, <21 3 3>;
interrupt-names = "rx_hp", "rx_lp";
interrupt-parent = <&pruss2_intc>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
pruss2_emac0: ethernet-port@0 {
reg = <0>;
phy-handle = <&pruss2_eth0_phy>;
phy-mode = "mii";
interrupts = <20 2 2>, <26 6 6>, <23 6 6>;
interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss2_emac1: ethernet-port@1 {
reg = <1>;
phy-handle = <&pruss2_eth1_phy>;
phy-mode = "mii";
interrupts = <21 3 3>, <27 9 7>, <24 9 7>;
interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
- |
/* Dual-MAC Ethernet application node on PRU-ICSS1 */
pruss1_eth: pruss1-eth {
compatible = "ti,am4376-prueth";
ti,prus = <&pru1_0>, <&pru1_1>;
sram = <&ocmcram>;
ti,mii-rt = <&pruss1_mii_rt>;
ti,iep = <&pruss1_iep>;
ti,ecap = <&pruss1_ecap>;
interrupts = <20 2 2>, <21 3 3>;
interrupt-names = "rx_hp", "rx_lp";
interrupt-parent = <&pruss1_intc>;
pinctrl-0 = <&pruss1_eth_default>;
pinctrl-names = "default";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
pruss1_emac0: ethernet-port@0 {
reg = <0>;
phy-handle = <&pruss1_eth0_phy>;
phy-mode = "mii";
interrupts = <20 2 2>, <26 6 6>, <23 6 6>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss1_emac1: ethernet-port@1 {
reg = <1>;
phy-handle = <&pruss1_eth1_phy>;
phy-mode = "mii";
interrupts = <21 3 3>, <27 9 7>, <24 9 7>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
- |
/* Dual-MAC Ethernet application node on PRU-ICSS */
pruss_eth: pruss-eth {
compatible = "ti,am3359-prueth";
ti,prus = <&pru0>, <&pru1>;
sram = <&ocmcram>;
ti,mii-rt = <&pruss_mii_rt>;
ti,iep = <&pruss_iep>;
ti,ecap = <&pruss_ecap>;
interrupts = <20 2 2>, <21 3 3>;
interrupt-names = "rx_hp", "rx_lp";
interrupt-parent = <&pruss_intc>;
pinctrl-0 = <&pruss_eth_default>;
pinctrl-names = "default";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
pruss_emac0: ethernet-port@0 {
reg = <0>;
phy-handle = <&pruss_eth0_phy>;
phy-mode = "mii";
interrupts = <20 2 2>, <26 6 6>, <23 6 6>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss_emac1: ethernet-port@1 {
reg = <1>;
phy-handle = <&pruss_eth1_phy>;
phy-mode = "mii";
interrupts = <21 3 3>, <27 9 7>, <24 9 7>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};

32
Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml Normal file
View File

@@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,pruss-ecap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments PRU-ICSS Enhanced Capture (eCAP) event module
maintainers:
- Murali Karicheri <m-karicheri2@ti.com>
- Parvathi Pudi <parvathi@couthit.com>
- Basharath Hussain Khaja <basharath@couthit.com>
properties:
compatible:
const: ti,pruss-ecap
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pruss2_ecap: ecap@30000 {
compatible = "ti,pruss-ecap";
reg = <0x30000 0x60>;
};

9
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
View File

@@ -251,6 +251,15 @@ patternProperties:
type: object
ecap@[a-f0-9]+$:
description:
PRU-ICSS has a Enhanced Capture (eCAP) event module which can generate
and capture periodic timer based events which will be used for features
like RX Pacing to rise interrupt when the timer event has occurred.
Each PRU-ICSS instance has one eCAP module irrespective of SOCs.
$ref: /schemas/net/ti,pruss-ecap.yaml#
type: object
mii-rt@[a-f0-9]+$:
description: |
Real-Time Ethernet to support multiple industrial communication protocols.

12
MAINTAINERS
View File

@@ -25319,6 +25319,18 @@ S: Maintained
F: Documentation/devicetree/bindings/net/ti,icss*.yaml
F: drivers/net/ethernet/ti/icssg/*
TI ICSSM ETHERNET DRIVER (ICSSM)
M: MD Danish Anwar <danishanwar@ti.com>
M: Parvathi Pudi <parvathi@couthit.com>
R: Roger Quadros <rogerq@kernel.org>
R: Mohan Reddy Putluru <pmohan@couthit.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/ti,icssm*.yaml
F: Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml
F: drivers/net/ethernet/ti/icssm/*
TI J721E CSI2RX DRIVER
M: Jai Luthra <jai.luthra@linux.dev>
L: linux-media@vger.kernel.org

12
drivers/net/ethernet/ti/Kconfig
View File

@@ -229,4 +229,16 @@ config TI_ICSS_IEP
To compile this driver as a module, choose M here. The module
will be called icss_iep.
config TI_PRUETH
tristate "TI PRU Ethernet EMAC driver"
depends on PRU_REMOTEPROC
depends on NET_SWITCHDEV
select TI_ICSS_IEP
imply PTP_1588_CLOCK
help
Some TI SoCs has Programmable Realtime Unit (PRU) cores which can
support Single or Dual Ethernet ports with the help of firmware code
running on PRU cores. This driver supports remoteproc based
communication to PRU firmware to expose Ethernet interface to Linux.
endif # NET_VENDOR_TI

3
drivers/net/ethernet/ti/Makefile
View File

@@ -3,6 +3,9 @@
# Makefile for the TI network device drivers.
#
obj-$(CONFIG_TI_PRUETH) += icssm-prueth.o
icssm-prueth-y := icssm/icssm_prueth.o
obj-$(CONFIG_TI_CPSW) += cpsw-common.o
obj-$(CONFIG_TI_DAVINCI_EMAC) += cpsw-common.o
obj-$(CONFIG_TI_CPSW_SWITCHDEV) += cpsw-common.o

101
drivers/net/ethernet/ti/icssg/icss_iep.c
View File

@@ -982,11 +982,112 @@ static const struct icss_iep_plat_data am654_icss_iep_plat_data = {
.config = &am654_icss_iep_regmap_config,
};
static const struct icss_iep_plat_data am57xx_icss_iep_plat_data = {
.flags = ICSS_IEP_64BIT_COUNTER_SUPPORT |
ICSS_IEP_SLOW_COMPEN_REG_SUPPORT,
.reg_offs = {
[ICSS_IEP_GLOBAL_CFG_REG] = 0x00,
[ICSS_IEP_COMPEN_REG] = 0x08,
[ICSS_IEP_SLOW_COMPEN_REG] = 0x0c,
[ICSS_IEP_COUNT_REG0] = 0x10,
[ICSS_IEP_COUNT_REG1] = 0x14,
[ICSS_IEP_CAPTURE_CFG_REG] = 0x18,
[ICSS_IEP_CAPTURE_STAT_REG] = 0x1c,
[ICSS_IEP_CAP6_RISE_REG0] = 0x50,
[ICSS_IEP_CAP6_RISE_REG1] = 0x54,
[ICSS_IEP_CAP7_RISE_REG0] = 0x60,
[ICSS_IEP_CAP7_RISE_REG1] = 0x64,
[ICSS_IEP_CMP_CFG_REG] = 0x70,
[ICSS_IEP_CMP_STAT_REG] = 0x74,
[ICSS_IEP_CMP0_REG0] = 0x78,
[ICSS_IEP_CMP0_REG1] = 0x7c,
[ICSS_IEP_CMP1_REG0] = 0x80,
[ICSS_IEP_CMP1_REG1] = 0x84,
[ICSS_IEP_CMP8_REG0] = 0xc0,
[ICSS_IEP_CMP8_REG1] = 0xc4,
[ICSS_IEP_SYNC_CTRL_REG] = 0x180,
[ICSS_IEP_SYNC0_STAT_REG] = 0x188,
[ICSS_IEP_SYNC1_STAT_REG] = 0x18c,
[ICSS_IEP_SYNC_PWIDTH_REG] = 0x190,
[ICSS_IEP_SYNC0_PERIOD_REG] = 0x194,
[ICSS_IEP_SYNC1_DELAY_REG] = 0x198,
[ICSS_IEP_SYNC_START_REG] = 0x19c,
},
.config = &am654_icss_iep_regmap_config,
};
static bool am335x_icss_iep_valid_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case ICSS_IEP_GLOBAL_CFG_REG ... ICSS_IEP_CAPTURE_STAT_REG:
case ICSS_IEP_CAP6_RISE_REG0:
case ICSS_IEP_CMP_CFG_REG ... ICSS_IEP_CMP0_REG0:
case ICSS_IEP_CMP8_REG0 ... ICSS_IEP_SYNC_START_REG:
return true;
default:
return false;
}
}
static const struct regmap_config am335x_icss_iep_regmap_config = {
.name = "icss iep",
.reg_stride = 1,
.reg_write = icss_iep_regmap_write,
.reg_read = icss_iep_regmap_read,
.writeable_reg = am335x_icss_iep_valid_reg,
.readable_reg = am335x_icss_iep_valid_reg,
};
static const struct icss_iep_plat_data am335x_icss_iep_plat_data = {
.flags = 0,
.reg_offs = {
[ICSS_IEP_GLOBAL_CFG_REG] = 0x00,
[ICSS_IEP_COMPEN_REG] = 0x08,
[ICSS_IEP_COUNT_REG0] = 0x0c,
[ICSS_IEP_CAPTURE_CFG_REG] = 0x10,
[ICSS_IEP_CAPTURE_STAT_REG] = 0x14,
[ICSS_IEP_CAP6_RISE_REG0] = 0x30,
[ICSS_IEP_CAP7_RISE_REG0] = 0x38,
[ICSS_IEP_CMP_CFG_REG] = 0x40,
[ICSS_IEP_CMP_STAT_REG] = 0x44,
[ICSS_IEP_CMP0_REG0] = 0x48,
[ICSS_IEP_CMP8_REG0] = 0x88,
[ICSS_IEP_SYNC_CTRL_REG] = 0x100,
[ICSS_IEP_SYNC0_STAT_REG] = 0x108,
[ICSS_IEP_SYNC1_STAT_REG] = 0x10c,
[ICSS_IEP_SYNC_PWIDTH_REG] = 0x110,
[ICSS_IEP_SYNC0_PERIOD_REG] = 0x114,
[ICSS_IEP_SYNC1_DELAY_REG] = 0x118,
[ICSS_IEP_SYNC_START_REG] = 0x11c,
},
.config = &am335x_icss_iep_regmap_config,
};
static const struct of_device_id icss_iep_of_match[] = {
{
.compatible = "ti,am654-icss-iep",
.data = &am654_icss_iep_plat_data,
},
{
.compatible = "ti,am5728-icss-iep",
.data = &am57xx_icss_iep_plat_data,
},
{
.compatible = "ti,am4376-icss-iep",
.data = &am335x_icss_iep_plat_data,
},
{
.compatible = "ti,am3356-icss-iep",
.data = &am335x_icss_iep_plat_data,
},
{},
};
MODULE_DEVICE_TABLE(of, icss_iep_of_match);

1748
drivers/net/ethernet/ti/icssm/icssm_prueth.c Normal file
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File diff suppressed because it is too large Load Diff

262
drivers/net/ethernet/ti/icssm/icssm_prueth.h Normal file
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@@ -0,0 +1,262 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Texas Instruments ICSSM Ethernet driver
*
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
*
*/
#ifndef __NET_TI_PRUETH_H
#define __NET_TI_PRUETH_H
#include <linux/phy.h>
#include <linux/types.h>
#include <linux/pruss_driver.h>
#include <linux/remoteproc/pruss.h>
#include "icssm_switch.h"
#include "icssm_prueth_ptp.h"
/* ICSSM size of redundancy tag */
#define ICSSM_LRE_TAG_SIZE 6
/* PRUSS local memory map */
#define ICSS_LOCAL_SHARED_RAM 0x00010000
#define EMAC_MAX_PKTLEN (ETH_HLEN + VLAN_HLEN + ETH_DATA_LEN)
/* Below macro is for 1528 Byte Frame support, to Allow even with
* Redundancy tag
*/
#define EMAC_MAX_FRM_SUPPORT (ETH_HLEN + VLAN_HLEN + ETH_DATA_LEN + \
ICSSM_LRE_TAG_SIZE)
/* PRU Ethernet Type - Ethernet functionality (protocol
* implemented) provided by the PRU firmware being loaded.
*/
enum pruss_ethtype {
PRUSS_ETHTYPE_EMAC = 0,
PRUSS_ETHTYPE_HSR,
PRUSS_ETHTYPE_PRP,
PRUSS_ETHTYPE_SWITCH,
PRUSS_ETHTYPE_MAX,
};
#define PRUETH_IS_EMAC(p) ((p)->eth_type == PRUSS_ETHTYPE_EMAC)
#define PRUETH_IS_SWITCH(p) ((p)->eth_type == PRUSS_ETHTYPE_SWITCH)
/**
* struct prueth_queue_desc - Queue descriptor
* @rd_ptr: Read pointer, points to a buffer descriptor in Shared PRU RAM.
* @wr_ptr: Write pointer, points to a buffer descriptor in Shared PRU RAM.
* @busy_s: Slave queue busy flag, set by slave(us) to request access from
* master(PRU).
* @status: Bit field status register, Bits:
* 0: Master queue busy flag.
* 1: Packet has been placed in collision queue.
* 2: Packet has been discarded due to overflow.
* @max_fill_level: Maximum queue usage seen.
* @overflow_cnt: Count of queue overflows.
*
* Each port has up to 4 queues with variable length. The queue is processed
* as ring buffer with read and write pointers. Both pointers are address
* pointers and increment by 4 for each buffer descriptor position. Queue has
* a length defined in constants and a status.
*/
struct prueth_queue_desc {
u16 rd_ptr;
u16 wr_ptr;
u8 busy_s;
u8 status;
u8 max_fill_level;
u8 overflow_cnt;
};
/**
* struct prueth_queue_info - Information about a queue in memory
* @buffer_offset: buffer offset in OCMC RAM
* @queue_desc_offset: queue descriptor offset in Shared RAM
* @buffer_desc_offset: buffer descriptors offset in Shared RAM
* @buffer_desc_end: end address of buffer descriptors in Shared RAM
*/
struct prueth_queue_info {
u16 buffer_offset;
u16 queue_desc_offset;
u16 buffer_desc_offset;
u16 buffer_desc_end;
};
/**
* struct prueth_packet_info - Info about a packet in buffer
* @shadow: this packet is stored in the collision queue
* @port: port packet is on
* @length: length of packet
* @broadcast: this packet is a broadcast packet
* @error: this packet has an error
* @lookup_success: src mac found in FDB
* @flood: packet is to be flooded
* @timestamp: Specifies if timestamp is appended to the packet
*/
struct prueth_packet_info {
bool shadow;
unsigned int port;
unsigned int length;
bool broadcast;
bool error;
bool lookup_success;
bool flood;
bool timestamp;
};
/* In switch mode there are 3 real ports i.e. 3 mac addrs.
* however Linux sees only the host side port. The other 2 ports
* are the switch ports.
* In emac mode there are 2 real ports i.e. 2 mac addrs.
* Linux sees both the ports.
*/
enum prueth_port {
PRUETH_PORT_HOST = 0, /* host side port */
PRUETH_PORT_MII0, /* physical port MII 0 */
PRUETH_PORT_MII1, /* physical port MII 1 */
PRUETH_PORT_INVALID, /* Invalid prueth port */
};
enum prueth_mac {
PRUETH_MAC0 = 0,
PRUETH_MAC1,
PRUETH_NUM_MACS,
PRUETH_MAC_INVALID,
};
/* In both switch & emac modes there are 3 port queues
* EMAC mode:
* RX packets for both MII0 & MII1 ports come on
* QUEUE_HOST.
* TX packets for MII0 go on QUEUE_MII0, TX packets
* for MII1 go on QUEUE_MII1.
* Switch mode:
* Host port RX packets come on QUEUE_HOST
* TX packets might have to go on MII0 or MII1 or both.
* MII0 TX queue is QUEUE_MII0 and MII1 TX queue is
* QUEUE_MII1.
*/
enum prueth_port_queue_id {
PRUETH_PORT_QUEUE_HOST = 0,
PRUETH_PORT_QUEUE_MII0,
PRUETH_PORT_QUEUE_MII1,
PRUETH_PORT_QUEUE_MAX,
};
/* Each port queue has 4 queues and 1 collision queue */
enum prueth_queue_id {
PRUETH_QUEUE1 = 0,
PRUETH_QUEUE2,
PRUETH_QUEUE3,
PRUETH_QUEUE4,
PRUETH_COLQUEUE, /* collision queue */
};
/**
* struct prueth_firmware - PRU Ethernet FW data
* @fw_name: firmware names of firmware to run on PRU
*/
struct prueth_firmware {
const char *fw_name[PRUSS_ETHTYPE_MAX];
};
/* PRUeth memory range identifiers */
enum prueth_mem {
PRUETH_MEM_DRAM0 = 0,
PRUETH_MEM_DRAM1,
PRUETH_MEM_SHARED_RAM,
PRUETH_MEM_OCMC,
PRUETH_MEM_MAX,
};
enum pruss_device {
PRUSS_AM57XX = 0,
PRUSS_AM43XX,
PRUSS_AM33XX,
PRUSS_K2G
};
/**
* struct prueth_private_data - PRU Ethernet private data
* @driver_data: PRU Ethernet device name
* @fw_pru: firmware names to be used for PRUSS ethernet usecases
*/
struct prueth_private_data {
enum pruss_device driver_data;
const struct prueth_firmware fw_pru[PRUSS_NUM_PRUS];
};
struct prueth_emac_stats {
u64 tx_packets;
u64 tx_dropped;
u64 tx_bytes;
u64 rx_packets;
u64 rx_bytes;
u64 rx_length_errors;
u64 rx_over_errors;
};
/* data for each emac port */
struct prueth_emac {
struct prueth *prueth;
struct net_device *ndev;
struct napi_struct napi;
struct rproc *pru;
struct phy_device *phydev;
struct prueth_queue_desc __iomem *rx_queue_descs;
struct prueth_queue_desc __iomem *tx_queue_descs;
int link;
int speed;
int duplex;
int rx_irq;
enum prueth_port_queue_id tx_port_queue;
enum prueth_queue_id rx_queue_start;
enum prueth_queue_id rx_queue_end;
enum prueth_port port_id;
enum prueth_mem dram;
const char *phy_id;
u32 msg_enable;
u8 mac_addr[6];
phy_interface_t phy_if;
/* spin lock used to protect
* during link configuration
*/
spinlock_t lock;
struct hrtimer tx_hrtimer;
struct prueth_emac_stats stats;
};
struct prueth {
struct device *dev;
struct pruss *pruss;
struct rproc *pru0, *pru1;
struct pruss_mem_region mem[PRUETH_MEM_MAX];
struct gen_pool *sram_pool;
struct regmap *mii_rt;
struct icss_iep *iep;
const struct prueth_private_data *fw_data;
struct prueth_fw_offsets *fw_offsets;
struct device_node *eth_node[PRUETH_NUM_MACS];
struct prueth_emac *emac[PRUETH_NUM_MACS];
struct net_device *registered_netdevs[PRUETH_NUM_MACS];
unsigned int eth_type;
size_t ocmc_ram_size;
u8 emac_configured;
};
void icssm_parse_packet_info(struct prueth *prueth, u32 buffer_descriptor,
struct prueth_packet_info *pkt_info);
int icssm_emac_rx_packet(struct prueth_emac *emac, u16 *bd_rd_ptr,
struct prueth_packet_info *pkt_info,
const struct prueth_queue_info *rxqueue);
#endif /* __NET_TI_PRUETH_H */

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drivers/net/ethernet/ti/icssm/icssm_prueth_ptp.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef PRUETH_PTP_H
#define PRUETH_PTP_H
#define RX_SYNC_TIMESTAMP_OFFSET_P1 0x8 /* 8 bytes */
#define RX_PDELAY_REQ_TIMESTAMP_OFFSET_P1 0x14 /* 12 bytes */
#define DISABLE_PTP_FRAME_FORWARDING_CTRL_OFFSET 0x14 /* 1 byte */
#define RX_PDELAY_RESP_TIMESTAMP_OFFSET_P1 0x20 /* 12 bytes */
#define RX_SYNC_TIMESTAMP_OFFSET_P2 0x2c /* 12 bytes */
#define RX_PDELAY_REQ_TIMESTAMP_OFFSET_P2 0x38 /* 12 bytes */
#define RX_PDELAY_RESP_TIMESTAMP_OFFSET_P2 0x44 /* 12 bytes */
#define TIMESYNC_DOMAIN_NUMBER_LIST 0x50 /* 2 bytes */
#define P1_SMA_LINE_DELAY_OFFSET 0x52 /* 4 bytes */
#define P2_SMA_LINE_DELAY_OFFSET 0x56 /* 4 bytes */
#define TIMESYNC_SECONDS_COUNT_OFFSET 0x5a /* 6 bytes */
#define TIMESYNC_TC_RCF_OFFSET 0x60 /* 4 bytes */
#define DUT_IS_MASTER_OFFSET 0x64 /* 1 byte */
#define MASTER_PORT_NUM_OFFSET 0x65 /* 1 byte */
#define SYNC_MASTER_MAC_OFFSET 0x66 /* 6 bytes */
#define TX_TS_NOTIFICATION_OFFSET_SYNC_P1 0x6c /* 1 byte */
#define TX_TS_NOTIFICATION_OFFSET_PDEL_REQ_P1 0x6d /* 1 byte */
#define TX_TS_NOTIFICATION_OFFSET_PDEL_RES_P1 0x6e /* 1 byte */
#define TX_TS_NOTIFICATION_OFFSET_SYNC_P2 0x6f /* 1 byte */
#define TX_TS_NOTIFICATION_OFFSET_PDEL_REQ_P2 0x70 /* 1 byte */
#define TX_TS_NOTIFICATION_OFFSET_PDEL_RES_P2 0x71 /* 1 byte */
#define TX_SYNC_TIMESTAMP_OFFSET_P1 0x72 /* 12 bytes */
#define TX_PDELAY_REQ_TIMESTAMP_OFFSET_P1 0x7e /* 12 bytes */
#define TX_PDELAY_RESP_TIMESTAMP_OFFSET_P1 0x8a /* 12 bytes */
#define TX_SYNC_TIMESTAMP_OFFSET_P2 0x96 /* 12 bytes */
#define TX_PDELAY_REQ_TIMESTAMP_OFFSET_P2 0xa2 /* 12 bytes */
#define TX_PDELAY_RESP_TIMESTAMP_OFFSET_P2 0xae /* 12 bytes */
#define TIMESYNC_CTRL_VAR_OFFSET 0xba /* 1 byte */
#define DISABLE_SWITCH_SYNC_RELAY_OFFSET 0xbb /* 1 byte */
#define MII_RX_CORRECTION_OFFSET 0xbc /* 2 bytes */
#define MII_TX_CORRECTION_OFFSET 0xbe /* 2 bytes */
#define TIMESYNC_CMP1_CMP_OFFSET 0xc0 /* 8 bytes */
#define TIMESYNC_SYNC0_CMP_OFFSET 0xc8 /* 8 bytes */
#define TIMESYNC_CMP1_PERIOD_OFFSET 0xd0 /* 4 bytes */
#define TIMESYNC_SYNC0_WIDTH_OFFSET 0xd4 /* 4 bytes */
#define SINGLE_STEP_IEP_OFFSET_P1 0xd8 /* 8 bytes */
#define SINGLE_STEP_SECONDS_OFFSET_P1 0xe0 /* 8 bytes */
#define SINGLE_STEP_IEP_OFFSET_P2 0xe8 /* 8 bytes */
#define SINGLE_STEP_SECONDS_OFFSET_P2 0xf0 /* 8 bytes */
#define LINK_LOCAL_FRAME_HAS_HSR_TAG 0xf8 /* 1 bytes */
#define PTP_PREV_TX_TIMESTAMP_P1 0xf9 /* 8 bytes */
#define PTP_PREV_TX_TIMESTAMP_P2 0x101 /* 8 bytes */
#define PTP_CLK_IDENTITY_OFFSET 0x109 /* 8 bytes */
#define PTP_SCRATCH_MEM 0x111 /* 16 byte */
#define PTP_IPV4_UDP_E2E_ENABLE 0x121 /* 1 byte */
enum {
PRUETH_PTP_SYNC,
PRUETH_PTP_DLY_REQ,
PRUETH_PTP_DLY_RESP,
PRUETH_PTP_TS_EVENTS,
};
#define PRUETH_PTP_TS_SIZE 12
#define PRUETH_PTP_TS_NOTIFY_SIZE 1
#define PRUETH_PTP_TS_NOTIFY_MASK 0xff
/* Bit definitions for TIMESYNC_CTRL */
#define TIMESYNC_CTRL_BG_ENABLE BIT(0)
#define TIMESYNC_CTRL_FORCED_2STEP BIT(1)
static inline u32 icssm_prueth_tx_ts_offs_get(u8 port, u8 event)
{
return TX_SYNC_TIMESTAMP_OFFSET_P1 + port *
PRUETH_PTP_TS_EVENTS * PRUETH_PTP_TS_SIZE +
event * PRUETH_PTP_TS_SIZE;
}
static inline u32 icssm_prueth_tx_ts_notify_offs_get(u8 port, u8 event)
{
return TX_TS_NOTIFICATION_OFFSET_SYNC_P1 +
PRUETH_PTP_TS_EVENTS * PRUETH_PTP_TS_NOTIFY_SIZE * port +
event * PRUETH_PTP_TS_NOTIFY_SIZE;
}
#endif /* PRUETH_PTP_H */

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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2015-2021 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __ICSS_SWITCH_H
#define __ICSS_SWITCH_H
/* Basic Switch Parameters
* Used to auto compute offset addresses on L3 OCMC RAM. Do not modify these
* without changing firmware accordingly
*/
#define SWITCH_BUFFER_SIZE (64 * 1024) /* L3 buffer */
#define ICSS_BLOCK_SIZE 32 /* data bytes per BD */
#define BD_SIZE 4 /* byte buffer descriptor */
#define NUM_QUEUES 4 /* Queues on Port 0/1/2 */
#define PORT_LINK_MASK 0x1
#define PORT_IS_HD_MASK 0x2
/* Physical Port queue size (number of BDs). Same for both ports */
#define QUEUE_1_SIZE 97 /* Network Management high */
#define QUEUE_2_SIZE 97 /* Network Management low */
#define QUEUE_3_SIZE 97 /* Protocol specific */
#define QUEUE_4_SIZE 97 /* NRT (IP,ARP, ICMP) */
/* Host queue size (number of BDs). Each BD points to data buffer of 32 bytes.
* HOST PORT QUEUES can buffer up to 4 full sized frames per queue
*/
#define HOST_QUEUE_1_SIZE 194 /* Protocol and VLAN priority 7 & 6 */
#define HOST_QUEUE_2_SIZE 194 /* Protocol mid */
#define HOST_QUEUE_3_SIZE 194 /* Protocol low */
#define HOST_QUEUE_4_SIZE 194 /* NRT (IP, ARP, ICMP) */
#define COL_QUEUE_SIZE 0
/* NRT Buffer descriptor definition
* Each buffer descriptor points to a max 32 byte block and has 32 bit in size
* to have atomic operation.
* PRU can address bytewise into memory.
* Definition of 32 bit descriptor is as follows
*
* Bits Name Meaning
* =============================================================================
* 0..7 Index points to index in buffer queue, max 256 x 32
* byte blocks can be addressed
* 6 LookupSuccess For switch, FDB lookup was successful (source
* MAC address found in FDB).
* For RED, NodeTable lookup was successful.
* 7 Flood Packet should be flooded (destination MAC
* address found in FDB). For switch only.
* 8..12 Block_length number of valid bytes in this specific block.
* Will be <=32 bytes on last block of packet
* 13 More "More" bit indicating that there are more blocks
* 14 Shadow indicates that "index" is pointing into shadow
* buffer
* 15 TimeStamp indicates that this packet has time stamp in
* separate buffer - only needed if PTP runs on
* host
* 16..17 Port different meaning for ingress and egress,
* Ingress: Port = 0 indicates phy port 1 and
* Port = 1 indicates phy port 2.
* Egress: 0 sends on phy port 1 and 1 sends on
* phy port 2. Port = 2 goes over MAC table
* look-up
* 18..28 Length 11 bit of total packet length which is put into
* first BD only so that host access only one BD
* 29 VlanTag indicates that packet has Length/Type field of
* 0x08100 with VLAN tag in following byte
* 30 Broadcast indicates that packet goes out on both physical
* ports, there will be two bd but only one buffer
* 31 Error indicates there was an error in the packet
*/
#define PRUETH_BD_START_FLAG_MASK BIT(0)
#define PRUETH_BD_START_FLAG_SHIFT 0
#define PRUETH_BD_HSR_FRAME_MASK BIT(4)
#define PRUETH_BD_HSR_FRAME_SHIFT 4
#define PRUETH_BD_SUP_HSR_FRAME_MASK BIT(5)
#define PRUETH_BD_SUP_HSR_FRAME_SHIFT 5
#define PRUETH_BD_LOOKUP_SUCCESS_MASK BIT(6)
#define PRUETH_BD_LOOKUP_SUCCESS_SHIFT 6
#define PRUETH_BD_SW_FLOOD_MASK BIT(7)
#define PRUETH_BD_SW_FLOOD_SHIFT 7
#define PRUETH_BD_SHADOW_MASK BIT(14)
#define PRUETH_BD_SHADOW_SHIFT 14
#define PRUETH_BD_TIMESTAMP_MASK BIT(15)
#define PRUETH_BD_TIMESTAMP_SHIFT 15
#define PRUETH_BD_PORT_MASK GENMASK(17, 16)
#define PRUETH_BD_PORT_SHIFT 16
#define PRUETH_BD_LENGTH_MASK GENMASK(28, 18)
#define PRUETH_BD_LENGTH_SHIFT 18
#define PRUETH_BD_BROADCAST_MASK BIT(30)
#define PRUETH_BD_BROADCAST_SHIFT 30
#define PRUETH_BD_ERROR_MASK BIT(31)
#define PRUETH_BD_ERROR_SHIFT 31
/* The following offsets indicate which sections of the memory are used
* for EMAC internal tasks
*/
#define DRAM_START_OFFSET 0x1E98
#define SRAM_START_OFFSET 0x400
/* General Purpose Statistics
* These are present on both PRU0 and PRU1 DRAM
*/
/* base statistics offset */
#define STATISTICS_OFFSET 0x1F00
#define STAT_SIZE 0x98
/* Offset for storing
* 1. Storm Prevention Params
* 2. PHY Speed Offset
* 3. Port Status Offset
* These are present on both PRU0 and PRU1
*/
/* 4 bytes */
#define STORM_PREVENTION_OFFSET_BC (STATISTICS_OFFSET + STAT_SIZE)
/* 4 bytes */
#define PHY_SPEED_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 4)
/* 1 byte */
#define PORT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 8)
/* 1 byte */
#define COLLISION_COUNTER (STATISTICS_OFFSET + STAT_SIZE + 9)
/* 4 bytes */
#define RX_PKT_SIZE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 10)
/* 4 bytes */
#define PORT_CONTROL_ADDR (STATISTICS_OFFSET + STAT_SIZE + 14)
/* 6 bytes */
#define PORT_MAC_ADDR (STATISTICS_OFFSET + STAT_SIZE + 18)
/* 1 byte */
#define RX_INT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 24)
/* 4 bytes */
#define STORM_PREVENTION_OFFSET_MC (STATISTICS_OFFSET + STAT_SIZE + 25)
/* 4 bytes */
#define STORM_PREVENTION_OFFSET_UC (STATISTICS_OFFSET + STAT_SIZE + 29)
/* 4 bytes ? */
#define STP_INVALID_STATE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 33)
/* DRAM Offsets for EMAC
* Present on Both DRAM0 and DRAM1
*/
/* 4 queue descriptors for port tx = 32 bytes */
#define TX_CONTEXT_Q1_OFFSET_ADDR (PORT_QUEUE_DESC_OFFSET + 32)
#define PORT_QUEUE_DESC_OFFSET (ICSS_EMAC_TTS_CYC_TX_SOF + 8)
/* EMAC Time Triggered Send Offsets */
#define ICSS_EMAC_TTS_CYC_TX_SOF (ICSS_EMAC_TTS_PREV_TX_SOF + 8)
#define ICSS_EMAC_TTS_PREV_TX_SOF \
(ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET + 4)
#define ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET (ICSS_EMAC_TTS_STATUS_OFFSET \
+ 4)
#define ICSS_EMAC_TTS_STATUS_OFFSET (ICSS_EMAC_TTS_CFG_TIME_OFFSET + 4)
#define ICSS_EMAC_TTS_CFG_TIME_OFFSET (ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET + 4)
#define ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET \
(ICSS_EMAC_TTS_CYCLE_START_OFFSET + 8)
#define ICSS_EMAC_TTS_CYCLE_START_OFFSET ICSS_EMAC_TTS_BASE_OFFSET
#define ICSS_EMAC_TTS_BASE_OFFSET DRAM_START_OFFSET
/* Shared RAM offsets for EMAC */
/* Queue Descriptors */
/* 4 queue descriptors for port 0 (host receive). 32 bytes */
#define HOST_QUEUE_DESC_OFFSET (HOST_QUEUE_SIZE_ADDR + 16)
/* table offset for queue size:
* 3 ports * 4 Queues * 1 byte offset = 12 bytes
*/
#define HOST_QUEUE_SIZE_ADDR (HOST_QUEUE_OFFSET_ADDR + 8)
/* table offset for queue:
* 4 Queues * 2 byte offset = 8 bytes
*/
#define HOST_QUEUE_OFFSET_ADDR (HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR + 8)
/* table offset for Host queue descriptors:
* 1 ports * 4 Queues * 2 byte offset = 8 bytes
*/
#define HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR (HOST_Q4_RX_CONTEXT_OFFSET + 8)
/* Host Port Rx Context */
#define HOST_Q4_RX_CONTEXT_OFFSET (HOST_Q3_RX_CONTEXT_OFFSET + 8)
#define HOST_Q3_RX_CONTEXT_OFFSET (HOST_Q2_RX_CONTEXT_OFFSET + 8)
#define HOST_Q2_RX_CONTEXT_OFFSET (HOST_Q1_RX_CONTEXT_OFFSET + 8)
#define HOST_Q1_RX_CONTEXT_OFFSET (EMAC_PROMISCUOUS_MODE_OFFSET + 4)
/* Promiscuous mode control */
#define EMAC_P1_PROMISCUOUS_BIT BIT(0)
#define EMAC_P2_PROMISCUOUS_BIT BIT(1)
#define EMAC_PROMISCUOUS_MODE_OFFSET (EMAC_RESERVED + 4)
#define EMAC_RESERVED EOF_48K_BUFFER_BD
/* allow for max 48k buffer which spans the descriptors up to 0x1800 6kB */
#define EOF_48K_BUFFER_BD (P0_BUFFER_DESC_OFFSET + HOST_BD_SIZE + \
PORT_BD_SIZE)
#define HOST_BD_SIZE ((HOST_QUEUE_1_SIZE + \
HOST_QUEUE_2_SIZE + HOST_QUEUE_3_SIZE + \
HOST_QUEUE_4_SIZE) * BD_SIZE)
#define PORT_BD_SIZE ((QUEUE_1_SIZE + QUEUE_2_SIZE + \
QUEUE_3_SIZE + QUEUE_4_SIZE) * 2 * BD_SIZE)
#define END_OF_BD_POOL (P2_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE)
#define P2_Q4_BD_OFFSET (P2_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE)
#define P2_Q3_BD_OFFSET (P2_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE)
#define P2_Q2_BD_OFFSET (P2_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE)
#define P2_Q1_BD_OFFSET (P1_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE)
#define P1_Q4_BD_OFFSET (P1_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE)
#define P1_Q3_BD_OFFSET (P1_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE)
#define P1_Q2_BD_OFFSET (P1_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE)
#define P1_Q1_BD_OFFSET (P0_Q4_BD_OFFSET + HOST_QUEUE_4_SIZE * BD_SIZE)
#define P0_Q4_BD_OFFSET (P0_Q3_BD_OFFSET + HOST_QUEUE_3_SIZE * BD_SIZE)
#define P0_Q3_BD_OFFSET (P0_Q2_BD_OFFSET + HOST_QUEUE_2_SIZE * BD_SIZE)
#define P0_Q2_BD_OFFSET (P0_Q1_BD_OFFSET + HOST_QUEUE_1_SIZE * BD_SIZE)
#define P0_Q1_BD_OFFSET P0_BUFFER_DESC_OFFSET
#define P0_BUFFER_DESC_OFFSET SRAM_START_OFFSET
/* Memory Usage of L3 OCMC RAM */
/* L3 64KB Memory - mainly buffer Pool */
#define END_OF_BUFFER_POOL (P2_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \
ICSS_BLOCK_SIZE)
#define P2_Q4_BUFFER_OFFSET (P2_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \
ICSS_BLOCK_SIZE)
#define P2_Q3_BUFFER_OFFSET (P2_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \
ICSS_BLOCK_SIZE)
#define P2_Q2_BUFFER_OFFSET (P2_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \
ICSS_BLOCK_SIZE)
#define P2_Q1_BUFFER_OFFSET (P1_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \
ICSS_BLOCK_SIZE)
#define P1_Q4_BUFFER_OFFSET (P1_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \
ICSS_BLOCK_SIZE)
#define P1_Q3_BUFFER_OFFSET (P1_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \
ICSS_BLOCK_SIZE)
#define P1_Q2_BUFFER_OFFSET (P1_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \
ICSS_BLOCK_SIZE)
#define P1_Q1_BUFFER_OFFSET (P0_Q4_BUFFER_OFFSET + HOST_QUEUE_4_SIZE * \
ICSS_BLOCK_SIZE)
#define P0_Q4_BUFFER_OFFSET (P0_Q3_BUFFER_OFFSET + HOST_QUEUE_3_SIZE * \
ICSS_BLOCK_SIZE)
#define P0_Q3_BUFFER_OFFSET (P0_Q2_BUFFER_OFFSET + HOST_QUEUE_2_SIZE * \
ICSS_BLOCK_SIZE)
#define P0_Q2_BUFFER_OFFSET (P0_Q1_BUFFER_OFFSET + HOST_QUEUE_1_SIZE * \
ICSS_BLOCK_SIZE)
#define P0_COL_BUFFER_OFFSET 0xEE00
#define P0_Q1_BUFFER_OFFSET 0x0000
#endif /* __ICSS_SWITCH_H */