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@@ -1,6 +1,11 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Core functions for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs
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* Core functions for following TI PMICs:
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* - LP8764
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* - TPS65224
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* - TPS652G1
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* - TPS6593
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* - TPS6594
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*
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* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
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*/
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@@ -414,6 +419,61 @@ static const unsigned int tps65224_irq_reg[] = {
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TPS6594_REG_INT_FSM_ERR,
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};
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/* TPS652G1 Resources */
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static const struct mfd_cell tps652g1_common_cells[] = {
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MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources),
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MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources),
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MFD_CELL_NAME("tps6594-regulator"),
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};
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static const struct regmap_irq tps652g1_irqs[] = {
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/* INT_GPIO register */
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REGMAP_IRQ_REG(TPS65224_IRQ_GPIO1, 2, TPS65224_BIT_GPIO1_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_GPIO2, 2, TPS65224_BIT_GPIO2_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_GPIO3, 2, TPS65224_BIT_GPIO3_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_GPIO4, 2, TPS65224_BIT_GPIO4_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_GPIO5, 2, TPS65224_BIT_GPIO5_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_GPIO6, 2, TPS65224_BIT_GPIO6_INT),
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/* INT_STARTUP register */
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REGMAP_IRQ_REG(TPS65224_IRQ_VSENSE, 3, TPS65224_BIT_VSENSE_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_ENABLE, 3, TPS6594_BIT_ENABLE_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_PB_SHORT, 3, TPS65224_BIT_PB_SHORT_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_FSD, 3, TPS6594_BIT_FSD_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_SOFT_REBOOT, 3, TPS6594_BIT_SOFT_REBOOT_INT),
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/* INT_MISC register */
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REGMAP_IRQ_REG(TPS65224_IRQ_BIST_PASS, 4, TPS6594_BIT_BIST_PASS_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_EXT_CLK, 4, TPS6594_BIT_EXT_CLK_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_REG_UNLOCK, 4, TPS65224_BIT_REG_UNLOCK_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_TWARN, 4, TPS6594_BIT_TWARN_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_PB_LONG, 4, TPS65224_BIT_PB_LONG_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_PB_FALL, 4, TPS65224_BIT_PB_FALL_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_PB_RISE, 4, TPS65224_BIT_PB_RISE_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_ADC_CONV_READY, 4, TPS65224_BIT_ADC_CONV_READY_INT),
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/* INT_MODERATE_ERR register */
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REGMAP_IRQ_REG(TPS65224_IRQ_TSD_ORD, 5, TPS6594_BIT_TSD_ORD_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_BIST_FAIL, 5, TPS6594_BIT_BIST_FAIL_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_REG_CRC_ERR, 5, TPS6594_BIT_REG_CRC_ERR_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_RECOV_CNT, 5, TPS6594_BIT_RECOV_CNT_INT),
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/* INT_SEVERE_ERR register */
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REGMAP_IRQ_REG(TPS65224_IRQ_TSD_IMM, 6, TPS6594_BIT_TSD_IMM_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_OVP, 6, TPS6594_BIT_VCCA_OVP_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_PFSM_ERR, 6, TPS6594_BIT_PFSM_ERR_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_BG_XMON, 6, TPS65224_BIT_BG_XMON_INT),
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/* INT_FSM_ERR register */
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REGMAP_IRQ_REG(TPS65224_IRQ_IMM_SHUTDOWN, 7, TPS6594_BIT_IMM_SHUTDOWN_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_ORD_SHUTDOWN, 7, TPS6594_BIT_ORD_SHUTDOWN_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_MCU_PWR_ERR, 7, TPS6594_BIT_MCU_PWR_ERR_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_SOC_PWR_ERR, 7, TPS6594_BIT_SOC_PWR_ERR_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_COMM_ERR, 7, TPS6594_BIT_COMM_ERR_INT),
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REGMAP_IRQ_REG(TPS65224_IRQ_I2C2_ERR, 7, TPS65224_BIT_I2C2_ERR_INT),
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};
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static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data,
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unsigned int base, int index)
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{
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@@ -443,7 +503,7 @@ static int tps6594_handle_post_irq(void *irq_drv_data)
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* a new interrupt.
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*/
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if (tps->use_crc) {
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if (tps->chip_id == TPS65224) {
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if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) {
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regmap_reg = TPS6594_REG_INT_FSM_ERR;
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mask_val = TPS6594_BIT_COMM_ERR_INT;
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} else {
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@@ -481,6 +541,18 @@ static struct regmap_irq_chip tps65224_irq_chip = {
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.handle_post_irq = tps6594_handle_post_irq,
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};
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static struct regmap_irq_chip tps652g1_irq_chip = {
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.ack_base = TPS6594_REG_INT_BUCK,
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.ack_invert = 1,
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.clear_ack = 1,
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.init_ack_masked = 1,
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.num_regs = ARRAY_SIZE(tps65224_irq_reg),
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.irqs = tps652g1_irqs,
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.num_irqs = ARRAY_SIZE(tps652g1_irqs),
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.get_irq_reg = tps65224_get_irq_reg,
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.handle_post_irq = tps6594_handle_post_irq,
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};
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static const struct regmap_range tps6594_volatile_ranges[] = {
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regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_READBACK_ERR),
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regmap_reg_range(TPS6594_REG_RTC_STATUS, TPS6594_REG_RTC_STATUS),
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@@ -507,7 +579,7 @@ static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic)
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int ret;
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unsigned int regmap_reg, mask_val;
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if (tps->chip_id == TPS65224) {
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if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) {
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regmap_reg = TPS6594_REG_CONFIG_2;
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mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN;
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} else {
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@@ -537,7 +609,7 @@ static int tps6594_set_crc_feature(struct tps6594 *tps)
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int ret;
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unsigned int regmap_reg, mask_val;
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if (tps->chip_id == TPS65224) {
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if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) {
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regmap_reg = TPS6594_REG_CONFIG_2;
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mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN;
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} else {
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@@ -628,6 +700,10 @@ int tps6594_device_init(struct tps6594 *tps, bool enable_crc)
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irq_chip = &tps65224_irq_chip;
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n_cells = ARRAY_SIZE(tps65224_common_cells);
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cells = tps65224_common_cells;
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} else if (tps->chip_id == TPS652G1) {
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irq_chip = &tps652g1_irq_chip;
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n_cells = ARRAY_SIZE(tps652g1_common_cells);
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cells = tps652g1_common_cells;
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} else {
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irq_chip = &tps6594_irq_chip;
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n_cells = ARRAY_SIZE(tps6594_common_cells);
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@@ -651,8 +727,8 @@ int tps6594_device_init(struct tps6594 *tps, bool enable_crc)
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if (ret)
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return dev_err_probe(dev, ret, "Failed to add common child devices\n");
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/* No RTC for LP8764 and TPS65224 */
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if (tps->chip_id != LP8764 && tps->chip_id != TPS65224) {
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/* No RTC for LP8764, TPS65224 and TPS652G1 */
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if (tps->chip_id != LP8764 && tps->chip_id != TPS65224 && tps->chip_id != TPS652G1) {
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ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells,
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ARRAY_SIZE(tps6594_rtc_cells), NULL, 0,
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regmap_irq_get_domain(tps->irq_data));
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