sugar/linux
1
0
Fork 0
Code Activity

Merge tag 'drm-intel-gt-next-2025-05-08-1' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

Browse Source 
Driver Changes:

- Fix SLPC wait boosting reference counting to avoid getting stuck on non-boost
  frequency on power saving profile on DG1/DG2 (Vinay)
- Add 20ms delay to engine reset for robustness on HSW (Nitin)

- Use proper sleeping functions for timeouts shorter than 20ms (Andi)
- Fix fence not released on early probe errors for HuC (Janusz)

- Remove const from struct i915_wa list allocation (Kees)
- Apply SPDX license format where missing and use single-line format (Andi)
- Whitespace fixes (Dan, Andi)
- Selftest improvements (Mikolaj, Badal, Sk,

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://lore.kernel.org/r/aBxNYp0IviE23zy-@jlahtine-mobl
This commit is contained in:
Dave Airlie
2025-05-09 11:39:27 +10:00
parent 5e0c679981 b2602a84ff
commit 8d782ad650
41 changed files with 111 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/gem/i915_gem_busy.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_clflush.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_clflush.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_context.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2011-2012 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_context.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_context_types.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2019 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright 2012 Red Hat Inc
*/

3
drivers/gpu/drm/i915/gem/i915_gem_domain.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2008,2010 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_internal.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2019 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_mman.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_mman.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2019 Intel Corporation
*/

1
drivers/gpu/drm/i915/gem/i915_gem_object.c
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: MIT
/*
* Copyright © 2017 Intel Corporation
*

3
drivers/gpu/drm/i915/gem/i915_gem_object.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_pages.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_phys.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_pm.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2019 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_pm.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2019 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_shmem.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2008-2015 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_stolen.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2008-2012 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_throttle.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2014-2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2008 Intel Corporation
*/

5
drivers/gpu/drm/i915/gem/i915_gem_userptr.c
View File

@@ -1,9 +1,8 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2012-2014 Intel Corporation
*
* Based on amdgpu_mn, which bears the following notice:
* Based on amdgpu_mn, which bears the following notice:
*
* Copyright 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.

3
drivers/gpu/drm/i915/gem/i915_gem_wait.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2016 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gemfs.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2017 Intel Corporation
*/

3
drivers/gpu/drm/i915/gem/i915_gemfs.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2017 Intel Corporation
*/

14
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
View File

@@ -1837,6 +1837,8 @@ static int igt_mmap_revoke(void *arg)
int i915_gem_mman_live_selftests(struct drm_i915_private *i915)
{
int ret;
bool unuse_mm = false;
static const struct i915_subtest tests[] = {
SUBTEST(igt_partial_tiling),
SUBTEST(igt_smoke_tiling),
@@ -1848,5 +1850,15 @@ int i915_gem_mman_live_selftests(struct drm_i915_private *i915)
SUBTEST(igt_mmap_gpu),
};
return i915_live_subtests(tests, i915);
if (!current->mm) {
kthread_use_mm(current->active_mm);
unuse_mm = true;
}
ret = i915_live_subtests(tests, i915);
if (unuse_mm)
kthread_unuse_mm(current->active_mm);
return ret;
}

1
drivers/gpu/drm/i915/gt/intel_gtt.c
View File

@@ -176,7 +176,6 @@ static void clear_vm_list(struct list_head *list)
i915_vma_destroy_locked(vma);
i915_gem_object_put(obj);
}
}
}

1
drivers/gpu/drm/i915/gt/intel_lrc.c
View File

@@ -751,7 +751,6 @@ static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
{
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
/*
* Note that the CSFE context has a dummy slot for CMD_BUF_CCTL

1
drivers/gpu/drm/i915/gt/intel_mocs.c
View File

@@ -314,7 +314,6 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
};
static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
/* UC */
MOCS_ENTRY(1, 0, L3_1_UC),
/* WB - L3 */

8
drivers/gpu/drm/i915/gt/intel_ring_submission.c
View File

@@ -365,7 +365,13 @@ static void reset_prepare(struct intel_engine_cs *engine)
ENGINE_READ_FW(engine, RING_HEAD),
ENGINE_READ_FW(engine, RING_TAIL),
ENGINE_READ_FW(engine, RING_START));
if (!stop_ring(engine)) {
/*
* Sometimes engine head failed to set to zero even after writing into it.
* Use wait_for_atomic() with 20ms delay to let engine resumes from
* correct RING_HEAD. Experimented different values and determined
* that 20ms works best based on testing.
*/
if (wait_for_atomic((!stop_ring(engine) == 0), 20)) {
drm_err(&engine->i915->drm,
"failed to set %s head to zero "
"ctl %08x head %08x tail %08x start %08x\n",

14
drivers/gpu/drm/i915/gt/intel_rps.c
View File

@@ -1003,6 +1003,10 @@ void intel_rps_dec_waiters(struct intel_rps *rps)
if (rps_uses_slpc(rps)) {
slpc = rps_to_slpc(rps);
/* Don't decrement num_waiters for req where increment was skipped */
if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING)
return;
intel_guc_slpc_dec_waiters(slpc);
} else {
atomic_dec(&rps->num_waiters);
@@ -1031,11 +1035,15 @@ void intel_rps_boost(struct i915_request *rq)
if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING)
return;
if (slpc->min_freq_softlimit >= slpc->boost_freq)
return;
/* Return if old value is non zero */
if (!atomic_fetch_inc(&slpc->num_waiters)) {
/*
* Skip queuing boost work if frequency is already boosted,
* but still increment num_waiters.
*/
if (slpc->min_freq_softlimit >= slpc->boost_freq)
return;
GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n",
rq->fence.context, rq->fence.seqno);
queue_work(rps_to_gt(rps)->i915->unordered_wq,

3
drivers/gpu/drm/i915/gt/intel_wopcm.h
View File

@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2017-2018 Intel Corporation
*/

2
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@@ -156,7 +156,7 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
struct i915_wa *list;
list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*list),
GFP_KERNEL);
if (!list) {
drm_err(&i915->drm, "No space for workaround init!\n");

9
drivers/gpu/drm/i915/gt/selftest_lrc.c
View File

@@ -7,6 +7,7 @@
#include "gem/i915_gem_internal.h"
#include "i915_drv.h"
#include "i915_selftest.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
@@ -858,6 +859,14 @@ static int live_lrc_timestamp(void *arg)
U32_MAX,
};
/*
* This test was designed to isolate a hardware bug.
* The bug was found and fixed in future generations but
* now the test pollutes our CI on previous generation.
*/
if (GRAPHICS_VER(gt->i915) == 12)
return 0;
/*
* We want to verify that the timestamp is saved and restore across
* context switches and is monotonic.

54
drivers/gpu/drm/i915/gt/selftest_rc6.c
View File

@@ -33,15 +33,22 @@ int live_rc6_manual(void *arg)
{
struct intel_gt *gt = arg;
struct intel_rc6 *rc6 = &gt->rc6;
u64 rc0_power, rc6_power;
struct intel_rps *rps = &gt->rps;
intel_wakeref_t wakeref;
u64 rc0_sample_energy[2];
u64 rc6_sample_energy[2];
u64 sleep_time = 1000;
u32 rc0_freq = 0;
u32 rc6_freq = 0;
u64 rc0_power;
u64 rc6_power;
bool has_power;
u64 threshold;
ktime_t dt;
u64 res[2];
int err = 0;
u32 rc0_freq = 0;
u32 rc6_freq = 0;
struct intel_rps *rps = &gt->rps;
u64 diff;
/*
* Our claim is that we can "encourage" the GPU to enter rc6 at will.
@@ -60,14 +67,15 @@ int live_rc6_manual(void *arg)
/* Force RC6 off for starters */
__intel_rc6_disable(rc6);
msleep(1); /* wakeup is not immediate, takes about 100us on icl */
/* wakeup is not immediate, takes about 100us on icl */
usleep_range(1000, 2000);
res[0] = rc6_residency(rc6);
dt = ktime_get();
rc0_power = librapl_energy_uJ();
msleep(1000);
rc0_power = librapl_energy_uJ() - rc0_power;
rc0_sample_energy[0] = librapl_energy_uJ();
msleep(sleep_time);
rc0_sample_energy[1] = librapl_energy_uJ() - rc0_sample_energy[0];
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
rc0_freq = intel_rps_read_actual_frequency_fw(rps);
@@ -79,11 +87,12 @@ int live_rc6_manual(void *arg)
}
if (has_power) {
rc0_power = div64_u64(NSEC_PER_SEC * rc0_power,
rc0_power = div64_u64(NSEC_PER_SEC * rc0_sample_energy[1],
ktime_to_ns(dt));
if (!rc0_power) {
if (rc0_freq)
pr_debug("No power measured while in RC0! GPU Freq: %u in RC0\n",
pr_debug("No power measured while in RC0! GPU Freq: %uMHz in RC0\n",
rc0_freq);
else
pr_err("No power and freq measured while in RC0\n");
@@ -98,10 +107,10 @@ int live_rc6_manual(void *arg)
res[0] = rc6_residency(rc6);
intel_uncore_forcewake_flush(rc6_to_uncore(rc6), FORCEWAKE_ALL);
dt = ktime_get();
rc6_power = librapl_energy_uJ();
msleep(1000);
rc6_sample_energy[0] = librapl_energy_uJ();
msleep(sleep_time);
rc6_freq = intel_rps_read_actual_frequency_fw(rps);
rc6_power = librapl_energy_uJ() - rc6_power;
rc6_sample_energy[1] = librapl_energy_uJ() - rc6_sample_energy[0];
dt = ktime_sub(ktime_get(), dt);
res[1] = rc6_residency(rc6);
if (res[1] == res[0]) {
@@ -113,13 +122,24 @@ int live_rc6_manual(void *arg)
}
if (has_power) {
rc6_power = div64_u64(NSEC_PER_SEC * rc6_power,
rc6_power = div64_u64(NSEC_PER_SEC * rc6_sample_energy[1],
ktime_to_ns(dt));
pr_info("GPU consumed %llduW in RC0 and %llduW in RC6\n",
pr_info("GPU consumed %lluuW in RC0 and %lluuW in RC6\n",
rc0_power, rc6_power);
if (2 * rc6_power > rc0_power) {
pr_err("GPU leaked energy while in RC6! GPU Freq: %u in RC6 and %u in RC0\n",
rc6_freq, rc0_freq);
pr_err("GPU leaked energy while in RC6!\n"
"GPU Freq: %uMHz in RC6 and %uMHz in RC0\n"
"RC0 energy before & after sleep respectively: %lluuJ %lluuJ\n"
"RC6 energy before & after sleep respectively: %lluuJ %lluuJ\n",
rc6_freq, rc0_freq, rc0_sample_energy[0], rc0_sample_energy[1],
rc6_sample_energy[0], rc6_sample_energy[1]);
diff = res[1] - res[0];
threshold = (9 * NSEC_PER_MSEC * sleep_time) / 10;
if (diff < threshold)
pr_err("Did not enter RC6 properly, RC6 start residency=%lluns, RC6 end residency=%lluns\n",
res[0], res[1]);
err = -EINVAL;
goto out_unlock;
}

2
drivers/gpu/drm/i915/gt/selftest_tlb.c
View File

@@ -143,7 +143,7 @@ pte_tlbinv(struct intel_context *ce,
if (ce->engine->class == OTHER_CLASS)
msleep(200);
else
msleep(10);
usleep_range(10000, 20000);
if (va == vb) {
if (!i915_request_completed(rq)) {

2
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
View File

@@ -230,7 +230,7 @@ int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data, s
gt_info(gt, "Invalid GSC firmware for MTL/ARL, got %d.%d.%d.%d but need 102.x.x.x",
gsc->release.major, gsc->release.minor,
gsc->release.patch, gsc->release.build);
return -EINVAL;
return -EINVAL;
}
if (min_ver.major) {