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Merge tag 'icc-6.17-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next

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Georgi writes:

interconnect changes for 6.17

This pull request contains the interconnect changes for the 6.17-rc1
merge window. It contains only driver changes.

Driver changes:
- SC8180X and SC8280XP driver fixes
- Add new driver for the Qualcomm Milos SoC
- Add Support for EPSS L3 hardware in QCS8300 SoC
- DT bindings fixes and other cleanups

Signed-off-by: Georgi Djakov <djakov@kernel.org>

* tag 'icc-6.17-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
  interconnect: qcom: Add Milos interconnect provider driver
  dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC
  dt-bindings: interconnect: qcom,msm8998-bwmon: Allow 'nonposted-mmio'
  dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC
  dt-bindings: interconnect: qcom: Remove double colon from description
  interconnect: qcom: qcs615: Drop IP0 interconnects
  interconnect: qcom: sc8180x: specify num_nodes
  interconnect: qcom: sc8280xp: specify num_links for qnm_a1noc_cfg
This commit is contained in:
Greg Kroah-Hartman
2025-07-24 08:03:36 +02:00
parent 35b6fc51c6 ca652cf0c2
commit a6d283c526
20 changed files with 2243 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

136
Documentation/devicetree/bindings/interconnect/qcom,milos-rpmh.yaml Normal file
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@@ -0,0 +1,136 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,milos-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on Milos SoC
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also: include/dt-bindings/interconnect/qcom,milos-rpmh.h
properties:
compatible:
enum:
- qcom,milos-aggre1-noc
- qcom,milos-aggre2-noc
- qcom,milos-clk-virt
- qcom,milos-cnoc-cfg
- qcom,milos-cnoc-main
- qcom,milos-gem-noc
- qcom,milos-lpass-ag-noc
- qcom,milos-mc-virt
- qcom,milos-mmss-noc
- qcom,milos-nsp-noc
- qcom,milos-pcie-anoc
- qcom,milos-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,milos-clk-virt
- qcom,milos-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,milos-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,milos-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre USB3 PRIM AXI clock
- description: aggre UFS PHY AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,milos-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,milos-aggre1-noc
- qcom,milos-aggre2-noc
- qcom,milos-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
interconnect-0 {
compatible = "qcom,milos-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
interconnect@16e0000 {
compatible = "qcom,milos-aggre1-noc";
reg = <0x016e0000 0x16400>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
View File

@@ -76,6 +76,8 @@ properties:
minItems: 1
maxItems: 2
nonposted-mmio: true
required:
- compatible
- interconnects

5
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
View File

@@ -36,6 +36,11 @@ properties:
- qcom,sm8350-epss-l3
- qcom,sm8650-epss-l3
- const: qcom,epss-l3
- items:
- enum:
- qcom,qcs8300-epss-l3
- const: qcom,sa8775p-epss-l3
- const: qcom,epss-l3
reg:
maxItems: 1

2
Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
View File

@@ -13,7 +13,7 @@ description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sa8775p.h
See also: include/dt-bindings/interconnect/qcom,sa8775p.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,sar2130p-rpmh.yaml
View File

@@ -18,7 +18,7 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
See also: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
View File

@@ -14,7 +14,7 @@ description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sc7280.h
See also: include/dt-bindings/interconnect/qcom,sc7280.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml
View File

@@ -14,7 +14,7 @@ description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h
See also: include/dt-bindings/interconnect/qcom,sc8280xp.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,sm7150-rpmh.yaml
View File

@@ -13,7 +13,7 @@ description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
See also: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
allOf:
- $ref: qcom,rpmh-common.yaml#

2
Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml
View File

@@ -14,7 +14,7 @@ description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sm8450.h
See also: include/dt-bindings/interconnect/qcom,sm8450.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml
View File

@@ -18,7 +18,7 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
See also: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,sm8650-rpmh.yaml
View File

@@ -18,7 +18,7 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
See also: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,sm8750-rpmh.yaml
View File

@@ -18,7 +18,7 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
See also: include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
properties:
compatible:

2
Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml
View File

@@ -18,7 +18,7 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
See also: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
properties:
compatible:

9
drivers/interconnect/qcom/Kconfig
View File

@@ -283,6 +283,15 @@ config INTERCONNECT_QCOM_SM7150
This is a driver for the Qualcomm Network-on-Chip on sm7150-based
platforms.
config INTERCONNECT_QCOM_MILOS
tristate "Qualcomm Milos interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on Milos-based
platforms.
config INTERCONNECT_QCOM_SM8150
tristate "Qualcomm SM8150 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

2
drivers/interconnect/qcom/Makefile
View File

@@ -4,6 +4,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o
interconnect_qcom-y := icc-common.o
icc-bcm-voter-objs := bcm-voter.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
qnoc-msm8916-objs := msm8916.o
qnoc-msm8937-objs := msm8937.o
@@ -45,6 +46,7 @@ qnoc-x1e80100-objs := x1e80100.o
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8937) += qnoc-msm8937.o

1931
drivers/interconnect/qcom/milos.c Normal file
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File diff suppressed because it is too large Load Diff

42
drivers/interconnect/qcom/qcs615.c
View File

@@ -342,15 +342,6 @@ static struct qcom_icc_node qnm_snoc_sf = {
.links = { QCS615_SLAVE_LLCC },
};
static struct qcom_icc_node ipa_core_master = {
.name = "ipa_core_master",
.id = QCS615_MASTER_IPA_CORE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { QCS615_SLAVE_IPA_CORE },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = QCS615_MASTER_LLCC,
@@ -942,14 +933,6 @@ static struct qcom_icc_node srvc_gemnoc = {
.num_links = 0,
};
static struct qcom_icc_node ipa_core_slave = {
.name = "ipa_core_slave",
.id = QCS615_SLAVE_IPA_CORE,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = QCS615_SLAVE_EBI1,
@@ -1113,12 +1096,6 @@ static struct qcom_icc_bcm bcm_cn1 = {
&qhs_sdc1, &qhs_sdc2 },
};
static struct qcom_icc_bcm bcm_ip0 = {
.name = "IP0",
.num_nodes = 1,
.nodes = { &ipa_core_slave },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
@@ -1260,7 +1237,6 @@ static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
&bcm_qup0,
&bcm_sn3,
&bcm_sn14,
&bcm_ip0,
};
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
@@ -1411,22 +1387,6 @@ static const struct qcom_icc_desc qcs615_gem_noc = {
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_node * const ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
};
static const struct qcom_icc_desc qcs615_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
@@ -1525,8 +1485,6 @@ static const struct of_device_id qnoc_of_match[] = {
.data = &qcs615_dc_noc},
{ .compatible = "qcom,qcs615-gem-noc",
.data = &qcs615_gem_noc},
{ .compatible = "qcom,qcs615-ipa-virt",
.data = &qcs615_ipa_virt},
{ .compatible = "qcom,qcs615-mc-virt",
.data = &qcs615_mc_virt},
{ .compatible = "qcom,qcs615-mmss-noc",

6
drivers/interconnect/qcom/sc8180x.c
View File

@@ -1492,34 +1492,40 @@ static struct qcom_icc_bcm bcm_sh3 = {
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.num_nodes = 1,
.nodes = { &slv_qns_gemnoc_sf }
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.num_nodes = 1,
.nodes = { &slv_qxs_imem }
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = true,
.num_nodes = 1,
.nodes = { &slv_qns_gemnoc_gc }
};
static struct qcom_icc_bcm bcm_co2 = {
.name = "CO2",
.num_nodes = 1,
.nodes = { &mas_qnm_npu }
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = true,
.num_nodes = 2,
.nodes = { &slv_srvc_aggre1_noc,
&slv_qns_cnoc }
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.num_nodes = 1,
.nodes = { &slv_qxs_pimem }
};

1
drivers/interconnect/qcom/sc8280xp.c
View File

@@ -48,6 +48,7 @@ static struct qcom_icc_node qnm_a1noc_cfg = {
.id = SC8280XP_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC8280XP_SLAVE_SERVICE_A1NOC },
};

141
include/dt-bindings/interconnect/qcom,milos-rpmh.h Normal file
View File

@@ -0,0 +1,141 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H
#define MASTER_QUP_1 0
#define MASTER_UFS_MEM 1
#define MASTER_USB3_0 2
#define SLAVE_A1NOC_SNOC 3
#define MASTER_QDSS_BAM 0
#define MASTER_QSPI_0 1
#define MASTER_QUP_0 2
#define MASTER_CRYPTO 3
#define MASTER_IPA 4
#define MASTER_QDSS_ETR 5
#define MASTER_QDSS_ETR_1 6
#define MASTER_SDCC_1 7
#define MASTER_SDCC_2 8
#define SLAVE_A2NOC_SNOC 9
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define SLAVE_QUP_CORE_0 2
#define SLAVE_QUP_CORE_1 3
#define MASTER_CNOC_CFG 0
#define SLAVE_AHB2PHY_SOUTH 1
#define SLAVE_AHB2PHY_NORTH 2
#define SLAVE_CAMERA_CFG 3
#define SLAVE_CLK_CTL 4
#define SLAVE_RBCPR_CX_CFG 5
#define SLAVE_RBCPR_MXA_CFG 6
#define SLAVE_CRYPTO_0_CFG 7
#define SLAVE_CX_RDPM 8
#define SLAVE_GFX3D_CFG 9
#define SLAVE_IMEM_CFG 10
#define SLAVE_CNOC_MSS 11
#define SLAVE_MX_2_RDPM 12
#define SLAVE_MX_RDPM 13
#define SLAVE_PDM 14
#define SLAVE_QDSS_CFG 15
#define SLAVE_QSPI_0 16
#define SLAVE_QUP_0 17
#define SLAVE_QUP_1 18
#define SLAVE_SDC1 19
#define SLAVE_SDCC_2 20
#define SLAVE_TCSR 21
#define SLAVE_TLMM 22
#define SLAVE_UFS_MEM_CFG 23
#define SLAVE_USB3_0 24
#define SLAVE_VENUS_CFG 25
#define SLAVE_VSENSE_CTRL_CFG 26
#define SLAVE_WLAN 27
#define SLAVE_CNOC_MNOC_HF_CFG 28
#define SLAVE_CNOC_MNOC_SF_CFG 29
#define SLAVE_NSP_QTB_CFG 30
#define SLAVE_PCIE_ANOC_CFG 31
#define SLAVE_WLAN_Q6_THROTTLE_CFG 32
#define SLAVE_SERVICE_CNOC_CFG 33
#define SLAVE_QDSS_STM 34
#define SLAVE_TCU 35
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AOSS 2
#define SLAVE_DISPLAY_CFG 3
#define SLAVE_IPA_CFG 4
#define SLAVE_IPC_ROUTER_CFG 5
#define SLAVE_PCIE_0_CFG 6
#define SLAVE_PCIE_1_CFG 7
#define SLAVE_PRNG 8
#define SLAVE_TME_CFG 9
#define SLAVE_APPSS 10
#define SLAVE_CNOC_CFG 11
#define SLAVE_DDRSS_CFG 12
#define SLAVE_IMEM 13
#define SLAVE_PIMEM 14
#define SLAVE_SERVICE_CNOC 15
#define SLAVE_PCIE_0 16
#define SLAVE_PCIE_1 17
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_GFX3D 3
#define MASTER_LPASS_GEM_NOC 4
#define MASTER_MSS_PROC 5
#define MASTER_MNOC_HF_MEM_NOC 6
#define MASTER_MNOC_SF_MEM_NOC 7
#define MASTER_COMPUTE_NOC 8
#define MASTER_ANOC_PCIE_GEM_NOC 9
#define MASTER_SNOC_GC_MEM_NOC 10
#define MASTER_SNOC_SF_MEM_NOC 11
#define MASTER_WLAN_Q6 12
#define SLAVE_GEM_NOC_CNOC 13
#define SLAVE_LLCC 14
#define SLAVE_MEM_NOC_PCIE_SNOC 15
#define MASTER_LPASS_PROC 0
#define SLAVE_LPASS_GEM_NOC 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_ICP 1
#define MASTER_CAMNOC_SF 2
#define MASTER_MDP 3
#define MASTER_VIDEO 4
#define MASTER_CNOC_MNOC_HF_CFG 5
#define MASTER_CNOC_MNOC_SF_CFG 6
#define SLAVE_MNOC_HF_MEM_NOC 7
#define SLAVE_MNOC_SF_MEM_NOC 8
#define SLAVE_SERVICE_MNOC_HF 9
#define SLAVE_SERVICE_MNOC_SF 10
#define MASTER_CDSP_PROC 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_PCIE_ANOC_CFG 0
#define MASTER_PCIE_0 1
#define MASTER_PCIE_1 2
#define SLAVE_ANOC_PCIE_GEM_NOC 3
#define SLAVE_SERVICE_PCIE_ANOC 4
#define MASTER_A1NOC_SNOC 0
#define MASTER_A2NOC_SNOC 1
#define MASTER_APSS_NOC 2
#define MASTER_CNOC_SNOC 3
#define MASTER_PIMEM 4
#define MASTER_GIC 5
#define SLAVE_SNOC_GEM_NOC_GC 6
#define SLAVE_SNOC_GEM_NOC_SF 7
#endif