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dt-bindings: phy: qcom: uniphy-pcie: Add ipq5018 compatible

The IPQ5018 SoC contains a Gen2 1 and 2-lane PCIe UNIPHY which is the
same as the one found in IPQ5332. As such, add IPQ5018 compatible.

Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-1-e1828fef06c9@outlook.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Nitheesh Sekar
2025-03-26 12:10:55 +04:00
committed by Vinod Koul
parent 0cc22f5a86
commit aae29082b6

View File

@@ -11,26 +11,24 @@ maintainers:
- Varadarajan Narayanan <quic_varada@quicinc.com>
description:
PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs
properties:
compatible:
enum:
- qcom,ipq5018-uniphy-pcie-phy
- qcom,ipq5332-uniphy-pcie-phy
reg:
maxItems: 1
clocks:
items:
- description: pcie pipe clock
- description: pcie ahb clock
minItems: 1
maxItems: 2
resets:
items:
- description: phy reset
- description: ahb reset
- description: cfg reset
minItems: 2
maxItems: 3
"#phy-cells":
const: 0
@@ -53,6 +51,41 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq5018-uniphy-pcie-phy
then:
properties:
clocks:
items:
- description: pcie pipe clock
resets:
items:
- description: phy reset
- description: cfg reset
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq5332-uniphy-pcie-phy
then:
properties:
clocks:
items:
- description: pcie pipe clock
- description: pcie ahb clock
resets:
items:
- description: phy reset
- description: ahb reset
- description: cfg reset
examples:
- |
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>