Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next
- Speed up clk_core_lookup() by using a hashtable * clk-microchip: ARM: at91: remove default values for PMC_PLL_ACR clk: at91: add ACR in all PLL settings clk: at91: sam9x7: Add peripheral clock id for pmecc clk: at91: clk-master: Add check for divide by 3 clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register ARM: at91: pm: save and restore ACR during PLL disable/enable * clk-lookup: clk: Use hashtable for global clk lookups clk: Sort include statements * clk-st: dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings
This commit is contained in:
Stephen Boyd
199
Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml
Normal file
199
Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml
Normal file
@@ -0,0 +1,199 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32MP21 Reset Clock Controller
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maintainers:
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- Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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description: |
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The RCC hardware block is both a reset and a clock controller.
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RCC makes also power management (resume/suspend).
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See also:
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include/dt-bindings/clock/st,stm32mp21-rcc.h
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include/dt-bindings/reset/st,stm32mp21-rcc.h
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properties:
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compatible:
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enum:
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- st,stm32mp21-rcc
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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clocks:
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items:
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- description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
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- description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
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- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
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- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
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- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
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- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
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- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
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- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
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- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
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- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
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- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
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- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
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- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
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- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
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- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
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- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
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- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
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- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
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- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
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- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
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- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
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- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
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- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
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- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
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- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
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- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
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- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
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- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
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- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
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- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
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- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
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- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
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- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
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- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
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- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
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- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
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- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
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- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
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- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
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- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
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- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
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- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
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- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
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- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
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- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
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- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
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- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
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- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
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- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
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- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
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- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
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- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
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- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
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- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
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- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
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- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
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- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
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- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
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- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
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- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
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- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
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- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
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- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
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- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
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- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
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- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
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- description: CK_SCMI_ICN_APB5 Peripheral bridge 5
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- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
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- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
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- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
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access-controllers:
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maxItems: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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- '#reset-cells'
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/st,stm32mp21-rcc.h>
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clock-controller@44200000 {
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compatible = "st,stm32mp21-rcc";
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reg = <0x44200000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_MSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>,
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<&scmi_clk CK_SCMI_HSE_DIV2>,
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<&scmi_clk CK_SCMI_ICN_HS_MCU>,
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<&scmi_clk CK_SCMI_ICN_LS_MCU>,
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<&scmi_clk CK_SCMI_ICN_SDMMC>,
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<&scmi_clk CK_SCMI_ICN_DDR>,
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<&scmi_clk CK_SCMI_ICN_DISPLAY>,
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<&scmi_clk CK_SCMI_ICN_HSL>,
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<&scmi_clk CK_SCMI_ICN_NIC>,
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<&scmi_clk CK_SCMI_FLEXGEN_07>,
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<&scmi_clk CK_SCMI_FLEXGEN_08>,
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<&scmi_clk CK_SCMI_FLEXGEN_09>,
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<&scmi_clk CK_SCMI_FLEXGEN_10>,
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<&scmi_clk CK_SCMI_FLEXGEN_11>,
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<&scmi_clk CK_SCMI_FLEXGEN_12>,
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<&scmi_clk CK_SCMI_FLEXGEN_13>,
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<&scmi_clk CK_SCMI_FLEXGEN_14>,
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<&scmi_clk CK_SCMI_FLEXGEN_16>,
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<&scmi_clk CK_SCMI_FLEXGEN_17>,
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<&scmi_clk CK_SCMI_FLEXGEN_18>,
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<&scmi_clk CK_SCMI_FLEXGEN_19>,
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<&scmi_clk CK_SCMI_FLEXGEN_20>,
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<&scmi_clk CK_SCMI_FLEXGEN_21>,
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<&scmi_clk CK_SCMI_FLEXGEN_22>,
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<&scmi_clk CK_SCMI_FLEXGEN_23>,
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<&scmi_clk CK_SCMI_FLEXGEN_24>,
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<&scmi_clk CK_SCMI_FLEXGEN_25>,
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<&scmi_clk CK_SCMI_FLEXGEN_26>,
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<&scmi_clk CK_SCMI_FLEXGEN_27>,
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<&scmi_clk CK_SCMI_FLEXGEN_29>,
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<&scmi_clk CK_SCMI_FLEXGEN_30>,
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<&scmi_clk CK_SCMI_FLEXGEN_31>,
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<&scmi_clk CK_SCMI_FLEXGEN_33>,
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<&scmi_clk CK_SCMI_FLEXGEN_36>,
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<&scmi_clk CK_SCMI_FLEXGEN_37>,
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<&scmi_clk CK_SCMI_FLEXGEN_38>,
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<&scmi_clk CK_SCMI_FLEXGEN_39>,
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<&scmi_clk CK_SCMI_FLEXGEN_40>,
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<&scmi_clk CK_SCMI_FLEXGEN_41>,
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<&scmi_clk CK_SCMI_FLEXGEN_42>,
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<&scmi_clk CK_SCMI_FLEXGEN_43>,
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<&scmi_clk CK_SCMI_FLEXGEN_44>,
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<&scmi_clk CK_SCMI_FLEXGEN_45>,
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<&scmi_clk CK_SCMI_FLEXGEN_46>,
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<&scmi_clk CK_SCMI_FLEXGEN_47>,
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<&scmi_clk CK_SCMI_FLEXGEN_48>,
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<&scmi_clk CK_SCMI_FLEXGEN_50>,
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<&scmi_clk CK_SCMI_FLEXGEN_51>,
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<&scmi_clk CK_SCMI_FLEXGEN_52>,
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<&scmi_clk CK_SCMI_FLEXGEN_53>,
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<&scmi_clk CK_SCMI_FLEXGEN_54>,
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<&scmi_clk CK_SCMI_FLEXGEN_55>,
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<&scmi_clk CK_SCMI_FLEXGEN_56>,
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<&scmi_clk CK_SCMI_FLEXGEN_57>,
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<&scmi_clk CK_SCMI_FLEXGEN_58>,
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<&scmi_clk CK_SCMI_FLEXGEN_61>,
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<&scmi_clk CK_SCMI_FLEXGEN_62>,
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<&scmi_clk CK_SCMI_FLEXGEN_63>,
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<&scmi_clk CK_SCMI_ICN_APB1>,
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<&scmi_clk CK_SCMI_ICN_APB2>,
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<&scmi_clk CK_SCMI_ICN_APB3>,
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<&scmi_clk CK_SCMI_ICN_APB4>,
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<&scmi_clk CK_SCMI_ICN_APB5>,
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<&scmi_clk CK_SCMI_ICN_APBDBG>,
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<&scmi_clk CK_SCMI_TIMG1>,
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<&scmi_clk CK_SCMI_TIMG2>;
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};
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...
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@@ -11,9 +11,9 @@ maintainers:
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description: |
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The RCC hardware block is both a reset and a clock controller.
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RCC makes also power management (resume/supend).
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RCC makes also power management (resume/suspend).
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See also::
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See also:
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include/dt-bindings/clock/st,stm32mp25-rcc.h
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include/dt-bindings/reset/st,stm32mp25-rcc.h
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@@ -38,7 +38,7 @@ properties:
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- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
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- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
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- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
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- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
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- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
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- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
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- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
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- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
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@@ -108,15 +108,14 @@ properties:
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- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
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- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
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- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
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- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
|
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- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
|
||||
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
|
||||
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
|
||||
- description: CK_SCMI_PLL3 PLL3 clock
|
||||
- description: clk_dsi_txbyte DSI byte clock
|
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||||
access-controllers:
|
||||
minItems: 1
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||||
maxItems: 2
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
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@@ -131,7 +130,7 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
|
||||
|
||||
rcc: clock-controller@44200000 {
|
||||
clock-controller@44200000 {
|
||||
compatible = "st,stm32mp25-rcc";
|
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reg = <0x44200000 0x10000>;
|
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#clock-cells = <1>;
|
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@@ -689,6 +689,10 @@ sr_dis_exit:
|
||||
bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
|
||||
str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
|
||||
|
||||
/* save acr */
|
||||
ldr tmp2, [pmc, #AT91_PMC_PLL_ACR]
|
||||
str tmp2, .saved_acr
|
||||
|
||||
/* save div. */
|
||||
mov tmp1, #0
|
||||
ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
|
||||
@@ -758,7 +762,7 @@ sr_dis_exit:
|
||||
str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
|
||||
|
||||
/* step 2. */
|
||||
ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
|
||||
ldr tmp1, .saved_acr
|
||||
str tmp1, [pmc, #AT91_PMC_PLL_ACR]
|
||||
|
||||
/* step 3. */
|
||||
@@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram)
|
||||
#endif
|
||||
.saved_mckr:
|
||||
.word 0
|
||||
.saved_acr:
|
||||
.word 0
|
||||
.saved_pllar:
|
||||
.word 0
|
||||
.saved_sam9_lpr:
|
||||
|
||||
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
|
||||
{
|
||||
struct clk_master *master = to_clk_master(hw);
|
||||
|
||||
if (master->div == MASTER_PRES_MAX)
|
||||
return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
|
||||
}
|
||||
|
||||
|
||||
@@ -93,8 +93,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
|
||||
|
||||
spin_lock_irqsave(core->lock, flags);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
|
||||
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
|
||||
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
|
||||
@@ -103,11 +103,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
|
||||
(cmul == frac->mul && cfrac == frac->frac))
|
||||
goto unlock;
|
||||
|
||||
/* Recommended value for PMC_PLL_ACR */
|
||||
if (core->characteristics->upll)
|
||||
val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
|
||||
else
|
||||
val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
|
||||
/* Load recommended value for PMC_PLL_ACR */
|
||||
val = core->characteristics->acr;
|
||||
regmap_write(regmap, AT91_PMC_PLL_ACR, val);
|
||||
|
||||
regmap_write(regmap, AT91_PMC_PLL_CTRL1,
|
||||
@@ -128,17 +125,17 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
|
||||
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
|
||||
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
|
||||
while (!sam9x60_pll_ready(regmap, core->id))
|
||||
cpu_relax();
|
||||
@@ -164,8 +161,8 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
|
||||
|
||||
spin_lock_irqsave(core->lock, flags);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
|
||||
|
||||
@@ -173,9 +170,9 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
|
||||
AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
|
||||
spin_unlock_irqrestore(core->lock, flags);
|
||||
}
|
||||
@@ -262,8 +259,8 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
|
||||
|
||||
spin_lock_irqsave(core->lock, irqflags);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
core->id);
|
||||
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
|
||||
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
|
||||
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
|
||||
@@ -275,18 +272,18 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
|
||||
(frac->mul << core->layout->mul_shift) |
|
||||
(frac->frac << core->layout->frac_shift));
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
|
||||
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
|
||||
AT91_PMC_PLL_CTRL0_ENLOCK |
|
||||
AT91_PMC_PLL_CTRL0_ENPLL);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
|
||||
while (!sam9x60_pll_ready(regmap, core->id))
|
||||
cpu_relax();
|
||||
@@ -338,7 +335,10 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = {
|
||||
.restore_context = sam9x60_frac_pll_restore_context,
|
||||
};
|
||||
|
||||
/* This function should be called with spinlock acquired. */
|
||||
/* This function should be called with spinlock acquired.
|
||||
* Warning: this function must be called only if the same PLL ID was set in
|
||||
* PLL_UPDT register previously.
|
||||
*/
|
||||
static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
|
||||
bool enable)
|
||||
{
|
||||
@@ -350,9 +350,9 @@ static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
|
||||
core->layout->div_mask | ena_msk,
|
||||
(div << core->layout->div_shift) | ena_val);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
|
||||
while (!sam9x60_pll_ready(regmap, core->id))
|
||||
cpu_relax();
|
||||
@@ -366,8 +366,8 @@ static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
|
||||
unsigned int val, cdiv;
|
||||
|
||||
spin_lock_irqsave(core->lock, flags);
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
|
||||
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
|
||||
|
||||
@@ -398,15 +398,15 @@ static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
|
||||
|
||||
spin_lock_irqsave(core->lock, flags);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
|
||||
core->layout->endiv_mask, 0);
|
||||
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
AT91_PMC_PLL_UPDT_UPDATE | core->id);
|
||||
|
||||
spin_unlock_irqrestore(core->lock, flags);
|
||||
}
|
||||
@@ -518,8 +518,8 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
|
||||
div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
|
||||
|
||||
spin_lock_irqsave(core->lock, irqflags);
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
core->id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
core->id);
|
||||
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
|
||||
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
|
||||
|
||||
@@ -574,8 +574,8 @@ static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
|
||||
div->div = div->safe_div;
|
||||
|
||||
spin_lock_irqsave(core.lock, irqflags);
|
||||
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
core.id);
|
||||
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
|
||||
core.id);
|
||||
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
|
||||
cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
|
||||
|
||||
|
||||
@@ -80,6 +80,7 @@ struct clk_pll_characteristics {
|
||||
u16 *icpll;
|
||||
u8 *out;
|
||||
u8 upll : 1;
|
||||
u32 acr;
|
||||
};
|
||||
|
||||
struct clk_programmable_layout {
|
||||
|
||||
@@ -36,6 +36,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
|
||||
.num_output = ARRAY_SIZE(plla_outputs),
|
||||
.output = plla_outputs,
|
||||
.core_output = core_outputs,
|
||||
.acr = UL(0x00020010),
|
||||
};
|
||||
|
||||
static const struct clk_range upll_outputs[] = {
|
||||
@@ -48,6 +49,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
|
||||
.output = upll_outputs,
|
||||
.core_output = core_outputs,
|
||||
.upll = true,
|
||||
.acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/
|
||||
};
|
||||
|
||||
static const struct clk_pll_layout pll_frac_layout = {
|
||||
|
||||
@@ -107,6 +107,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
|
||||
.num_output = ARRAY_SIZE(plla_outputs),
|
||||
.output = plla_outputs,
|
||||
.core_output = plla_core_outputs,
|
||||
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
|
||||
};
|
||||
|
||||
static const struct clk_pll_characteristics upll_characteristics = {
|
||||
@@ -115,6 +116,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
|
||||
.output = upll_outputs,
|
||||
.core_output = upll_core_outputs,
|
||||
.upll = true,
|
||||
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
|
||||
};
|
||||
|
||||
static const struct clk_pll_characteristics lvdspll_characteristics = {
|
||||
@@ -122,6 +124,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(lvdspll_outputs),
|
||||
.output = lvdspll_outputs,
|
||||
.core_output = lvdspll_core_outputs,
|
||||
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
|
||||
};
|
||||
|
||||
static const struct clk_pll_characteristics audiopll_characteristics = {
|
||||
@@ -129,6 +132,7 @@ static const struct clk_pll_characteristics audiopll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(audiopll_outputs),
|
||||
.output = audiopll_outputs,
|
||||
.core_output = audiopll_core_outputs,
|
||||
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
|
||||
};
|
||||
|
||||
static const struct clk_pll_characteristics plladiv2_characteristics = {
|
||||
@@ -136,6 +140,7 @@ static const struct clk_pll_characteristics plladiv2_characteristics = {
|
||||
.num_output = ARRAY_SIZE(plladiv2_outputs),
|
||||
.output = plladiv2_outputs,
|
||||
.core_output = plladiv2_core_outputs,
|
||||
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
|
||||
};
|
||||
|
||||
/* Layout for fractional PLL ID PLLA. */
|
||||
@@ -403,6 +408,7 @@ static const struct {
|
||||
{ .n = "pioD_clk", .id = 44, },
|
||||
{ .n = "tcb1_clk", .id = 45, },
|
||||
{ .n = "dbgu_clk", .id = 47, },
|
||||
{ .n = "pmecc_clk", .id = 48, },
|
||||
/*
|
||||
* mpddr_clk feeds DDR controller and is enabled by bootloader thus we
|
||||
* need to keep it enabled in case there is no Linux consumer for it.
|
||||
|
||||
@@ -138,6 +138,7 @@ static const struct clk_pll_characteristics cpu_pll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(cpu_pll_outputs),
|
||||
.output = cpu_pll_outputs,
|
||||
.core_output = core_outputs,
|
||||
.acr = UL(0x00070010),
|
||||
};
|
||||
|
||||
/* PLL characteristics. */
|
||||
@@ -146,6 +147,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(pll_outputs),
|
||||
.output = pll_outputs,
|
||||
.core_output = core_outputs,
|
||||
.acr = UL(0x00070010),
|
||||
};
|
||||
|
||||
static const struct clk_pll_characteristics lvdspll_characteristics = {
|
||||
@@ -153,6 +155,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(lvdspll_outputs),
|
||||
.output = lvdspll_outputs,
|
||||
.core_output = lvdspll_core_outputs,
|
||||
.acr = UL(0x00070010),
|
||||
};
|
||||
|
||||
static const struct clk_pll_characteristics upll_characteristics = {
|
||||
@@ -160,6 +163,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(upll_outputs),
|
||||
.output = upll_outputs,
|
||||
.core_output = upll_core_outputs,
|
||||
.acr = UL(0x12020010),
|
||||
.upll = true,
|
||||
};
|
||||
|
||||
|
||||
@@ -113,6 +113,7 @@ static const struct clk_pll_characteristics cpu_pll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(cpu_pll_outputs),
|
||||
.output = cpu_pll_outputs,
|
||||
.core_output = core_outputs,
|
||||
.acr = UL(0x00070010),
|
||||
};
|
||||
|
||||
/* PLL characteristics. */
|
||||
@@ -121,6 +122,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
|
||||
.num_output = ARRAY_SIZE(pll_outputs),
|
||||
.output = pll_outputs,
|
||||
.core_output = core_outputs,
|
||||
.acr = UL(0x00070010),
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
@@ -6,21 +6,24 @@
|
||||
* Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
|
||||
*/
|
||||
|
||||
#include <linux/clk/clk-conf.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/clk-conf.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/hashtable.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/stringhash.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
@@ -33,6 +36,9 @@ static struct task_struct *enable_owner;
|
||||
static int prepare_refcnt;
|
||||
static int enable_refcnt;
|
||||
|
||||
#define CLK_HASH_BITS 9
|
||||
static DEFINE_HASHTABLE(clk_hashtable, CLK_HASH_BITS);
|
||||
|
||||
static HLIST_HEAD(clk_root_list);
|
||||
static HLIST_HEAD(clk_orphan_list);
|
||||
static LIST_HEAD(clk_notifier_list);
|
||||
@@ -87,6 +93,7 @@ struct clk_core {
|
||||
struct clk_duty duty;
|
||||
struct hlist_head children;
|
||||
struct hlist_node child_node;
|
||||
struct hlist_node hashtable_node;
|
||||
struct hlist_head clks;
|
||||
unsigned int notifier_count;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
@@ -395,45 +402,20 @@ struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_hw_get_parent);
|
||||
|
||||
static struct clk_core *__clk_lookup_subtree(const char *name,
|
||||
struct clk_core *core)
|
||||
{
|
||||
struct clk_core *child;
|
||||
struct clk_core *ret;
|
||||
|
||||
if (!strcmp(core->name, name))
|
||||
return core;
|
||||
|
||||
hlist_for_each_entry(child, &core->children, child_node) {
|
||||
ret = __clk_lookup_subtree(name, child);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct clk_core *clk_core_lookup(const char *name)
|
||||
{
|
||||
struct clk_core *root_clk;
|
||||
struct clk_core *ret;
|
||||
struct clk_core *core;
|
||||
u32 hash;
|
||||
|
||||
if (!name)
|
||||
return NULL;
|
||||
|
||||
/* search the 'proper' clk tree first */
|
||||
hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
|
||||
ret = __clk_lookup_subtree(name, root_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
hash = full_name_hash(NULL, name, strlen(name));
|
||||
|
||||
/* if not found, then search the orphan tree */
|
||||
hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
|
||||
ret = __clk_lookup_subtree(name, root_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
/* search the hashtable */
|
||||
hash_for_each_possible(clk_hashtable, core, hashtable_node, hash)
|
||||
if (!strcmp(core->name, name))
|
||||
return core;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
@@ -4013,6 +3995,8 @@ static int __clk_core_init(struct clk_core *core)
|
||||
hlist_add_head(&core->child_node, &clk_orphan_list);
|
||||
core->orphan = true;
|
||||
}
|
||||
hash_add(clk_hashtable, &core->hashtable_node,
|
||||
full_name_hash(NULL, core->name, strlen(core->name)));
|
||||
|
||||
/*
|
||||
* Set clk's accuracy. The preferred method is to use
|
||||
@@ -4089,6 +4073,7 @@ out:
|
||||
clk_pm_runtime_put(core);
|
||||
unlock:
|
||||
if (ret) {
|
||||
hash_del(&core->hashtable_node);
|
||||
hlist_del_init(&core->child_node);
|
||||
core->hw->core = NULL;
|
||||
}
|
||||
@@ -4610,6 +4595,7 @@ void clk_unregister(struct clk *clk)
|
||||
|
||||
clk_core_evict_parent_cache(clk->core);
|
||||
|
||||
hash_del(&clk->core->hashtable_node);
|
||||
hlist_del_init(&clk->core->child_node);
|
||||
|
||||
if (clk->core->prepare_count)
|
||||
|
||||
@@ -25,6 +25,13 @@ config COMMON_CLK_STM32MP157
|
||||
help
|
||||
Support for stm32mp15x SoC family clocks.
|
||||
|
||||
config COMMON_CLK_STM32MP215
|
||||
bool "Clock driver for stm32mp21x clocks"
|
||||
depends on ARM || ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Support for stm32mp21x SoC family clocks
|
||||
|
||||
config COMMON_CLK_STM32MP257
|
||||
bool "Clock driver for stm32mp25x clocks"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
||||
@@ -1,3 +1,4 @@
|
||||
obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
|
||||
obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
|
||||
obj-$(CONFIG_COMMON_CLK_STM32MP215) += clk-stm32mp21.o clk-stm32-core.o reset-stm32.o
|
||||
obj-$(CONFIG_COMMON_CLK_STM32MP257) += clk-stm32mp25.o clk-stm32-core.o reset-stm32.o
|
||||
|
||||
1586
drivers/clk/stm32/clk-stm32mp21.c
Normal file
1586
drivers/clk/stm32/clk-stm32mp21.c
Normal file
File diff suppressed because it is too large
Load Diff
651
drivers/clk/stm32/stm32mp21_rcc.h
Normal file
651
drivers/clk/stm32/stm32mp21_rcc.h
Normal file
@@ -0,0 +1,651 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#ifndef STM32MP21_RCC_H
|
||||
#define STM32MP21_RCC_H
|
||||
|
||||
#define RCC_SECCFGR0 0x0
|
||||
#define RCC_SECCFGR1 0x4
|
||||
#define RCC_SECCFGR2 0x8
|
||||
#define RCC_SECCFGR3 0xC
|
||||
#define RCC_PRIVCFGR0 0x10
|
||||
#define RCC_PRIVCFGR1 0x14
|
||||
#define RCC_PRIVCFGR2 0x18
|
||||
#define RCC_PRIVCFGR3 0x1C
|
||||
#define RCC_RCFGLOCKR0 0x20
|
||||
#define RCC_RCFGLOCKR1 0x24
|
||||
#define RCC_RCFGLOCKR2 0x28
|
||||
#define RCC_RCFGLOCKR3 0x2C
|
||||
#define RCC_R0CIDCFGR 0x30
|
||||
#define RCC_R0SEMCR 0x34
|
||||
#define RCC_R1CIDCFGR 0x38
|
||||
#define RCC_R1SEMCR 0x3C
|
||||
#define RCC_R2CIDCFGR 0x40
|
||||
#define RCC_R2SEMCR 0x44
|
||||
#define RCC_R3CIDCFGR 0x48
|
||||
#define RCC_R3SEMCR 0x4C
|
||||
#define RCC_R4CIDCFGR 0x50
|
||||
#define RCC_R4SEMCR 0x54
|
||||
#define RCC_R5CIDCFGR 0x58
|
||||
#define RCC_R5SEMCR 0x5C
|
||||
#define RCC_R6CIDCFGR 0x60
|
||||
#define RCC_R6SEMCR 0x64
|
||||
#define RCC_R7CIDCFGR 0x68
|
||||
#define RCC_R7SEMCR 0x6C
|
||||
#define RCC_R8CIDCFGR 0x70
|
||||
#define RCC_R8SEMCR 0x74
|
||||
#define RCC_R9CIDCFGR 0x78
|
||||
#define RCC_R9SEMCR 0x7C
|
||||
#define RCC_R10CIDCFGR 0x80
|
||||
#define RCC_R10SEMCR 0x84
|
||||
#define RCC_R11CIDCFGR 0x88
|
||||
#define RCC_R11SEMCR 0x8C
|
||||
#define RCC_R12CIDCFGR 0x90
|
||||
#define RCC_R12SEMCR 0x94
|
||||
#define RCC_R13CIDCFGR 0x98
|
||||
#define RCC_R13SEMCR 0x9C
|
||||
#define RCC_R14CIDCFGR 0xA0
|
||||
#define RCC_R14SEMCR 0xA4
|
||||
#define RCC_R15CIDCFGR 0xA8
|
||||
#define RCC_R15SEMCR 0xAC
|
||||
#define RCC_R16CIDCFGR 0xB0
|
||||
#define RCC_R16SEMCR 0xB4
|
||||
#define RCC_R17CIDCFGR 0xB8
|
||||
#define RCC_R17SEMCR 0xBC
|
||||
#define RCC_R18CIDCFGR 0xC0
|
||||
#define RCC_R18SEMCR 0xC4
|
||||
#define RCC_R19CIDCFGR 0xC8
|
||||
#define RCC_R19SEMCR 0xCC
|
||||
#define RCC_R20CIDCFGR 0xD0
|
||||
#define RCC_R20SEMCR 0xD4
|
||||
#define RCC_R21CIDCFGR 0xD8
|
||||
#define RCC_R21SEMCR 0xDC
|
||||
#define RCC_R22CIDCFGR 0xE0
|
||||
#define RCC_R22SEMCR 0xE4
|
||||
#define RCC_R23CIDCFGR 0xE8
|
||||
#define RCC_R23SEMCR 0xEC
|
||||
#define RCC_R24CIDCFGR 0xF0
|
||||
#define RCC_R24SEMCR 0xF4
|
||||
#define RCC_R25CIDCFGR 0xF8
|
||||
#define RCC_R25SEMCR 0xFC
|
||||
#define RCC_R26CIDCFGR 0x100
|
||||
#define RCC_R26SEMCR 0x104
|
||||
#define RCC_R27CIDCFGR 0x108
|
||||
#define RCC_R27SEMCR 0x10C
|
||||
#define RCC_R28CIDCFGR 0x110
|
||||
#define RCC_R28SEMCR 0x114
|
||||
#define RCC_R29CIDCFGR 0x118
|
||||
#define RCC_R29SEMCR 0x11C
|
||||
#define RCC_R30CIDCFGR 0x120
|
||||
#define RCC_R30SEMCR 0x124
|
||||
#define RCC_R31CIDCFGR 0x128
|
||||
#define RCC_R31SEMCR 0x12C
|
||||
#define RCC_R32CIDCFGR 0x130
|
||||
#define RCC_R32SEMCR 0x134
|
||||
#define RCC_R33CIDCFGR 0x138
|
||||
#define RCC_R33SEMCR 0x13C
|
||||
#define RCC_R34CIDCFGR 0x140
|
||||
#define RCC_R34SEMCR 0x144
|
||||
#define RCC_R35CIDCFGR 0x148
|
||||
#define RCC_R35SEMCR 0x14C
|
||||
#define RCC_R36CIDCFGR 0x150
|
||||
#define RCC_R36SEMCR 0x154
|
||||
#define RCC_R37CIDCFGR 0x158
|
||||
#define RCC_R37SEMCR 0x15C
|
||||
#define RCC_R38CIDCFGR 0x160
|
||||
#define RCC_R38SEMCR 0x164
|
||||
#define RCC_R39CIDCFGR 0x168
|
||||
#define RCC_R39SEMCR 0x16C
|
||||
#define RCC_R40CIDCFGR 0x170
|
||||
#define RCC_R40SEMCR 0x174
|
||||
#define RCC_R41CIDCFGR 0x178
|
||||
#define RCC_R41SEMCR 0x17C
|
||||
#define RCC_R42CIDCFGR 0x180
|
||||
#define RCC_R42SEMCR 0x184
|
||||
#define RCC_R43CIDCFGR 0x188
|
||||
#define RCC_R43SEMCR 0x18C
|
||||
#define RCC_R44CIDCFGR 0x190
|
||||
#define RCC_R44SEMCR 0x194
|
||||
#define RCC_R45CIDCFGR 0x198
|
||||
#define RCC_R45SEMCR 0x19C
|
||||
#define RCC_R46CIDCFGR 0x1A0
|
||||
#define RCC_R46SEMCR 0x1A4
|
||||
#define RCC_R47CIDCFGR 0x1A8
|
||||
#define RCC_R47SEMCR 0x1AC
|
||||
#define RCC_R48CIDCFGR 0x1B0
|
||||
#define RCC_R48SEMCR 0x1B4
|
||||
#define RCC_R49CIDCFGR 0x1B8
|
||||
#define RCC_R49SEMCR 0x1BC
|
||||
#define RCC_R50CIDCFGR 0x1C0
|
||||
#define RCC_R50SEMCR 0x1C4
|
||||
#define RCC_R51CIDCFGR 0x1C8
|
||||
#define RCC_R51SEMCR 0x1CC
|
||||
#define RCC_R52CIDCFGR 0x1D0
|
||||
#define RCC_R52SEMCR 0x1D4
|
||||
#define RCC_R53CIDCFGR 0x1D8
|
||||
#define RCC_R53SEMCR 0x1DC
|
||||
#define RCC_R54CIDCFGR 0x1E0
|
||||
#define RCC_R54SEMCR 0x1E4
|
||||
#define RCC_R55CIDCFGR 0x1E8
|
||||
#define RCC_R55SEMCR 0x1EC
|
||||
#define RCC_R56CIDCFGR 0x1F0
|
||||
#define RCC_R56SEMCR 0x1F4
|
||||
#define RCC_R57CIDCFGR 0x1F8
|
||||
#define RCC_R57SEMCR 0x1FC
|
||||
#define RCC_R58CIDCFGR 0x200
|
||||
#define RCC_R58SEMCR 0x204
|
||||
#define RCC_R59CIDCFGR 0x208
|
||||
#define RCC_R59SEMCR 0x20C
|
||||
#define RCC_R60CIDCFGR 0x210
|
||||
#define RCC_R60SEMCR 0x214
|
||||
#define RCC_R61CIDCFGR 0x218
|
||||
#define RCC_R61SEMCR 0x21C
|
||||
#define RCC_R62CIDCFGR 0x220
|
||||
#define RCC_R62SEMCR 0x224
|
||||
#define RCC_R63CIDCFGR 0x228
|
||||
#define RCC_R63SEMCR 0x22C
|
||||
#define RCC_R64CIDCFGR 0x230
|
||||
#define RCC_R64SEMCR 0x234
|
||||
#define RCC_R65CIDCFGR 0x238
|
||||
#define RCC_R65SEMCR 0x23C
|
||||
#define RCC_R66CIDCFGR 0x240
|
||||
#define RCC_R66SEMCR 0x244
|
||||
#define RCC_R67CIDCFGR 0x248
|
||||
#define RCC_R67SEMCR 0x24C
|
||||
#define RCC_R68CIDCFGR 0x250
|
||||
#define RCC_R68SEMCR 0x254
|
||||
#define RCC_R69CIDCFGR 0x258
|
||||
#define RCC_R69SEMCR 0x25C
|
||||
#define RCC_R70CIDCFGR 0x260
|
||||
#define RCC_R70SEMCR 0x264
|
||||
#define RCC_R71CIDCFGR 0x268
|
||||
#define RCC_R71SEMCR 0x26C
|
||||
#define RCC_R73CIDCFGR 0x278
|
||||
#define RCC_R73SEMCR 0x27C
|
||||
#define RCC_R74CIDCFGR 0x280
|
||||
#define RCC_R74SEMCR 0x284
|
||||
#define RCC_R75CIDCFGR 0x288
|
||||
#define RCC_R75SEMCR 0x28C
|
||||
#define RCC_R76CIDCFGR 0x290
|
||||
#define RCC_R76SEMCR 0x294
|
||||
#define RCC_R77CIDCFGR 0x298
|
||||
#define RCC_R77SEMCR 0x29C
|
||||
#define RCC_R78CIDCFGR 0x2A0
|
||||
#define RCC_R78SEMCR 0x2A4
|
||||
#define RCC_R79CIDCFGR 0x2A8
|
||||
#define RCC_R79SEMCR 0x2AC
|
||||
#define RCC_R83CIDCFGR 0x2C8
|
||||
#define RCC_R83SEMCR 0x2CC
|
||||
#define RCC_R84CIDCFGR 0x2D0
|
||||
#define RCC_R84SEMCR 0x2D4
|
||||
#define RCC_R85CIDCFGR 0x2D8
|
||||
#define RCC_R85SEMCR 0x2DC
|
||||
#define RCC_R86CIDCFGR 0x2E0
|
||||
#define RCC_R86SEMCR 0x2E4
|
||||
#define RCC_R87CIDCFGR 0x2E8
|
||||
#define RCC_R87SEMCR 0x2EC
|
||||
#define RCC_R88CIDCFGR 0x2F0
|
||||
#define RCC_R88SEMCR 0x2F4
|
||||
#define RCC_R90CIDCFGR 0x300
|
||||
#define RCC_R90SEMCR 0x304
|
||||
#define RCC_R91CIDCFGR 0x308
|
||||
#define RCC_R91SEMCR 0x30C
|
||||
#define RCC_R92CIDCFGR 0x310
|
||||
#define RCC_R92SEMCR 0x314
|
||||
#define RCC_R93CIDCFGR 0x318
|
||||
#define RCC_R93SEMCR 0x31C
|
||||
#define RCC_R94CIDCFGR 0x320
|
||||
#define RCC_R94SEMCR 0x324
|
||||
#define RCC_R95CIDCFGR 0x328
|
||||
#define RCC_R95SEMCR 0x32C
|
||||
#define RCC_R96CIDCFGR 0x330
|
||||
#define RCC_R96SEMCR 0x334
|
||||
#define RCC_R97CIDCFGR 0x338
|
||||
#define RCC_R97SEMCR 0x33C
|
||||
#define RCC_R98CIDCFGR 0x340
|
||||
#define RCC_R98SEMCR 0x344
|
||||
#define RCC_R101CIDCFGR 0x358
|
||||
#define RCC_R101SEMCR 0x35C
|
||||
#define RCC_R102CIDCFGR 0x360
|
||||
#define RCC_R102SEMCR 0x364
|
||||
#define RCC_R103CIDCFGR 0x368
|
||||
#define RCC_R103SEMCR 0x36C
|
||||
#define RCC_R104CIDCFGR 0x370
|
||||
#define RCC_R104SEMCR 0x374
|
||||
#define RCC_R105CIDCFGR 0x378
|
||||
#define RCC_R105SEMCR 0x37C
|
||||
#define RCC_R106CIDCFGR 0x380
|
||||
#define RCC_R106SEMCR 0x384
|
||||
#define RCC_R108CIDCFGR 0x390
|
||||
#define RCC_R108SEMCR 0x394
|
||||
#define RCC_R109CIDCFGR 0x398
|
||||
#define RCC_R109SEMCR 0x39C
|
||||
#define RCC_R110CIDCFGR 0x3A0
|
||||
#define RCC_R110SEMCR 0x3A4
|
||||
#define RCC_R111CIDCFGR 0x3A8
|
||||
#define RCC_R111SEMCR 0x3AC
|
||||
#define RCC_R112CIDCFGR 0x3B0
|
||||
#define RCC_R112SEMCR 0x3B4
|
||||
#define RCC_R113CIDCFGR 0x3B8
|
||||
#define RCC_R113SEMCR 0x3BC
|
||||
#define RCC_GRSTCSETR 0x400
|
||||
#define RCC_C1RSTCSETR 0x404
|
||||
#define RCC_C2RSTCSETR 0x40C
|
||||
#define RCC_HWRSTSCLRR 0x410
|
||||
#define RCC_C1HWRSTSCLRR 0x414
|
||||
#define RCC_C2HWRSTSCLRR 0x418
|
||||
#define RCC_C1BOOTRSTSSETR 0x41C
|
||||
#define RCC_C1BOOTRSTSCLRR 0x420
|
||||
#define RCC_C2BOOTRSTSSETR 0x424
|
||||
#define RCC_C2BOOTRSTSCLRR 0x428
|
||||
#define RCC_C1SREQSETR 0x42C
|
||||
#define RCC_C1SREQCLRR 0x430
|
||||
#define RCC_CPUBOOTCR 0x434
|
||||
#define RCC_STBYBOOTCR 0x438
|
||||
#define RCC_LEGBOOTCR 0x43C
|
||||
#define RCC_BDCR 0x440
|
||||
#define RCC_RDCR 0x44C
|
||||
#define RCC_C1MSRDCR 0x450
|
||||
#define RCC_PWRLPDLYCR 0x454
|
||||
#define RCC_C1CIESETR 0x458
|
||||
#define RCC_C1CIFCLRR 0x45C
|
||||
#define RCC_C2CIESETR 0x460
|
||||
#define RCC_C2CIFCLRR 0x464
|
||||
#define RCC_IWDGC1FZSETR 0x468
|
||||
#define RCC_IWDGC1FZCLRR 0x46C
|
||||
#define RCC_IWDGC1CFGSETR 0x470
|
||||
#define RCC_IWDGC1CFGCLRR 0x474
|
||||
#define RCC_IWDGC2FZSETR 0x478
|
||||
#define RCC_IWDGC2FZCLRR 0x47C
|
||||
#define RCC_IWDGC2CFGSETR 0x480
|
||||
#define RCC_IWDGC2CFGCLRR 0x484
|
||||
#define RCC_MCO1CFGR 0x488
|
||||
#define RCC_MCO2CFGR 0x48C
|
||||
#define RCC_OCENSETR 0x490
|
||||
#define RCC_OCENCLRR 0x494
|
||||
#define RCC_OCRDYR 0x498
|
||||
#define RCC_HSICFGR 0x49C
|
||||
#define RCC_MSICFGR 0x4A0
|
||||
#define RCC_LSICR 0x4A4
|
||||
#define RCC_RTCDIVR 0x4A8
|
||||
#define RCC_APB1DIVR 0x4AC
|
||||
#define RCC_APB2DIVR 0x4B0
|
||||
#define RCC_APB3DIVR 0x4B4
|
||||
#define RCC_APB4DIVR 0x4B8
|
||||
#define RCC_APB5DIVR 0x4BC
|
||||
#define RCC_APBDBGDIVR 0x4C0
|
||||
#define RCC_TIMG1PRER 0x4C8
|
||||
#define RCC_TIMG2PRER 0x4CC
|
||||
#define RCC_LSMCUDIVR 0x4D0
|
||||
#define RCC_DDRCPCFGR 0x4D4
|
||||
#define RCC_DDRCAPBCFGR 0x4D8
|
||||
#define RCC_DDRPHYCAPBCFGR 0x4DC
|
||||
#define RCC_DDRPHYCCFGR 0x4E0
|
||||
#define RCC_DDRCFGR 0x4E4
|
||||
#define RCC_DDRITFCFGR 0x4E8
|
||||
#define RCC_SYSRAMCFGR 0x4F0
|
||||
#define RCC_SRAM1CFGR 0x4F8
|
||||
#define RCC_RETRAMCFGR 0x500
|
||||
#define RCC_BKPSRAMCFGR 0x504
|
||||
#define RCC_OSPI1CFGR 0x514
|
||||
#define RCC_FMCCFGR 0x51C
|
||||
#define RCC_DBGCFGR 0x520
|
||||
#define RCC_STMCFGR 0x524
|
||||
#define RCC_ETRCFGR 0x528
|
||||
#define RCC_GPIOACFGR 0x52C
|
||||
#define RCC_GPIOBCFGR 0x530
|
||||
#define RCC_GPIOCCFGR 0x534
|
||||
#define RCC_GPIODCFGR 0x538
|
||||
#define RCC_GPIOECFGR 0x53C
|
||||
#define RCC_GPIOFCFGR 0x540
|
||||
#define RCC_GPIOGCFGR 0x544
|
||||
#define RCC_GPIOHCFGR 0x548
|
||||
#define RCC_GPIOICFGR 0x54C
|
||||
#define RCC_GPIOZCFGR 0x558
|
||||
#define RCC_HPDMA1CFGR 0x55C
|
||||
#define RCC_HPDMA2CFGR 0x560
|
||||
#define RCC_HPDMA3CFGR 0x564
|
||||
#define RCC_IPCC1CFGR 0x570
|
||||
#define RCC_RTCCFGR 0x578
|
||||
#define RCC_SYSCPU1CFGR 0x580
|
||||
#define RCC_BSECCFGR 0x584
|
||||
#define RCC_PLL2CFGR1 0x590
|
||||
#define RCC_PLL2CFGR2 0x594
|
||||
#define RCC_PLL2CFGR3 0x598
|
||||
#define RCC_PLL2CFGR4 0x59C
|
||||
#define RCC_PLL2CFGR5 0x5A0
|
||||
#define RCC_PLL2CFGR6 0x5A8
|
||||
#define RCC_PLL2CFGR7 0x5AC
|
||||
#define RCC_HSIFMONCR 0x5E0
|
||||
#define RCC_HSIFVALR 0x5E4
|
||||
#define RCC_MSIFMONCR 0x5E8
|
||||
#define RCC_MSIFVALR 0x5EC
|
||||
#define RCC_TIM1CFGR 0x700
|
||||
#define RCC_TIM2CFGR 0x704
|
||||
#define RCC_TIM3CFGR 0x708
|
||||
#define RCC_TIM4CFGR 0x70C
|
||||
#define RCC_TIM5CFGR 0x710
|
||||
#define RCC_TIM6CFGR 0x714
|
||||
#define RCC_TIM7CFGR 0x718
|
||||
#define RCC_TIM8CFGR 0x71C
|
||||
#define RCC_TIM10CFGR 0x720
|
||||
#define RCC_TIM11CFGR 0x724
|
||||
#define RCC_TIM12CFGR 0x728
|
||||
#define RCC_TIM13CFGR 0x72C
|
||||
#define RCC_TIM14CFGR 0x730
|
||||
#define RCC_TIM15CFGR 0x734
|
||||
#define RCC_TIM16CFGR 0x738
|
||||
#define RCC_TIM17CFGR 0x73C
|
||||
#define RCC_LPTIM1CFGR 0x744
|
||||
#define RCC_LPTIM2CFGR 0x748
|
||||
#define RCC_LPTIM3CFGR 0x74C
|
||||
#define RCC_LPTIM4CFGR 0x750
|
||||
#define RCC_LPTIM5CFGR 0x754
|
||||
#define RCC_SPI1CFGR 0x758
|
||||
#define RCC_SPI2CFGR 0x75C
|
||||
#define RCC_SPI3CFGR 0x760
|
||||
#define RCC_SPI4CFGR 0x764
|
||||
#define RCC_SPI5CFGR 0x768
|
||||
#define RCC_SPI6CFGR 0x76C
|
||||
#define RCC_SPDIFRXCFGR 0x778
|
||||
#define RCC_USART1CFGR 0x77C
|
||||
#define RCC_USART2CFGR 0x780
|
||||
#define RCC_USART3CFGR 0x784
|
||||
#define RCC_UART4CFGR 0x788
|
||||
#define RCC_UART5CFGR 0x78C
|
||||
#define RCC_USART6CFGR 0x790
|
||||
#define RCC_UART7CFGR 0x794
|
||||
#define RCC_LPUART1CFGR 0x7A0
|
||||
#define RCC_I2C1CFGR 0x7A4
|
||||
#define RCC_I2C2CFGR 0x7A8
|
||||
#define RCC_I2C3CFGR 0x7AC
|
||||
#define RCC_SAI1CFGR 0x7C4
|
||||
#define RCC_SAI2CFGR 0x7C8
|
||||
#define RCC_SAI3CFGR 0x7CC
|
||||
#define RCC_SAI4CFGR 0x7D0
|
||||
#define RCC_MDF1CFGR 0x7D8
|
||||
#define RCC_FDCANCFGR 0x7E0
|
||||
#define RCC_HDPCFGR 0x7E4
|
||||
#define RCC_ADC1CFGR 0x7E8
|
||||
#define RCC_ADC2CFGR 0x7EC
|
||||
#define RCC_ETH1CFGR 0x7F0
|
||||
#define RCC_ETH2CFGR 0x7F4
|
||||
#define RCC_USBHCFGR 0x7FC
|
||||
#define RCC_USB2PHY1CFGR 0x800
|
||||
#define RCC_OTGCFGR 0x808
|
||||
#define RCC_USB2PHY2CFGR 0x80C
|
||||
#define RCC_STGENCFGR 0x824
|
||||
#define RCC_SDMMC1CFGR 0x830
|
||||
#define RCC_SDMMC2CFGR 0x834
|
||||
#define RCC_SDMMC3CFGR 0x838
|
||||
#define RCC_LTDCCFGR 0x840
|
||||
#define RCC_CSICFGR 0x858
|
||||
#define RCC_DCMIPPCFGR 0x85C
|
||||
#define RCC_DCMIPSSICFGR 0x860
|
||||
#define RCC_RNG1CFGR 0x870
|
||||
#define RCC_RNG2CFGR 0x874
|
||||
#define RCC_PKACFGR 0x878
|
||||
#define RCC_SAESCFGR 0x87C
|
||||
#define RCC_HASH1CFGR 0x880
|
||||
#define RCC_HASH2CFGR 0x884
|
||||
#define RCC_CRYP1CFGR 0x888
|
||||
#define RCC_CRYP2CFGR 0x88C
|
||||
#define RCC_IWDG1CFGR 0x894
|
||||
#define RCC_IWDG2CFGR 0x898
|
||||
#define RCC_IWDG3CFGR 0x89C
|
||||
#define RCC_IWDG4CFGR 0x8A0
|
||||
#define RCC_WWDG1CFGR 0x8A4
|
||||
#define RCC_VREFCFGR 0x8AC
|
||||
#define RCC_DTSCFGR 0x8B0
|
||||
#define RCC_CRCCFGR 0x8B4
|
||||
#define RCC_SERCCFGR 0x8B8
|
||||
#define RCC_DDRPERFMCFGR 0x8C0
|
||||
#define RCC_I3C1CFGR 0x8C8
|
||||
#define RCC_I3C2CFGR 0x8CC
|
||||
#define RCC_I3C3CFGR 0x8D0
|
||||
#define RCC_MUXSELCFGR 0x1000
|
||||
#define RCC_XBAR0CFGR 0x1018
|
||||
#define RCC_XBAR1CFGR 0x101C
|
||||
#define RCC_XBAR2CFGR 0x1020
|
||||
#define RCC_XBAR3CFGR 0x1024
|
||||
#define RCC_XBAR4CFGR 0x1028
|
||||
#define RCC_XBAR5CFGR 0x102C
|
||||
#define RCC_XBAR6CFGR 0x1030
|
||||
#define RCC_XBAR7CFGR 0x1034
|
||||
#define RCC_XBAR8CFGR 0x1038
|
||||
#define RCC_XBAR9CFGR 0x103C
|
||||
#define RCC_XBAR10CFGR 0x1040
|
||||
#define RCC_XBAR11CFGR 0x1044
|
||||
#define RCC_XBAR12CFGR 0x1048
|
||||
#define RCC_XBAR13CFGR 0x104C
|
||||
#define RCC_XBAR14CFGR 0x1050
|
||||
#define RCC_XBAR15CFGR 0x1054
|
||||
#define RCC_XBAR16CFGR 0x1058
|
||||
#define RCC_XBAR17CFGR 0x105C
|
||||
#define RCC_XBAR18CFGR 0x1060
|
||||
#define RCC_XBAR19CFGR 0x1064
|
||||
#define RCC_XBAR20CFGR 0x1068
|
||||
#define RCC_XBAR21CFGR 0x106C
|
||||
#define RCC_XBAR22CFGR 0x1070
|
||||
#define RCC_XBAR23CFGR 0x1074
|
||||
#define RCC_XBAR24CFGR 0x1078
|
||||
#define RCC_XBAR25CFGR 0x107C
|
||||
#define RCC_XBAR26CFGR 0x1080
|
||||
#define RCC_XBAR27CFGR 0x1084
|
||||
#define RCC_XBAR28CFGR 0x1088
|
||||
#define RCC_XBAR29CFGR 0x108C
|
||||
#define RCC_XBAR30CFGR 0x1090
|
||||
#define RCC_XBAR31CFGR 0x1094
|
||||
#define RCC_XBAR32CFGR 0x1098
|
||||
#define RCC_XBAR33CFGR 0x109C
|
||||
#define RCC_XBAR34CFGR 0x10A0
|
||||
#define RCC_XBAR35CFGR 0x10A4
|
||||
#define RCC_XBAR36CFGR 0x10A8
|
||||
#define RCC_XBAR37CFGR 0x10AC
|
||||
#define RCC_XBAR38CFGR 0x10B0
|
||||
#define RCC_XBAR39CFGR 0x10B4
|
||||
#define RCC_XBAR40CFGR 0x10B8
|
||||
#define RCC_XBAR41CFGR 0x10BC
|
||||
#define RCC_XBAR42CFGR 0x10C0
|
||||
#define RCC_XBAR43CFGR 0x10C4
|
||||
#define RCC_XBAR44CFGR 0x10C8
|
||||
#define RCC_XBAR45CFGR 0x10CC
|
||||
#define RCC_XBAR46CFGR 0x10D0
|
||||
#define RCC_XBAR47CFGR 0x10D4
|
||||
#define RCC_XBAR48CFGR 0x10D8
|
||||
#define RCC_XBAR49CFGR 0x10DC
|
||||
#define RCC_XBAR50CFGR 0x10E0
|
||||
#define RCC_XBAR51CFGR 0x10E4
|
||||
#define RCC_XBAR52CFGR 0x10E8
|
||||
#define RCC_XBAR53CFGR 0x10EC
|
||||
#define RCC_XBAR54CFGR 0x10F0
|
||||
#define RCC_XBAR55CFGR 0x10F4
|
||||
#define RCC_XBAR56CFGR 0x10F8
|
||||
#define RCC_XBAR57CFGR 0x10FC
|
||||
#define RCC_XBAR58CFGR 0x1100
|
||||
#define RCC_XBAR59CFGR 0x1104
|
||||
#define RCC_XBAR60CFGR 0x1108
|
||||
#define RCC_XBAR61CFGR 0x110C
|
||||
#define RCC_XBAR62CFGR 0x1110
|
||||
#define RCC_XBAR63CFGR 0x1114
|
||||
#define RCC_PREDIV0CFGR 0x1118
|
||||
#define RCC_PREDIV1CFGR 0x111C
|
||||
#define RCC_PREDIV2CFGR 0x1120
|
||||
#define RCC_PREDIV3CFGR 0x1124
|
||||
#define RCC_PREDIV4CFGR 0x1128
|
||||
#define RCC_PREDIV5CFGR 0x112C
|
||||
#define RCC_PREDIV6CFGR 0x1130
|
||||
#define RCC_PREDIV7CFGR 0x1134
|
||||
#define RCC_PREDIV8CFGR 0x1138
|
||||
#define RCC_PREDIV9CFGR 0x113C
|
||||
#define RCC_PREDIV10CFGR 0x1140
|
||||
#define RCC_PREDIV11CFGR 0x1144
|
||||
#define RCC_PREDIV12CFGR 0x1148
|
||||
#define RCC_PREDIV13CFGR 0x114C
|
||||
#define RCC_PREDIV14CFGR 0x1150
|
||||
#define RCC_PREDIV15CFGR 0x1154
|
||||
#define RCC_PREDIV16CFGR 0x1158
|
||||
#define RCC_PREDIV17CFGR 0x115C
|
||||
#define RCC_PREDIV18CFGR 0x1160
|
||||
#define RCC_PREDIV19CFGR 0x1164
|
||||
#define RCC_PREDIV20CFGR 0x1168
|
||||
#define RCC_PREDIV21CFGR 0x116C
|
||||
#define RCC_PREDIV22CFGR 0x1170
|
||||
#define RCC_PREDIV23CFGR 0x1174
|
||||
#define RCC_PREDIV24CFGR 0x1178
|
||||
#define RCC_PREDIV25CFGR 0x117C
|
||||
#define RCC_PREDIV26CFGR 0x1180
|
||||
#define RCC_PREDIV27CFGR 0x1184
|
||||
#define RCC_PREDIV28CFGR 0x1188
|
||||
#define RCC_PREDIV29CFGR 0x118C
|
||||
#define RCC_PREDIV30CFGR 0x1190
|
||||
#define RCC_PREDIV31CFGR 0x1194
|
||||
#define RCC_PREDIV32CFGR 0x1198
|
||||
#define RCC_PREDIV33CFGR 0x119C
|
||||
#define RCC_PREDIV34CFGR 0x11A0
|
||||
#define RCC_PREDIV35CFGR 0x11A4
|
||||
#define RCC_PREDIV36CFGR 0x11A8
|
||||
#define RCC_PREDIV37CFGR 0x11AC
|
||||
#define RCC_PREDIV38CFGR 0x11B0
|
||||
#define RCC_PREDIV39CFGR 0x11B4
|
||||
#define RCC_PREDIV40CFGR 0x11B8
|
||||
#define RCC_PREDIV41CFGR 0x11BC
|
||||
#define RCC_PREDIV42CFGR 0x11C0
|
||||
#define RCC_PREDIV43CFGR 0x11C4
|
||||
#define RCC_PREDIV44CFGR 0x11C8
|
||||
#define RCC_PREDIV45CFGR 0x11CC
|
||||
#define RCC_PREDIV46CFGR 0x11D0
|
||||
#define RCC_PREDIV47CFGR 0x11D4
|
||||
#define RCC_PREDIV48CFGR 0x11D8
|
||||
#define RCC_PREDIV49CFGR 0x11DC
|
||||
#define RCC_PREDIV50CFGR 0x11E0
|
||||
#define RCC_PREDIV51CFGR 0x11E4
|
||||
#define RCC_PREDIV52CFGR 0x11E8
|
||||
#define RCC_PREDIV53CFGR 0x11EC
|
||||
#define RCC_PREDIV54CFGR 0x11F0
|
||||
#define RCC_PREDIV55CFGR 0x11F4
|
||||
#define RCC_PREDIV56CFGR 0x11F8
|
||||
#define RCC_PREDIV57CFGR 0x11FC
|
||||
#define RCC_PREDIV58CFGR 0x1200
|
||||
#define RCC_PREDIV59CFGR 0x1204
|
||||
#define RCC_PREDIV60CFGR 0x1208
|
||||
#define RCC_PREDIV61CFGR 0x120C
|
||||
#define RCC_PREDIV62CFGR 0x1210
|
||||
#define RCC_PREDIV63CFGR 0x1214
|
||||
#define RCC_PREDIVSR1 0x1218
|
||||
#define RCC_PREDIVSR2 0x121C
|
||||
#define RCC_FINDIV0CFGR 0x1224
|
||||
#define RCC_FINDIV1CFGR 0x1228
|
||||
#define RCC_FINDIV2CFGR 0x122C
|
||||
#define RCC_FINDIV3CFGR 0x1230
|
||||
#define RCC_FINDIV4CFGR 0x1234
|
||||
#define RCC_FINDIV5CFGR 0x1238
|
||||
#define RCC_FINDIV6CFGR 0x123C
|
||||
#define RCC_FINDIV7CFGR 0x1240
|
||||
#define RCC_FINDIV8CFGR 0x1244
|
||||
#define RCC_FINDIV9CFGR 0x1248
|
||||
#define RCC_FINDIV10CFGR 0x124C
|
||||
#define RCC_FINDIV11CFGR 0x1250
|
||||
#define RCC_FINDIV12CFGR 0x1254
|
||||
#define RCC_FINDIV13CFGR 0x1258
|
||||
#define RCC_FINDIV14CFGR 0x125C
|
||||
#define RCC_FINDIV15CFGR 0x1260
|
||||
#define RCC_FINDIV16CFGR 0x1264
|
||||
#define RCC_FINDIV17CFGR 0x1268
|
||||
#define RCC_FINDIV18CFGR 0x126C
|
||||
#define RCC_FINDIV19CFGR 0x1270
|
||||
#define RCC_FINDIV20CFGR 0x1274
|
||||
#define RCC_FINDIV21CFGR 0x1278
|
||||
#define RCC_FINDIV22CFGR 0x127C
|
||||
#define RCC_FINDIV23CFGR 0x1280
|
||||
#define RCC_FINDIV24CFGR 0x1284
|
||||
#define RCC_FINDIV25CFGR 0x1288
|
||||
#define RCC_FINDIV26CFGR 0x128C
|
||||
#define RCC_FINDIV27CFGR 0x1290
|
||||
#define RCC_FINDIV28CFGR 0x1294
|
||||
#define RCC_FINDIV29CFGR 0x1298
|
||||
#define RCC_FINDIV30CFGR 0x129C
|
||||
#define RCC_FINDIV31CFGR 0x12A0
|
||||
#define RCC_FINDIV32CFGR 0x12A4
|
||||
#define RCC_FINDIV33CFGR 0x12A8
|
||||
#define RCC_FINDIV34CFGR 0x12AC
|
||||
#define RCC_FINDIV35CFGR 0x12B0
|
||||
#define RCC_FINDIV36CFGR 0x12B4
|
||||
#define RCC_FINDIV37CFGR 0x12B8
|
||||
#define RCC_FINDIV38CFGR 0x12BC
|
||||
#define RCC_FINDIV39CFGR 0x12C0
|
||||
#define RCC_FINDIV40CFGR 0x12C4
|
||||
#define RCC_FINDIV41CFGR 0x12C8
|
||||
#define RCC_FINDIV42CFGR 0x12CC
|
||||
#define RCC_FINDIV43CFGR 0x12D0
|
||||
#define RCC_FINDIV44CFGR 0x12D4
|
||||
#define RCC_FINDIV45CFGR 0x12D8
|
||||
#define RCC_FINDIV46CFGR 0x12DC
|
||||
#define RCC_FINDIV47CFGR 0x12E0
|
||||
#define RCC_FINDIV48CFGR 0x12E4
|
||||
#define RCC_FINDIV49CFGR 0x12E8
|
||||
#define RCC_FINDIV50CFGR 0x12EC
|
||||
#define RCC_FINDIV51CFGR 0x12F0
|
||||
#define RCC_FINDIV52CFGR 0x12F4
|
||||
#define RCC_FINDIV53CFGR 0x12F8
|
||||
#define RCC_FINDIV54CFGR 0x12FC
|
||||
#define RCC_FINDIV55CFGR 0x1300
|
||||
#define RCC_FINDIV56CFGR 0x1304
|
||||
#define RCC_FINDIV57CFGR 0x1308
|
||||
#define RCC_FINDIV58CFGR 0x130C
|
||||
#define RCC_FINDIV59CFGR 0x1310
|
||||
#define RCC_FINDIV60CFGR 0x1314
|
||||
#define RCC_FINDIV61CFGR 0x1318
|
||||
#define RCC_FINDIV62CFGR 0x131C
|
||||
#define RCC_FINDIV63CFGR 0x1320
|
||||
#define RCC_FINDIVSR1 0x1324
|
||||
#define RCC_FINDIVSR2 0x1328
|
||||
#define RCC_FCALCOBS0CFGR 0x1340
|
||||
#define RCC_FCALCOBS1CFGR 0x1344
|
||||
#define RCC_FCALCREFCFGR 0x1348
|
||||
#define RCC_FCALCCR1 0x134C
|
||||
#define RCC_FCALCCR2 0x1354
|
||||
#define RCC_FCALCSR 0x1358
|
||||
#define RCC_PLL4CFGR1 0x1360
|
||||
#define RCC_PLL4CFGR2 0x1364
|
||||
#define RCC_PLL4CFGR3 0x1368
|
||||
#define RCC_PLL4CFGR4 0x136C
|
||||
#define RCC_PLL4CFGR5 0x1370
|
||||
#define RCC_PLL4CFGR6 0x1378
|
||||
#define RCC_PLL4CFGR7 0x137C
|
||||
#define RCC_PLL5CFGR1 0x1388
|
||||
#define RCC_PLL5CFGR2 0x138C
|
||||
#define RCC_PLL5CFGR3 0x1390
|
||||
#define RCC_PLL5CFGR4 0x1394
|
||||
#define RCC_PLL5CFGR5 0x1398
|
||||
#define RCC_PLL5CFGR6 0x13A0
|
||||
#define RCC_PLL5CFGR7 0x13A4
|
||||
#define RCC_PLL6CFGR1 0x13B0
|
||||
#define RCC_PLL6CFGR2 0x13B4
|
||||
#define RCC_PLL6CFGR3 0x13B8
|
||||
#define RCC_PLL6CFGR4 0x13BC
|
||||
#define RCC_PLL6CFGR5 0x13C0
|
||||
#define RCC_PLL6CFGR6 0x13C8
|
||||
#define RCC_PLL6CFGR7 0x13CC
|
||||
#define RCC_PLL7CFGR1 0x13D8
|
||||
#define RCC_PLL7CFGR2 0x13DC
|
||||
#define RCC_PLL7CFGR3 0x13E0
|
||||
#define RCC_PLL7CFGR4 0x13E4
|
||||
#define RCC_PLL7CFGR5 0x13E8
|
||||
#define RCC_PLL7CFGR6 0x13F0
|
||||
#define RCC_PLL7CFGR7 0x13F4
|
||||
#define RCC_PLL8CFGR1 0x1400
|
||||
#define RCC_PLL8CFGR2 0x1404
|
||||
#define RCC_PLL8CFGR3 0x1408
|
||||
#define RCC_PLL8CFGR4 0x140C
|
||||
#define RCC_PLL8CFGR5 0x1410
|
||||
#define RCC_PLL8CFGR6 0x1418
|
||||
#define RCC_PLL8CFGR7 0x141C
|
||||
#define RCC_VERR 0xFFF4
|
||||
#define RCC_IDR 0xFFF8
|
||||
#define RCC_SIDR 0xFFFC
|
||||
|
||||
#endif /* STM32MP21_RCC_H */
|
||||
426
include/dt-bindings/clock/st,stm32mp21-rcc.h
Normal file
426
include/dt-bindings/clock/st,stm32mp21-rcc.h
Normal file
@@ -0,0 +1,426 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
|
||||
#define _DT_BINDINGS_STM32MP21_CLKS_H_
|
||||
|
||||
/* INTERNAL/EXTERNAL OSCILLATORS */
|
||||
#define HSI_CK 0
|
||||
#define HSE_CK 1
|
||||
#define MSI_CK 2
|
||||
#define LSI_CK 3
|
||||
#define LSE_CK 4
|
||||
#define I2S_CK 5
|
||||
#define RTC_CK 6
|
||||
#define SPDIF_CK_SYMB 7
|
||||
|
||||
/* PLL CLOCKS */
|
||||
#define PLL1_CK 8
|
||||
#define PLL2_CK 9
|
||||
#define PLL4_CK 10
|
||||
#define PLL5_CK 11
|
||||
#define PLL6_CK 12
|
||||
#define PLL7_CK 13
|
||||
#define PLL8_CK 14
|
||||
|
||||
#define CK_CPU1 15
|
||||
|
||||
/* APB DIV CLOCKS */
|
||||
#define CK_ICN_APB1 16
|
||||
#define CK_ICN_APB2 17
|
||||
#define CK_ICN_APB3 18
|
||||
#define CK_ICN_APB4 19
|
||||
#define CK_ICN_APB5 20
|
||||
#define CK_ICN_APBDBG 21
|
||||
|
||||
/* GLOBAL TIMER */
|
||||
#define TIMG1_CK 22
|
||||
#define TIMG2_CK 23
|
||||
|
||||
/* FLEXGEN CLOCKS */
|
||||
#define CK_ICN_HS_MCU 24
|
||||
#define CK_ICN_SDMMC 25
|
||||
#define CK_ICN_DDR 26
|
||||
#define CK_ICN_DISPLAY 27
|
||||
#define CK_ICN_HSL 28
|
||||
#define CK_ICN_NIC 29
|
||||
#define CK_ICN_VID 30
|
||||
#define CK_FLEXGEN_07 31
|
||||
#define CK_FLEXGEN_08 32
|
||||
#define CK_FLEXGEN_09 33
|
||||
#define CK_FLEXGEN_10 34
|
||||
#define CK_FLEXGEN_11 35
|
||||
#define CK_FLEXGEN_12 36
|
||||
#define CK_FLEXGEN_13 37
|
||||
#define CK_FLEXGEN_14 38
|
||||
#define CK_FLEXGEN_15 39
|
||||
#define CK_FLEXGEN_16 40
|
||||
#define CK_FLEXGEN_17 41
|
||||
#define CK_FLEXGEN_18 42
|
||||
#define CK_FLEXGEN_19 43
|
||||
#define CK_FLEXGEN_20 44
|
||||
#define CK_FLEXGEN_21 45
|
||||
#define CK_FLEXGEN_22 46
|
||||
#define CK_FLEXGEN_23 47
|
||||
#define CK_FLEXGEN_24 48
|
||||
#define CK_FLEXGEN_25 49
|
||||
#define CK_FLEXGEN_26 50
|
||||
#define CK_FLEXGEN_27 51
|
||||
#define CK_FLEXGEN_28 52
|
||||
#define CK_FLEXGEN_29 53
|
||||
#define CK_FLEXGEN_30 54
|
||||
#define CK_FLEXGEN_31 55
|
||||
#define CK_FLEXGEN_32 56
|
||||
#define CK_FLEXGEN_33 57
|
||||
#define CK_FLEXGEN_34 58
|
||||
#define CK_FLEXGEN_35 59
|
||||
#define CK_FLEXGEN_36 60
|
||||
#define CK_FLEXGEN_37 61
|
||||
#define CK_FLEXGEN_38 62
|
||||
#define CK_FLEXGEN_39 63
|
||||
#define CK_FLEXGEN_40 64
|
||||
#define CK_FLEXGEN_41 65
|
||||
#define CK_FLEXGEN_42 66
|
||||
#define CK_FLEXGEN_43 67
|
||||
#define CK_FLEXGEN_44 68
|
||||
#define CK_FLEXGEN_45 69
|
||||
#define CK_FLEXGEN_46 70
|
||||
#define CK_FLEXGEN_47 71
|
||||
#define CK_FLEXGEN_48 72
|
||||
#define CK_FLEXGEN_49 73
|
||||
#define CK_FLEXGEN_50 74
|
||||
#define CK_FLEXGEN_51 75
|
||||
#define CK_FLEXGEN_52 76
|
||||
#define CK_FLEXGEN_53 77
|
||||
#define CK_FLEXGEN_54 78
|
||||
#define CK_FLEXGEN_55 79
|
||||
#define CK_FLEXGEN_56 80
|
||||
#define CK_FLEXGEN_57 81
|
||||
#define CK_FLEXGEN_58 82
|
||||
#define CK_FLEXGEN_59 83
|
||||
#define CK_FLEXGEN_60 84
|
||||
#define CK_FLEXGEN_61 85
|
||||
#define CK_FLEXGEN_62 86
|
||||
#define CK_FLEXGEN_63 87
|
||||
|
||||
/* LOW SPEED MCU CLOCK */
|
||||
#define CK_ICN_LS_MCU 88
|
||||
|
||||
#define CK_BUS_STM 89
|
||||
#define CK_BUS_FMC 90
|
||||
#define CK_BUS_ETH1 91
|
||||
#define CK_BUS_ETH2 92
|
||||
#define CK_BUS_DDRPHYC 93
|
||||
#define CK_BUS_SYSCPU1 94
|
||||
#define CK_BUS_HPDMA1 95
|
||||
#define CK_BUS_HPDMA2 96
|
||||
#define CK_BUS_HPDMA3 97
|
||||
#define CK_BUS_ADC1 98
|
||||
#define CK_BUS_ADC2 99
|
||||
#define CK_BUS_IPCC1 100
|
||||
#define CK_BUS_DCMIPSSI 101
|
||||
#define CK_BUS_CRC 102
|
||||
#define CK_BUS_MDF1 103
|
||||
#define CK_BUS_BKPSRAM 104
|
||||
#define CK_BUS_HASH1 105
|
||||
#define CK_BUS_HASH2 106
|
||||
#define CK_BUS_RNG1 107
|
||||
#define CK_BUS_RNG2 108
|
||||
#define CK_BUS_CRYP1 109
|
||||
#define CK_BUS_CRYP2 110
|
||||
#define CK_BUS_SAES 111
|
||||
#define CK_BUS_PKA 112
|
||||
#define CK_BUS_GPIOA 113
|
||||
#define CK_BUS_GPIOB 114
|
||||
#define CK_BUS_GPIOC 115
|
||||
#define CK_BUS_GPIOD 116
|
||||
#define CK_BUS_GPIOE 117
|
||||
#define CK_BUS_GPIOF 118
|
||||
#define CK_BUS_GPIOG 119
|
||||
#define CK_BUS_GPIOH 120
|
||||
#define CK_BUS_GPIOI 121
|
||||
#define CK_BUS_GPIOZ 122
|
||||
#define CK_BUS_RTC 124
|
||||
#define CK_BUS_LPUART1 125
|
||||
#define CK_BUS_LPTIM3 126
|
||||
#define CK_BUS_LPTIM4 127
|
||||
#define CK_BUS_LPTIM5 128
|
||||
#define CK_BUS_TIM2 129
|
||||
#define CK_BUS_TIM3 130
|
||||
#define CK_BUS_TIM4 131
|
||||
#define CK_BUS_TIM5 132
|
||||
#define CK_BUS_TIM6 133
|
||||
#define CK_BUS_TIM7 134
|
||||
#define CK_BUS_TIM10 135
|
||||
#define CK_BUS_TIM11 136
|
||||
#define CK_BUS_TIM12 137
|
||||
#define CK_BUS_TIM13 138
|
||||
#define CK_BUS_TIM14 139
|
||||
#define CK_BUS_LPTIM1 140
|
||||
#define CK_BUS_LPTIM2 141
|
||||
#define CK_BUS_SPI2 142
|
||||
#define CK_BUS_SPI3 143
|
||||
#define CK_BUS_SPDIFRX 144
|
||||
#define CK_BUS_USART2 145
|
||||
#define CK_BUS_USART3 146
|
||||
#define CK_BUS_UART4 147
|
||||
#define CK_BUS_UART5 148
|
||||
#define CK_BUS_I2C1 149
|
||||
#define CK_BUS_I2C2 150
|
||||
#define CK_BUS_I2C3 151
|
||||
#define CK_BUS_I3C1 152
|
||||
#define CK_BUS_I3C2 153
|
||||
#define CK_BUS_I3C3 154
|
||||
#define CK_BUS_TIM1 155
|
||||
#define CK_BUS_TIM8 156
|
||||
#define CK_BUS_TIM15 157
|
||||
#define CK_BUS_TIM16 158
|
||||
#define CK_BUS_TIM17 159
|
||||
#define CK_BUS_SAI1 160
|
||||
#define CK_BUS_SAI2 161
|
||||
#define CK_BUS_SAI3 162
|
||||
#define CK_BUS_SAI4 163
|
||||
#define CK_BUS_USART1 164
|
||||
#define CK_BUS_USART6 165
|
||||
#define CK_BUS_UART7 166
|
||||
#define CK_BUS_FDCAN 167
|
||||
#define CK_BUS_SPI1 168
|
||||
#define CK_BUS_SPI4 169
|
||||
#define CK_BUS_SPI5 170
|
||||
#define CK_BUS_SPI6 171
|
||||
#define CK_BUS_BSEC 172
|
||||
#define CK_BUS_IWDG1 173
|
||||
#define CK_BUS_IWDG2 174
|
||||
#define CK_BUS_IWDG3 175
|
||||
#define CK_BUS_IWDG4 176
|
||||
#define CK_BUS_WWDG1 177
|
||||
#define CK_BUS_VREF 178
|
||||
#define CK_BUS_DTS 179
|
||||
#define CK_BUS_SERC 180
|
||||
#define CK_BUS_HDP 181
|
||||
#define CK_BUS_DDRPERFM 182
|
||||
#define CK_BUS_OTG 183
|
||||
#define CK_BUS_LTDC 184
|
||||
#define CK_BUS_CSI 185
|
||||
#define CK_BUS_DCMIPP 186
|
||||
#define CK_BUS_DDRC 187
|
||||
#define CK_BUS_DDRCFG 188
|
||||
#define CK_BUS_STGEN 189
|
||||
#define CK_SYSDBG 190
|
||||
#define CK_KER_TIM2 191
|
||||
#define CK_KER_TIM3 192
|
||||
#define CK_KER_TIM4 193
|
||||
#define CK_KER_TIM5 194
|
||||
#define CK_KER_TIM6 195
|
||||
#define CK_KER_TIM7 196
|
||||
#define CK_KER_TIM10 197
|
||||
#define CK_KER_TIM11 198
|
||||
#define CK_KER_TIM12 199
|
||||
#define CK_KER_TIM13 200
|
||||
#define CK_KER_TIM14 201
|
||||
#define CK_KER_TIM1 202
|
||||
#define CK_KER_TIM8 203
|
||||
#define CK_KER_TIM15 204
|
||||
#define CK_KER_TIM16 205
|
||||
#define CK_KER_TIM17 206
|
||||
#define CK_BUS_SYSRAM 207
|
||||
#define CK_BUS_RETRAM 208
|
||||
#define CK_BUS_OSPI1 209
|
||||
#define CK_BUS_OTFD1 210
|
||||
#define CK_BUS_SRAM1 211
|
||||
#define CK_BUS_SDMMC1 212
|
||||
#define CK_BUS_SDMMC2 213
|
||||
#define CK_BUS_SDMMC3 214
|
||||
#define CK_BUS_DDR 215
|
||||
#define CK_BUS_RISAF4 216
|
||||
#define CK_BUS_USBHOHCI 217
|
||||
#define CK_BUS_USBHEHCI 218
|
||||
#define CK_KER_LPTIM1 219
|
||||
#define CK_KER_LPTIM2 220
|
||||
#define CK_KER_USART2 221
|
||||
#define CK_KER_UART4 222
|
||||
#define CK_KER_USART3 223
|
||||
#define CK_KER_UART5 224
|
||||
#define CK_KER_SPI2 225
|
||||
#define CK_KER_SPI3 226
|
||||
#define CK_KER_SPDIFRX 227
|
||||
#define CK_KER_I2C1 228
|
||||
#define CK_KER_I2C2 229
|
||||
#define CK_KER_I3C1 230
|
||||
#define CK_KER_I3C2 231
|
||||
#define CK_KER_I2C3 232
|
||||
#define CK_KER_I3C3 233
|
||||
#define CK_KER_SPI1 234
|
||||
#define CK_KER_SPI4 235
|
||||
#define CK_KER_SPI5 236
|
||||
#define CK_KER_SPI6 237
|
||||
#define CK_KER_USART1 238
|
||||
#define CK_KER_USART6 239
|
||||
#define CK_KER_UART7 240
|
||||
#define CK_KER_MDF1 241
|
||||
#define CK_KER_SAI1 242
|
||||
#define CK_KER_SAI2 243
|
||||
#define CK_KER_SAI3 244
|
||||
#define CK_KER_SAI4 245
|
||||
#define CK_KER_FDCAN 246
|
||||
#define CK_KER_CSI 247
|
||||
#define CK_KER_CSITXESC 248
|
||||
#define CK_KER_CSIPHY 249
|
||||
#define CK_KER_STGEN 250
|
||||
#define CK_KER_USB2PHY2EN 251
|
||||
#define CK_KER_LPUART1 252
|
||||
#define CK_KER_LPTIM3 253
|
||||
#define CK_KER_LPTIM4 254
|
||||
#define CK_KER_LPTIM5 255
|
||||
#define CK_KER_TSDBG 256
|
||||
#define CK_KER_TPIU 257
|
||||
#define CK_BUS_ETR 258
|
||||
#define CK_BUS_SYSATB 259
|
||||
#define CK_KER_ADC1 260
|
||||
#define CK_KER_ADC2 261
|
||||
#define CK_KER_OSPI1 262
|
||||
#define CK_KER_FMC 263
|
||||
#define CK_KER_SDMMC1 264
|
||||
#define CK_KER_SDMMC2 265
|
||||
#define CK_KER_SDMMC3 266
|
||||
#define CK_KER_ETH1 267
|
||||
#define CK_KER_ETH2 268
|
||||
#define CK_KER_ETH1PTP 269
|
||||
#define CK_KER_ETH2PTP 270
|
||||
#define CK_KER_USB2PHY1 271
|
||||
#define CK_KER_USB2PHY2 272
|
||||
#define CK_MCO1 273
|
||||
#define CK_MCO2 274
|
||||
#define CK_KER_DTS 275
|
||||
#define CK_ETH1_RX 276
|
||||
#define CK_ETH1_TX 277
|
||||
#define CK_ETH1_MAC 278
|
||||
#define CK_ETH2_RX 279
|
||||
#define CK_ETH2_TX 280
|
||||
#define CK_ETH2_MAC 281
|
||||
#define CK_ETH1_STP 282
|
||||
#define CK_ETH2_STP 283
|
||||
#define CK_KER_LTDC 284
|
||||
#define HSE_DIV2_CK 285
|
||||
#define CK_DBGMCU 286
|
||||
#define CK_DAP 287
|
||||
#define CK_KER_ETR 288
|
||||
#define CK_KER_STM 289
|
||||
|
||||
#define CK_SCMI_ICN_HS_MCU 0
|
||||
#define CK_SCMI_ICN_SDMMC 1
|
||||
#define CK_SCMI_ICN_DDR 2
|
||||
#define CK_SCMI_ICN_DISPLAY 3
|
||||
#define CK_SCMI_ICN_HSL 4
|
||||
#define CK_SCMI_ICN_NIC 5
|
||||
#define CK_SCMI_FLEXGEN_07 7
|
||||
#define CK_SCMI_FLEXGEN_08 8
|
||||
#define CK_SCMI_FLEXGEN_09 9
|
||||
#define CK_SCMI_FLEXGEN_10 10
|
||||
#define CK_SCMI_FLEXGEN_11 11
|
||||
#define CK_SCMI_FLEXGEN_12 12
|
||||
#define CK_SCMI_FLEXGEN_13 13
|
||||
#define CK_SCMI_FLEXGEN_14 14
|
||||
#define CK_SCMI_FLEXGEN_15 15
|
||||
#define CK_SCMI_FLEXGEN_16 16
|
||||
#define CK_SCMI_FLEXGEN_17 17
|
||||
#define CK_SCMI_FLEXGEN_18 18
|
||||
#define CK_SCMI_FLEXGEN_19 19
|
||||
#define CK_SCMI_FLEXGEN_20 20
|
||||
#define CK_SCMI_FLEXGEN_21 21
|
||||
#define CK_SCMI_FLEXGEN_22 22
|
||||
#define CK_SCMI_FLEXGEN_23 23
|
||||
#define CK_SCMI_FLEXGEN_24 24
|
||||
#define CK_SCMI_FLEXGEN_25 25
|
||||
#define CK_SCMI_FLEXGEN_26 26
|
||||
#define CK_SCMI_FLEXGEN_27 27
|
||||
#define CK_SCMI_FLEXGEN_28 28
|
||||
#define CK_SCMI_FLEXGEN_29 29
|
||||
#define CK_SCMI_FLEXGEN_30 30
|
||||
#define CK_SCMI_FLEXGEN_31 31
|
||||
#define CK_SCMI_FLEXGEN_32 32
|
||||
#define CK_SCMI_FLEXGEN_33 33
|
||||
#define CK_SCMI_FLEXGEN_34 34
|
||||
#define CK_SCMI_FLEXGEN_35 35
|
||||
#define CK_SCMI_FLEXGEN_36 36
|
||||
#define CK_SCMI_FLEXGEN_37 37
|
||||
#define CK_SCMI_FLEXGEN_38 38
|
||||
#define CK_SCMI_FLEXGEN_39 39
|
||||
#define CK_SCMI_FLEXGEN_40 40
|
||||
#define CK_SCMI_FLEXGEN_41 41
|
||||
#define CK_SCMI_FLEXGEN_42 42
|
||||
#define CK_SCMI_FLEXGEN_43 43
|
||||
#define CK_SCMI_FLEXGEN_44 44
|
||||
#define CK_SCMI_FLEXGEN_45 45
|
||||
#define CK_SCMI_FLEXGEN_46 46
|
||||
#define CK_SCMI_FLEXGEN_47 47
|
||||
#define CK_SCMI_FLEXGEN_48 48
|
||||
#define CK_SCMI_FLEXGEN_49 49
|
||||
#define CK_SCMI_FLEXGEN_50 50
|
||||
#define CK_SCMI_FLEXGEN_51 51
|
||||
#define CK_SCMI_FLEXGEN_52 52
|
||||
#define CK_SCMI_FLEXGEN_53 53
|
||||
#define CK_SCMI_FLEXGEN_54 54
|
||||
#define CK_SCMI_FLEXGEN_55 55
|
||||
#define CK_SCMI_FLEXGEN_56 56
|
||||
#define CK_SCMI_FLEXGEN_57 57
|
||||
#define CK_SCMI_FLEXGEN_58 58
|
||||
#define CK_SCMI_FLEXGEN_59 59
|
||||
#define CK_SCMI_FLEXGEN_60 60
|
||||
#define CK_SCMI_FLEXGEN_61 61
|
||||
#define CK_SCMI_FLEXGEN_62 62
|
||||
#define CK_SCMI_FLEXGEN_63 63
|
||||
#define CK_SCMI_ICN_LS_MCU 64
|
||||
#define CK_SCMI_HSE 65
|
||||
#define CK_SCMI_LSE 66
|
||||
#define CK_SCMI_HSI 67
|
||||
#define CK_SCMI_LSI 68
|
||||
#define CK_SCMI_MSI 69
|
||||
#define CK_SCMI_HSE_DIV2 70
|
||||
#define CK_SCMI_CPU1 71
|
||||
#define CK_SCMI_SYSCPU1 72
|
||||
#define CK_SCMI_PLL2 73
|
||||
#define CK_SCMI_RTC 74
|
||||
#define CK_SCMI_RTCCK 75
|
||||
#define CK_SCMI_ICN_APB1 76
|
||||
#define CK_SCMI_ICN_APB2 77
|
||||
#define CK_SCMI_ICN_APB3 78
|
||||
#define CK_SCMI_ICN_APB4 79
|
||||
#define CK_SCMI_ICN_APB5 80
|
||||
#define CK_SCMI_ICN_APBDBG 81
|
||||
#define CK_SCMI_TIMG1 82
|
||||
#define CK_SCMI_TIMG2 83
|
||||
#define CK_SCMI_BKPSRAM 84
|
||||
#define CK_SCMI_BSEC 85
|
||||
#define CK_SCMI_BUS_ETR 86
|
||||
#define CK_SCMI_FMC 87
|
||||
#define CK_SCMI_GPIOA 88
|
||||
#define CK_SCMI_GPIOB 89
|
||||
#define CK_SCMI_GPIOC 90
|
||||
#define CK_SCMI_GPIOD 91
|
||||
#define CK_SCMI_GPIOE 92
|
||||
#define CK_SCMI_GPIOF 93
|
||||
#define CK_SCMI_GPIOG 94
|
||||
#define CK_SCMI_GPIOH 95
|
||||
#define CK_SCMI_GPIOI 96
|
||||
#define CK_SCMI_GPIOZ 97
|
||||
#define CK_SCMI_HPDMA1 98
|
||||
#define CK_SCMI_HPDMA2 99
|
||||
#define CK_SCMI_HPDMA3 100
|
||||
#define CK_SCMI_IPCC1 101
|
||||
#define CK_SCMI_RETRAM 102
|
||||
#define CK_SCMI_SRAM1 103
|
||||
#define CK_SCMI_SYSRAM 104
|
||||
#define CK_SCMI_OSPI1 105
|
||||
#define CK_SCMI_TPIU 106
|
||||
#define CK_SCMI_SYSDBG 107
|
||||
#define CK_SCMI_SYSATB 108
|
||||
#define CK_SCMI_TSDBG 109
|
||||
#define CK_SCMI_BUS_STM 110
|
||||
#define CK_SCMI_KER_STM 111
|
||||
#define CK_SCMI_KER_ETR 112
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */
|
||||
138
include/dt-bindings/reset/st,stm32mp21-rcc.h
Normal file
138
include/dt-bindings/reset/st,stm32mp21-rcc.h
Normal file
@@ -0,0 +1,138 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
|
||||
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
|
||||
#define _DT_BINDINGS_STM32MP21_RESET_H_
|
||||
|
||||
#define TIM1_R 0
|
||||
#define TIM2_R 1
|
||||
#define TIM3_R 2
|
||||
#define TIM4_R 3
|
||||
#define TIM5_R 4
|
||||
#define TIM6_R 5
|
||||
#define TIM7_R 6
|
||||
#define TIM8_R 7
|
||||
#define TIM10_R 8
|
||||
#define TIM11_R 9
|
||||
#define TIM12_R 10
|
||||
#define TIM13_R 11
|
||||
#define TIM14_R 12
|
||||
#define TIM15_R 13
|
||||
#define TIM16_R 14
|
||||
#define TIM17_R 15
|
||||
#define LPTIM1_R 16
|
||||
#define LPTIM2_R 17
|
||||
#define LPTIM3_R 18
|
||||
#define LPTIM4_R 19
|
||||
#define LPTIM5_R 20
|
||||
#define SPI1_R 21
|
||||
#define SPI2_R 22
|
||||
#define SPI3_R 23
|
||||
#define SPI4_R 24
|
||||
#define SPI5_R 25
|
||||
#define SPI6_R 26
|
||||
#define SPDIFRX_R 27
|
||||
#define USART1_R 28
|
||||
#define USART2_R 29
|
||||
#define USART3_R 30
|
||||
#define UART4_R 31
|
||||
#define UART5_R 32
|
||||
#define USART6_R 33
|
||||
#define UART7_R 34
|
||||
#define LPUART1_R 35
|
||||
#define I2C1_R 36
|
||||
#define I2C2_R 37
|
||||
#define I2C3_R 38
|
||||
#define SAI1_R 39
|
||||
#define SAI2_R 40
|
||||
#define SAI3_R 41
|
||||
#define SAI4_R 42
|
||||
#define MDF1_R 43
|
||||
#define FDCAN_R 44
|
||||
#define HDP_R 45
|
||||
#define ADC1_R 46
|
||||
#define ADC2_R 47
|
||||
#define ETH1_R 48
|
||||
#define ETH2_R 49
|
||||
#define USBH_R 50
|
||||
#define USB2PHY1_R 51
|
||||
#define USB2PHY2_R 52
|
||||
#define SDMMC1_R 53
|
||||
#define SDMMC1DLL_R 54
|
||||
#define SDMMC2_R 55
|
||||
#define SDMMC2DLL_R 56
|
||||
#define SDMMC3_R 57
|
||||
#define SDMMC3DLL_R 58
|
||||
#define LTDC_R 59
|
||||
#define CSI_R 60
|
||||
#define DCMIPP_R 61
|
||||
#define DCMIPSSI_R 62
|
||||
#define WWDG1_R 63
|
||||
#define VREF_R 64
|
||||
#define DTS_R 65
|
||||
#define CRC_R 66
|
||||
#define SERC_R 67
|
||||
#define I3C1_R 68
|
||||
#define I3C2_R 69
|
||||
#define I3C3_R 70
|
||||
#define IWDG2_KER_R 71
|
||||
#define IWDG4_KER_R 72
|
||||
#define RNG1_R 73
|
||||
#define RNG2_R 74
|
||||
#define PKA_R 75
|
||||
#define SAES_R 76
|
||||
#define HASH1_R 77
|
||||
#define HASH2_R 78
|
||||
#define CRYP1_R 79
|
||||
#define CRYP2_R 80
|
||||
#define OSPI1_R 81
|
||||
#define OSPI1DLL_R 82
|
||||
#define OTG_R 83
|
||||
#define FMC_R 84
|
||||
#define DBG_R 85
|
||||
#define GPIOA_R 86
|
||||
#define GPIOB_R 87
|
||||
#define GPIOC_R 88
|
||||
#define GPIOD_R 89
|
||||
#define GPIOE_R 90
|
||||
#define GPIOF_R 91
|
||||
#define GPIOG_R 92
|
||||
#define GPIOH_R 93
|
||||
#define GPIOI_R 94
|
||||
#define GPIOZ_R 95
|
||||
#define HPDMA1_R 96
|
||||
#define HPDMA2_R 97
|
||||
#define HPDMA3_R 98
|
||||
#define IPCC1_R 99
|
||||
#define C2_HOLDBOOT_R 100
|
||||
#define C1_HOLDBOOT_R 101
|
||||
#define C1_R 102
|
||||
#define C1P1POR_R 103
|
||||
#define C1P1_R 104
|
||||
#define C2_R 105
|
||||
#define SYS_R 106
|
||||
#define VSW_R 107
|
||||
#define C1MS_R 108
|
||||
#define DDRCP_R 109
|
||||
#define DDRCAPB_R 110
|
||||
#define DDRPHYCAPB_R 111
|
||||
#define DDRCFG_R 112
|
||||
#define DDR_R 113
|
||||
#define DDRPERFM_R 114
|
||||
#define IWDG1_SYS_R 116
|
||||
#define IWDG2_SYS_R 117
|
||||
#define IWDG3_SYS_R 118
|
||||
#define IWDG4_SYS_R 119
|
||||
|
||||
#define RST_SCMI_C1_R 0
|
||||
#define RST_SCMI_C2_R 1
|
||||
#define RST_SCMI_C1_HOLDBOOT_R 2
|
||||
#define RST_SCMI_C2_HOLDBOOT_R 3
|
||||
#define RST_SCMI_FMC 4
|
||||
#define RST_SCMI_OSPI1 5
|
||||
#define RST_SCMI_OSPI1DLL 6
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
|
||||
@@ -47,8 +47,6 @@
|
||||
#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
|
||||
|
||||
#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
|
||||
#define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */
|
||||
#define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */
|
||||
#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
|
||||
#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user