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Merge tag 'samsung-pinctrl-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

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Samsung pinctrl drivers changes for v6.18

1. Add pin controller drivers for new Axis ARTPEC-8 SoC.  The SoC shares
   all main blocks, including the pin controller, with Samsung SoC, so
   same drivers and bindings are used.

2. Drop remaining support for Samsung S3C2410 SoC pin controllers.  The
   actual SoC support was removed in January 2023, so this is just
   remaining cleanup.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
2025-09-12 14:01:06 +02:00
parent 5e30210609 d37db94b07
commit cb730dac4a
6 changed files with 65 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
View File

@@ -30,8 +30,6 @@ properties:
compatible:
oneOf:
- enum:
- samsung,s3c2410-wakeup-eint
- samsung,s3c2412-wakeup-eint
- samsung,s3c64xx-wakeup-eint
- samsung,s5pv210-wakeup-eint
- samsung,exynos4210-wakeup-eint
@@ -59,27 +57,12 @@ properties:
description:
Interrupt used by multiplexed external wake-up interrupts.
minItems: 1
maxItems: 6
maxItems: 4
required:
- compatible
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,s3c2410-wakeup-eint
- samsung,s3c2412-wakeup-eint
then:
properties:
interrupts:
minItems: 6
maxItems: 6
required:
- interrupts
- if:
properties:
compatible:

5
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
View File

@@ -35,11 +35,8 @@ properties:
compatible:
enum:
- axis,artpec8-pinctrl
- google,gs101-pinctrl
- samsung,s3c2412-pinctrl
- samsung,s3c2416-pinctrl
- samsung,s3c2440-pinctrl
- samsung,s3c2450-pinctrl
- samsung,s3c64xx-pinctrl
- samsung,s5pv210-pinctrl
- samsung,exynos2200-pinctrl

50
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
View File

@@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
};
/*
* Bank type for non-alive type. Bit fields:
* CON: 4, DAT: 1, PUD: 4, DRV: 4
*/
static const struct samsung_pin_bank_type artpec_bank_type_off = {
.fld_width = { 4, 1, 4, 4, },
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
/* Pad retention control code for accessing PMU regmap */
static atomic_t exynos_shared_retention_refcnt;
@@ -1816,3 +1825,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
.ctrl = gs101_pin_ctrl,
.num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
};
/* pin banks of artpec8 pin-controller (FSYS0) */
static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst = {
ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00),
ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04),
ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08),
ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c),
ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10),
ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14),
ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18),
ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c),
ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20),
ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24),
};
/* pin banks of artpec8 pin-controller (PERIC) */
static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst = {
ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04),
ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c),
};
static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst = {
{
/* pin-controller instance 0 FSYS data */
.pin_banks = artpec8_pin_banks0,
.nr_banks = ARRAY_SIZE(artpec8_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
}, {
/* pin-controller instance 1 PERIC data */
.pin_banks = artpec8_pin_banks1,
.nr_banks = ARRAY_SIZE(artpec8_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
},
};
const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = {
.ctrl = artpec8_pin_ctrl,
.num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl),
};

10
drivers/pinctrl/samsung/pinctrl-exynos.h
View File

@@ -236,6 +236,16 @@
.name = id \
}
#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \
{ \
.type = &artpec_bank_type_off, \
.pctl_offset = reg, \
.nr_pins = pins, \
.eint_type = EINT_TYPE_GPIO, \
.eint_offset = offs, \
.name = id \
}
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.

2
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@@ -1482,6 +1482,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &s5pv210_of_data },
#endif
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
{ .compatible = "axis,artpec8-pinctrl",
.data = &artpec8_of_data },
{ .compatible = "google,gs101-pinctrl",
.data = &gs101_of_data },
{ .compatible = "samsung,exynos2200-pinctrl",

5
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@@ -381,6 +381,7 @@ struct samsung_pmx_func {
};
/* list of all exported SoC specific data */
extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
@@ -402,10 +403,6 @@ extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
extern const struct samsung_pinctrl_of_match_data fsd_of_data;
extern const struct samsung_pinctrl_of_match_data gs101_of_data;
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2440_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2450_of_data;
extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;
#endif /* __PINCTRL_SAMSUNG_H */