Merge branch 'pci/controller/sophgo'
- Add DT binding and driver for Sophgo SG2044 PCIe controller driver in Root Complex mode (Inochi Amaoto) * pci/controller/sophgo: PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode dt-bindings: pci: Add Sophgo SG2044 PCIe host
This commit is contained in:
Bjorn Helgaas
122
Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
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122
Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
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@@ -0,0 +1,122 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DesignWare based PCIe Root Complex controller on Sophgo SoCs
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maintainers:
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- Inochi Amaoto <inochiama@gmail.com>
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description:
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SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
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PCIe IP and thus inherits all the common properties defined in
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snps,dw-pcie.yaml.
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: sophgo,sg2044-pcie
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reg:
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items:
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- description: Data Bus Interface (DBI) registers
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- description: iATU registers
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- description: Config registers
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- description: Sophgo designed configuration registers
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reg-names:
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items:
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- const: dbi
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- const: atu
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- const: config
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- const: app
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clocks:
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items:
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- description: core clk
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clock-names:
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items:
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- const: core
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interrupt-controller:
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description: Interrupt controller node for handling legacy PCI interrupts.
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type: object
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properties:
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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interrupt-controller: true
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interrupts:
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items:
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- description: combined legacy interrupt
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required:
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- "#address-cells"
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- "#interrupt-cells"
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- interrupt-controller
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- interrupts
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additionalProperties: false
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msi-parent: true
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ranges:
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maxItems: 5
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required:
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- compatible
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- reg
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@6c00400000 {
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compatible = "sophgo,sg2044-pcie";
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reg = <0x6c 0x00400000 0x0 0x00001000>,
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<0x6c 0x00700000 0x0 0x00004000>,
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<0x40 0x00000000 0x0 0x00001000>,
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<0x6c 0x00780c00 0x0 0x00000400>;
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reg-names = "dbi", "atu", "config", "app";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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clocks = <&clk 0>;
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clock-names = "core";
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device_type = "pci";
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linux,pci-domain = <0>;
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msi-parent = <&msi>;
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ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
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<0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
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<0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
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<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
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<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
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interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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...
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@@ -404,6 +404,16 @@ config PCIE_UNIPHIER_EP
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Say Y here if you want PCIe endpoint controller support on
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UniPhier SoCs. This driver supports Pro5 SoC.
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config PCIE_SOPHGO_DW
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bool "Sophgo DesignWare PCIe controller (host mode)"
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depends on ARCH_SOPHGO || COMPILE_TEST
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depends on PCI_MSI
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depends on OF
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe host controller support on
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Sophgo SoCs.
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config PCIE_SPEAR13XX
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bool "STMicroelectronics SPEAr PCIe controller"
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depends on ARCH_SPEAR13XX || COMPILE_TEST
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@@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_ROCKCHIP_DW) += pcie-dw-rockchip.o
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obj-$(CONFIG_PCIE_SOPHGO_DW) += pcie-sophgo.o
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obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
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obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o
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obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
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257
drivers/pci/controller/dwc/pcie-sophgo.c
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257
drivers/pci/controller/dwc/pcie-sophgo.c
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@@ -0,0 +1,257 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Sophgo DesignWare based PCIe host controller driver
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/property.h>
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#include <linux/platform_device.h>
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#include "pcie-designware.h"
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#define to_sophgo_pcie(x) dev_get_drvdata((x)->dev)
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#define PCIE_INT_SIGNAL 0xc48
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#define PCIE_INT_EN 0xca0
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#define PCIE_INT_SIGNAL_INTX GENMASK(8, 5)
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#define PCIE_INT_EN_INTX GENMASK(4, 1)
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#define PCIE_INT_EN_INT_MSI BIT(5)
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struct sophgo_pcie {
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struct dw_pcie pci;
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void __iomem *app_base;
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struct clk_bulk_data *clks;
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unsigned int clk_cnt;
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struct irq_domain *irq_domain;
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};
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static int sophgo_pcie_readl_app(struct sophgo_pcie *sophgo, u32 reg)
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{
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return readl_relaxed(sophgo->app_base + reg);
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}
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static void sophgo_pcie_writel_app(struct sophgo_pcie *sophgo, u32 val, u32 reg)
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{
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writel_relaxed(val, sophgo->app_base + reg);
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}
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static void sophgo_pcie_intx_handler(struct irq_desc *desc)
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{
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struct dw_pcie_rp *pp = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
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unsigned long hwirq, reg;
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chained_irq_enter(chip, desc);
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reg = sophgo_pcie_readl_app(sophgo, PCIE_INT_SIGNAL);
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reg = FIELD_GET(PCIE_INT_SIGNAL_INTX, reg);
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for_each_set_bit(hwirq, ®, PCI_NUM_INTX)
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generic_handle_domain_irq(sophgo->irq_domain, hwirq);
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chained_irq_exit(chip, desc);
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}
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static void sophgo_intx_irq_mask(struct irq_data *d)
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{
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struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&pp->lock, flags);
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val = sophgo_pcie_readl_app(sophgo, PCIE_INT_EN);
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val &= ~FIELD_PREP(PCIE_INT_EN_INTX, BIT(d->hwirq));
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sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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};
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static void sophgo_intx_irq_unmask(struct irq_data *d)
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{
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struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&pp->lock, flags);
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val = sophgo_pcie_readl_app(sophgo, PCIE_INT_EN);
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val |= FIELD_PREP(PCIE_INT_EN_INTX, BIT(d->hwirq));
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sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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};
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static struct irq_chip sophgo_intx_irq_chip = {
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.name = "INTx",
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.irq_mask = sophgo_intx_irq_mask,
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.irq_unmask = sophgo_intx_irq_unmask,
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};
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static int sophgo_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sophgo_intx_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = sophgo_pcie_intx_map,
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};
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static int sophgo_pcie_init_irq_domain(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
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struct device *dev = sophgo->pci.dev;
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struct fwnode_handle *intc;
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int irq;
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intc = device_get_named_child_node(dev, "interrupt-controller");
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if (!intc) {
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dev_err(dev, "missing child interrupt-controller node\n");
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return -ENODEV;
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}
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irq = fwnode_irq_get(intc, 0);
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if (irq < 0) {
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dev_err(dev, "failed to get INTx irq number\n");
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fwnode_handle_put(intc);
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return irq;
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}
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sophgo->irq_domain = irq_domain_create_linear(intc, PCI_NUM_INTX,
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&intx_domain_ops, pp);
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fwnode_handle_put(intc);
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if (!sophgo->irq_domain) {
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dev_err(dev, "failed to get a INTx irq domain\n");
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return -EINVAL;
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}
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return irq;
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}
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static void sophgo_pcie_msi_enable(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&pp->lock, flags);
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val = sophgo_pcie_readl_app(sophgo, PCIE_INT_EN);
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val |= PCIE_INT_EN_INT_MSI;
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sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static int sophgo_pcie_host_init(struct dw_pcie_rp *pp)
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{
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int irq;
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irq = sophgo_pcie_init_irq_domain(pp);
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if (irq < 0)
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return irq;
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irq_set_chained_handler_and_data(irq, sophgo_pcie_intx_handler, pp);
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sophgo_pcie_msi_enable(pp);
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return 0;
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}
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static const struct dw_pcie_host_ops sophgo_pcie_host_ops = {
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.init = sophgo_pcie_host_init,
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};
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static int sophgo_pcie_clk_init(struct sophgo_pcie *sophgo)
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{
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struct device *dev = sophgo->pci.dev;
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int ret;
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ret = devm_clk_bulk_get_all_enabled(dev, &sophgo->clks);
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if (ret < 0)
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return dev_err_probe(dev, ret, "failed to get clocks\n");
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sophgo->clk_cnt = ret;
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return 0;
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}
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static int sophgo_pcie_resource_get(struct platform_device *pdev,
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struct sophgo_pcie *sophgo)
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{
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sophgo->app_base = devm_platform_ioremap_resource_byname(pdev, "app");
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if (IS_ERR(sophgo->app_base))
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return dev_err_probe(&pdev->dev, PTR_ERR(sophgo->app_base),
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"failed to map app registers\n");
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return 0;
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}
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static int sophgo_pcie_configure_rc(struct sophgo_pcie *sophgo)
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{
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struct dw_pcie_rp *pp;
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pp = &sophgo->pci.pp;
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pp->ops = &sophgo_pcie_host_ops;
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return dw_pcie_host_init(pp);
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}
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static int sophgo_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sophgo_pcie *sophgo;
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int ret;
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sophgo = devm_kzalloc(dev, sizeof(*sophgo), GFP_KERNEL);
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if (!sophgo)
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return -ENOMEM;
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platform_set_drvdata(pdev, sophgo);
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sophgo->pci.dev = dev;
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ret = sophgo_pcie_resource_get(pdev, sophgo);
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if (ret)
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return ret;
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ret = sophgo_pcie_clk_init(sophgo);
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if (ret)
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return ret;
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return sophgo_pcie_configure_rc(sophgo);
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}
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static const struct of_device_id sophgo_pcie_of_match[] = {
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{ .compatible = "sophgo,sg2044-pcie" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sophgo_pcie_of_match);
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static struct platform_driver sophgo_pcie_driver = {
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.driver = {
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.name = "sophgo-pcie",
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.of_match_table = sophgo_pcie_of_match,
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.suppress_bind_attrs = true,
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},
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.probe = sophgo_pcie_probe,
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};
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builtin_platform_driver(sophgo_pcie_driver);
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