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Merge branch 'dpll-zl3073x-add-misc-features'

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Ivan Vecera says:

====================
dpll: zl3073x: Add misc features

Add several new features missing in initial submission:

* Embedded sync for both pin types
* Phase offset reporting for connected input pin
* Selectable phase offset monitoring (aka all inputs phase monitor)
* Phase adjustments for both pin types
* Fractional frequency offset reporting for input pins

Everything was tested on Microchip EVB-LAN9668 EDS2 development board.
====================

Link: https://patch.msgid.link/20250715144633.149156-1-ivecera@redhat.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni
2025-07-17 15:31:56 +02:00
parent 44eb62e1ea 904c99ea36
commit e0c7e3154e
5 changed files with 1062 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

171
drivers/dpll/zl3073x/core.c
View File

@@ -669,12 +669,137 @@ zl3073x_dev_state_fetch(struct zl3073x_dev *zldev)
return rc;
}
/**
* zl3073x_ref_phase_offsets_update - update reference phase offsets
* @zldev: pointer to zl3073x_dev structure
* @channel: DPLL channel number or -1
*
* The function asks device to update phase offsets latch registers with
* the latest measured values. There are 2 sets of latch registers:
*
* 1) Up to 5 DPLL-to-connected-ref registers that contain phase offset
* values between particular DPLL channel and its *connected* input
* reference.
*
* 2) 10 selected-DPLL-to-all-ref registers that contain phase offset values
* between selected DPLL channel and all input references.
*
* If the caller is interested in 2) then it has to pass DPLL channel number
* in @channel parameter. If it is interested only in 1) then it should pass
* @channel parameter with value of -1.
*
* Return: 0 on success, <0 on error
*/
int zl3073x_ref_phase_offsets_update(struct zl3073x_dev *zldev, int channel)
{
int rc;
/* Per datasheet we have to wait for 'dpll_ref_phase_err_rqst_rd'
* to be zero to ensure that the measured data are coherent.
*/
rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
ZL_REF_PHASE_ERR_READ_RQST_RD);
if (rc)
return rc;
/* Select DPLL channel if it is specified */
if (channel != -1) {
rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_IDX, channel);
if (rc)
return rc;
}
/* Request to update phase offsets measurement values */
rc = zl3073x_write_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
ZL_REF_PHASE_ERR_READ_RQST_RD);
if (rc)
return rc;
/* Wait for finish */
return zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
ZL_REF_PHASE_ERR_READ_RQST_RD);
}
/**
* zl3073x_ref_ffo_update - update reference fractional frequency offsets
* @zldev: pointer to zl3073x_dev structure
*
* The function asks device to update fractional frequency offsets latch
* registers the latest measured values, reads and stores them into
*
* Return: 0 on success, <0 on error
*/
static int
zl3073x_ref_ffo_update(struct zl3073x_dev *zldev)
{
int i, rc;
/* Per datasheet we have to wait for 'ref_freq_meas_ctrl' to be zero
* to ensure that the measured data are coherent.
*/
rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
ZL_REF_FREQ_MEAS_CTRL);
if (rc)
return rc;
/* Select all references for measurement */
rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_3_0,
GENMASK(7, 0)); /* REF0P..REF3N */
if (rc)
return rc;
rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_4,
GENMASK(1, 0)); /* REF4P..REF4N */
if (rc)
return rc;
/* Request frequency offset measurement */
rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF);
if (rc)
return rc;
/* Wait for finish */
rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
ZL_REF_FREQ_MEAS_CTRL);
if (rc)
return rc;
/* Read DPLL-to-REFx frequency offset measurements */
for (i = 0; i < ZL3073X_NUM_REFS; i++) {
s32 value;
/* Read value stored in units of 2^-32 signed */
rc = zl3073x_read_u32(zldev, ZL_REG_REF_FREQ(i), &value);
if (rc)
return rc;
/* Convert to ppm -> ffo = (10^6 * value) / 2^32 */
zldev->ref[i].ffo = mul_s64_u64_shr(value, 1000000, 32);
}
return 0;
}
static void
zl3073x_dev_periodic_work(struct kthread_work *work)
{
struct zl3073x_dev *zldev = container_of(work, struct zl3073x_dev,
work.work);
struct zl3073x_dpll *zldpll;
int rc;
/* Update DPLL-to-connected-ref phase offsets registers */
rc = zl3073x_ref_phase_offsets_update(zldev, -1);
if (rc)
dev_warn(zldev->dev, "Failed to update phase offsets: %pe\n",
ERR_PTR(rc));
/* Update references' fractional frequency offsets */
rc = zl3073x_ref_ffo_update(zldev);
if (rc)
dev_warn(zldev->dev,
"Failed to update fractional frequency offsets: %pe\n",
ERR_PTR(rc));
list_for_each_entry(zldpll, &zldev->dplls, list)
zl3073x_dpll_changes_check(zldpll);
@@ -767,6 +892,46 @@ error:
return rc;
}
/**
* zl3073x_dev_phase_meas_setup - setup phase offset measurement
* @zldev: pointer to zl3073x_dev structure
* @num_channels: number of DPLL channels
*
* Enable phase offset measurement block, set measurement averaging factor
* and enable DPLL-to-its-ref phase measurement for all DPLLs.
*
* Returns: 0 on success, <0 on error
*/
static int
zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev, int num_channels)
{
u8 dpll_meas_ctrl, mask;
int i, rc;
/* Read DPLL phase measurement control register */
rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl);
if (rc)
return rc;
/* Setup phase measurement averaging factor */
dpll_meas_ctrl &= ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR;
dpll_meas_ctrl |= FIELD_PREP(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, 3);
/* Enable DPLL measurement block */
dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN;
/* Update phase measurement control register */
rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl);
if (rc)
return rc;
/* Enable DPLL-to-connected-ref measurement for each channel */
for (i = 0, mask = 0; i < num_channels; i++)
mask |= BIT(i);
return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask);
}
/**
* zl3073x_dev_probe - initialize zl3073x device
* @zldev: pointer to zl3073x device
@@ -839,6 +1004,12 @@ int zl3073x_dev_probe(struct zl3073x_dev *zldev,
if (rc)
return rc;
/* Setup phase offset measurement block */
rc = zl3073x_dev_phase_meas_setup(zldev, chip_info->num_channels);
if (rc)
return dev_err_probe(zldev->dev, rc,
"Failed to setup phase measurement\n");
/* Register DPLL channels */
rc = zl3073x_devm_dpll_init(zldev, chip_info->num_channels);
if (rc)

16
drivers/dpll/zl3073x/core.h
View File

@@ -30,10 +30,12 @@ struct zl3073x_dpll;
* struct zl3073x_ref - input reference invariant info
* @enabled: input reference is enabled or disabled
* @diff: true if input reference is differential
* @ffo: current fractional frequency offset
*/
struct zl3073x_ref {
bool enabled;
bool diff;
s64 ffo;
};
/**
@@ -130,6 +132,7 @@ int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val);
*****************/
int zl3073x_ref_freq_factorize(u32 freq, u16 *base, u16 *mult);
int zl3073x_ref_phase_offsets_update(struct zl3073x_dev *zldev, int channel);
static inline bool
zl3073x_is_n_pin(u8 id)
@@ -169,6 +172,19 @@ zl3073x_output_pin_out_get(u8 id)
return id / 2;
}
/**
* zl3073x_ref_ffo_get - get current fractional frequency offset
* @zldev: pointer to zl3073x device
* @index: input reference index
*
* Return: the latest measured fractional frequency offset
*/
static inline s64
zl3073x_ref_ffo_get(struct zl3073x_dev *zldev, u8 index)
{
return zldev->ref[index].ffo;
}
/**
* zl3073x_ref_is_diff - check if the given input reference is differential
* @zldev: pointer to zl3073x device

818
drivers/dpll/zl3073x/dpll.c
View File

@@ -34,7 +34,10 @@
* @id: pin id
* @prio: pin priority <0, 14>
* @selectable: pin is selectable in automatic mode
* @esync_control: embedded sync is controllable
* @pin_state: last saved pin state
* @phase_offset: last saved pin phase offset
* @freq_offset: last saved fractional frequency offset
*/
struct zl3073x_dpll_pin {
struct list_head list;
@@ -45,7 +48,17 @@ struct zl3073x_dpll_pin {
u8 id;
u8 prio;
bool selectable;
bool esync_control;
enum dpll_pin_state pin_state;
s64 phase_offset;
s64 freq_offset;
};
/*
* Supported esync ranges for input and for output per output pair type
*/
static const struct dpll_pin_frequency esync_freq_ranges[] = {
DPLL_PIN_FREQUENCY_RANGE(0, 1),
};
/**
@@ -139,6 +152,138 @@ zl3073x_dpll_input_ref_frequency_get(struct zl3073x_dpll *zldpll, u8 ref_id,
return rc;
}
static int
zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv,
struct dpll_pin_esync *esync,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
u8 ref, ref_sync_ctrl, sync_mode;
u32 esync_div, ref_freq;
int rc;
/* Get reference frequency */
ref = zl3073x_input_pin_ref_get(pin->id);
rc = zl3073x_dpll_input_ref_frequency_get(zldpll, pin->id, &ref_freq);
if (rc)
return rc;
guard(mutex)(&zldev->multiop_lock);
/* Read reference configuration into mailbox */
rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
ZL_REG_REF_MB_MASK, BIT(ref));
if (rc)
return rc;
/* Get ref sync mode */
rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl);
if (rc)
return rc;
/* Get esync divisor */
rc = zl3073x_read_u32(zldev, ZL_REG_REF_ESYNC_DIV, &esync_div);
if (rc)
return rc;
sync_mode = FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref_sync_ctrl);
switch (sync_mode) {
case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75:
esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0;
esync->pulse = 25;
break;
default:
esync->freq = 0;
esync->pulse = 0;
break;
}
/* If the pin supports esync control expose its range but only
* if the current reference frequency is > 1 Hz.
*/
if (pin->esync_control && ref_freq > 1) {
esync->range = esync_freq_ranges;
esync->range_num = ARRAY_SIZE(esync_freq_ranges);
} else {
esync->range = NULL;
esync->range_num = 0;
}
return rc;
}
static int
zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv, u64 freq,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
u8 ref, ref_sync_ctrl, sync_mode;
int rc;
guard(mutex)(&zldev->multiop_lock);
/* Read reference configuration into mailbox */
ref = zl3073x_input_pin_ref_get(pin->id);
rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
ZL_REG_REF_MB_MASK, BIT(ref));
if (rc)
return rc;
/* Get ref sync mode */
rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl);
if (rc)
return rc;
/* Use freq == 0 to disable esync */
if (!freq)
sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF;
else
sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75;
ref_sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE;
ref_sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode);
/* Update ref sync control register */
rc = zl3073x_write_u8(zldev, ZL_REG_REF_SYNC_CTRL, ref_sync_ctrl);
if (rc)
return rc;
if (freq) {
/* 1 Hz is only supported frequnecy currently */
rc = zl3073x_write_u32(zldev, ZL_REG_REF_ESYNC_DIV,
ZL_REF_ESYNC_DIV_1HZ);
if (rc)
return rc;
}
/* Commit reference configuration */
return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR,
ZL_REG_REF_MB_MASK, BIT(ref));
}
static int
zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv,
const struct dpll_device *dpll, void *dpll_priv,
s64 *ffo, struct netlink_ext_ack *extack)
{
struct zl3073x_dpll_pin *pin = pin_priv;
*ffo = pin->freq_offset;
return 0;
}
static int
zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
@@ -367,6 +512,161 @@ zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref)
return 0;
}
static int
zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv, s64 *phase_offset,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
u8 conn_ref, ref, ref_status;
s64 ref_phase;
int rc;
/* Get currently connected reference */
rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_ref);
if (rc)
return rc;
/* Report phase offset only for currently connected pin if the phase
* monitor feature is disabled.
*/
ref = zl3073x_input_pin_ref_get(pin->id);
if (!zldpll->phase_monitor && ref != conn_ref) {
*phase_offset = 0;
return 0;
}
/* Get this pin monitor status */
rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &ref_status);
if (rc)
return rc;
/* Report phase offset only if the input pin signal is present */
if (ref_status != ZL_REF_MON_STATUS_OK) {
*phase_offset = 0;
return 0;
}
ref_phase = pin->phase_offset;
/* The DPLL being locked to a higher freq than the current ref
* the phase offset is modded to the period of the signal
* the dpll is locked to.
*/
if (ZL3073X_DPLL_REF_IS_VALID(conn_ref) && conn_ref != ref) {
u32 conn_freq, ref_freq;
/* Get frequency of connected ref */
rc = zl3073x_dpll_input_ref_frequency_get(zldpll, conn_ref,
&conn_freq);
if (rc)
return rc;
/* Get frequency of given ref */
rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref,
&ref_freq);
if (rc)
return rc;
if (conn_freq > ref_freq) {
s64 conn_period, div_factor;
conn_period = div_s64(PSEC_PER_SEC, conn_freq);
div_factor = div64_s64(ref_phase, conn_period);
ref_phase -= conn_period * div_factor;
}
}
*phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER;
return rc;
}
static int
zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv,
s32 *phase_adjust,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
s64 phase_comp;
u8 ref;
int rc;
guard(mutex)(&zldev->multiop_lock);
/* Read reference configuration */
ref = zl3073x_input_pin_ref_get(pin->id);
rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
ZL_REG_REF_MB_MASK, BIT(ref));
if (rc)
return rc;
/* Read current phase offset compensation */
rc = zl3073x_read_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, &phase_comp);
if (rc)
return rc;
/* Perform sign extension for 48bit signed value */
phase_comp = sign_extend64(phase_comp, 47);
/* Reverse two's complement negation applied during set and convert
* to 32bit signed int
*/
*phase_adjust = (s32)-phase_comp;
return rc;
}
static int
zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv,
s32 phase_adjust,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
s64 phase_comp;
u8 ref;
int rc;
/* The value in the register is stored as two's complement negation
* of requested value.
*/
phase_comp = -phase_adjust;
guard(mutex)(&zldev->multiop_lock);
/* Read reference configuration */
ref = zl3073x_input_pin_ref_get(pin->id);
rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD,
ZL_REG_REF_MB_MASK, BIT(ref));
if (rc)
return rc;
/* Write the requested value into the compensation register */
rc = zl3073x_write_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, phase_comp);
if (rc)
return rc;
/* Commit reference configuration */
return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR,
ZL_REG_REF_MB_MASK, BIT(ref));
}
/**
* zl3073x_dpll_ref_prio_get - get priority for given input pin
* @pin: pointer to pin
@@ -640,6 +940,220 @@ zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv,
return 0;
}
static int
zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv,
struct dpll_pin_esync *esync,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
struct device *dev = zldev->dev;
u32 esync_period, esync_width;
u8 clock_type, synth;
u8 out, output_mode;
u32 output_div;
u32 synth_freq;
int rc;
out = zl3073x_output_pin_out_get(pin->id);
/* If N-division is enabled, esync is not supported. The register used
* for N-division is also used for the esync divider so both cannot
* be used.
*/
switch (zl3073x_out_signal_format_get(zldev, out)) {
case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
return -EOPNOTSUPP;
default:
break;
}
guard(mutex)(&zldev->multiop_lock);
/* Read output configuration into mailbox */
rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
ZL_REG_OUTPUT_MB_MASK, BIT(out));
if (rc)
return rc;
/* Read output mode */
rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode);
if (rc)
return rc;
/* Read output divisor */
rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div);
if (rc)
return rc;
/* Check output divisor for zero */
if (!output_div) {
dev_err(dev, "Zero divisor for OUTPUT%u got from device\n",
out);
return -EINVAL;
}
/* Get synth attached to output pin */
synth = zl3073x_out_synth_get(zldev, out);
/* Get synth frequency */
synth_freq = zl3073x_synth_freq_get(zldev, synth);
clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, output_mode);
if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) {
/* No need to read esync data if it is not enabled */
esync->freq = 0;
esync->pulse = 0;
goto finish;
}
/* Read esync period */
rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &esync_period);
if (rc)
return rc;
/* Check esync divisor for zero */
if (!esync_period) {
dev_err(dev, "Zero esync divisor for OUTPUT%u got from device\n",
out);
return -EINVAL;
}
/* Get esync pulse width in units of half synth cycles */
rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, &esync_width);
if (rc)
return rc;
/* Compute esync frequency */
esync->freq = synth_freq / output_div / esync_period;
/* By comparing the esync_pulse_width to the half of the pulse width
* the esync pulse percentage can be determined.
* Note that half pulse width is in units of half synth cycles, which
* is why it reduces down to be output_div.
*/
esync->pulse = (50 * esync_width) / output_div;
finish:
/* Set supported esync ranges if the pin supports esync control and
* if the output frequency is > 1 Hz.
*/
if (pin->esync_control && (synth_freq / output_div) > 1) {
esync->range = esync_freq_ranges;
esync->range_num = ARRAY_SIZE(esync_freq_ranges);
} else {
esync->range = NULL;
esync->range_num = 0;
}
return 0;
}
static int
zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv, u64 freq,
struct netlink_ext_ack *extack)
{
u32 esync_period, esync_width, output_div;
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
u8 clock_type, out, output_mode, synth;
u32 synth_freq;
int rc;
out = zl3073x_output_pin_out_get(pin->id);
/* If N-division is enabled, esync is not supported. The register used
* for N-division is also used for the esync divider so both cannot
* be used.
*/
switch (zl3073x_out_signal_format_get(zldev, out)) {
case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV:
case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV:
return -EOPNOTSUPP;
default:
break;
}
guard(mutex)(&zldev->multiop_lock);
/* Read output configuration into mailbox */
rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
ZL_REG_OUTPUT_MB_MASK, BIT(out));
if (rc)
return rc;
/* Read output mode */
rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode);
if (rc)
return rc;
/* Select clock type */
if (freq)
clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC;
else
clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL;
/* Update clock type in output mode */
output_mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE;
output_mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type);
rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_MODE, output_mode);
if (rc)
return rc;
/* If esync is being disabled just write mailbox and finish */
if (!freq)
goto write_mailbox;
/* Get synth attached to output pin */
synth = zl3073x_out_synth_get(zldev, out);
/* Get synth frequency */
synth_freq = zl3073x_synth_freq_get(zldev, synth);
rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div);
if (rc)
return rc;
/* Check output divisor for zero */
if (!output_div) {
dev_err(zldev->dev,
"Zero divisor for OUTPUT%u got from device\n", out);
return -EINVAL;
}
/* Compute and update esync period */
esync_period = synth_freq / (u32)freq / output_div;
rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, esync_period);
if (rc)
return rc;
/* Half of the period in units of 1/2 synth cycle can be represented by
* the output_div. To get the supported esync pulse width of 25% of the
* period the output_div can just be divided by 2. Note that this
* assumes that output_div is even, otherwise some resolution will be
* lost.
*/
esync_width = output_div / 2;
rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, esync_width);
if (rc)
return rc;
write_mailbox:
/* Commit output configuration */
return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR,
ZL_REG_OUTPUT_MB_MASK, BIT(out));
}
static int
zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
@@ -863,6 +1377,114 @@ zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin,
ZL_REG_OUTPUT_MB_MASK, BIT(out));
}
static int
zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv,
s32 *phase_adjust,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
u32 synth_freq;
s32 phase_comp;
u8 out, synth;
int rc;
out = zl3073x_output_pin_out_get(pin->id);
synth = zl3073x_out_synth_get(zldev, out);
synth_freq = zl3073x_synth_freq_get(zldev, synth);
/* Check synth freq for zero */
if (!synth_freq) {
dev_err(zldev->dev, "Got zero synth frequency for output %u\n",
out);
return -EINVAL;
}
guard(mutex)(&zldev->multiop_lock);
/* Read output configuration */
rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
ZL_REG_OUTPUT_MB_MASK, BIT(out));
if (rc)
return rc;
/* Read current output phase compensation */
rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, &phase_comp);
if (rc)
return rc;
/* Value in register is expressed in half synth clock cycles */
phase_comp *= (int)div_u64(PSEC_PER_SEC, 2 * synth_freq);
/* Reverse two's complement negation applied during 'set' */
*phase_adjust = -phase_comp;
return rc;
}
static int
zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
void *pin_priv,
const struct dpll_device *dpll,
void *dpll_priv,
s32 phase_adjust,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
struct zl3073x_dev *zldev = zldpll->dev;
struct zl3073x_dpll_pin *pin = pin_priv;
int half_synth_cycle;
u32 synth_freq;
u8 out, synth;
int rc;
/* Get attached synth */
out = zl3073x_output_pin_out_get(pin->id);
synth = zl3073x_out_synth_get(zldev, out);
/* Get synth's frequency */
synth_freq = zl3073x_synth_freq_get(zldev, synth);
/* Value in register is expressed in half synth clock cycles so
* the given phase adjustment a multiple of half synth clock.
*/
half_synth_cycle = (int)div_u64(PSEC_PER_SEC, 2 * synth_freq);
if ((phase_adjust % half_synth_cycle) != 0) {
NL_SET_ERR_MSG_FMT(extack,
"Phase adjustment value has to be multiple of %d",
half_synth_cycle);
return -EINVAL;
}
phase_adjust /= half_synth_cycle;
/* The value in the register is stored as two's complement negation
* of requested value.
*/
phase_adjust = -phase_adjust;
guard(mutex)(&zldev->multiop_lock);
/* Read output configuration */
rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
ZL_REG_OUTPUT_MB_MASK, BIT(out));
if (rc)
return rc;
/* Write the requested value into the compensation register */
rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, phase_adjust);
if (rc)
return rc;
/* Update output configuration from mailbox */
return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR,
ZL_REG_OUTPUT_MB_MASK, BIT(out));
}
static int
zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin,
void *pin_priv,
@@ -954,10 +1576,45 @@ zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv,
return 0;
}
static int
zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll,
void *dpll_priv,
enum dpll_feature_state *state,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
if (zldpll->phase_monitor)
*state = DPLL_FEATURE_STATE_ENABLE;
else
*state = DPLL_FEATURE_STATE_DISABLE;
return 0;
}
static int
zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll,
void *dpll_priv,
enum dpll_feature_state state,
struct netlink_ext_ack *extack)
{
struct zl3073x_dpll *zldpll = dpll_priv;
zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE);
return 0;
}
static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = {
.direction_get = zl3073x_dpll_pin_direction_get,
.esync_get = zl3073x_dpll_input_pin_esync_get,
.esync_set = zl3073x_dpll_input_pin_esync_set,
.ffo_get = zl3073x_dpll_input_pin_ffo_get,
.frequency_get = zl3073x_dpll_input_pin_frequency_get,
.frequency_set = zl3073x_dpll_input_pin_frequency_set,
.phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get,
.phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get,
.phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set,
.prio_get = zl3073x_dpll_input_pin_prio_get,
.prio_set = zl3073x_dpll_input_pin_prio_set,
.state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get,
@@ -966,14 +1623,20 @@ static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = {
static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = {
.direction_get = zl3073x_dpll_pin_direction_get,
.esync_get = zl3073x_dpll_output_pin_esync_get,
.esync_set = zl3073x_dpll_output_pin_esync_set,
.frequency_get = zl3073x_dpll_output_pin_frequency_get,
.frequency_set = zl3073x_dpll_output_pin_frequency_set,
.phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get,
.phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set,
.state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get,
};
static const struct dpll_device_ops zl3073x_dpll_device_ops = {
.lock_status_get = zl3073x_dpll_lock_status_get,
.mode_get = zl3073x_dpll_mode_get,
.phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get,
.phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set,
};
/**
@@ -1040,8 +1703,9 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index)
if (IS_ERR(props))
return PTR_ERR(props);
/* Save package label */
/* Save package label & esync capability */
strscpy(pin->label, props->package_label);
pin->esync_control = props->esync_control;
if (zl3073x_dpll_is_input_pin(pin)) {
rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio);
@@ -1325,6 +1989,128 @@ zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll)
zldpll->dpll_dev = NULL;
}
/**
* zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change
* @pin: pin to check
*
* Check for the change of DPLL to connected pin phase offset change.
*
* Return: true on phase offset change, false otherwise
*/
static bool
zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin)
{
struct zl3073x_dpll *zldpll = pin->dpll;
struct zl3073x_dev *zldev = zldpll->dev;
unsigned int reg;
s64 phase_offset;
u8 ref;
int rc;
ref = zl3073x_input_pin_ref_get(pin->id);
/* Select register to read phase offset value depending on pin and
* phase monitor state:
* 1) For connected pin use dpll_phase_err_data register
* 2) For other pins use appropriate ref_phase register if the phase
* monitor feature is enabled and reference monitor does not
* report signal errors for given input pin
*/
if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) {
reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id);
} else if (zldpll->phase_monitor) {
u8 status;
/* Get reference monitor status */
rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref),
&status);
if (rc) {
dev_err(zldev->dev,
"Failed to read %s refmon status: %pe\n",
pin->label, ERR_PTR(rc));
return false;
}
if (status != ZL_REF_MON_STATUS_OK)
return false;
reg = ZL_REG_REF_PHASE(ref);
} else {
/* The pin is not connected or phase monitor disabled */
return false;
}
/* Read measured phase offset value */
rc = zl3073x_read_u48(zldev, reg, &phase_offset);
if (rc) {
dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n",
ERR_PTR(rc));
return false;
}
/* Convert to ps */
phase_offset = div_s64(sign_extend64(phase_offset, 47), 100);
/* Compare with previous value */
if (phase_offset != pin->phase_offset) {
dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n",
pin->label, pin->phase_offset, phase_offset);
pin->phase_offset = phase_offset;
return true;
}
return false;
}
/**
* zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change
* @pin: pin to check
*
* Check for the given pin's fractional frequency change.
*
* Return: true on fractional frequency offset change, false otherwise
*/
static bool
zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin)
{
struct zl3073x_dpll *zldpll = pin->dpll;
struct zl3073x_dev *zldev = zldpll->dev;
u8 ref, status;
s64 ffo;
int rc;
/* Get reference monitor status */
ref = zl3073x_input_pin_ref_get(pin->id);
rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &status);
if (rc) {
dev_err(zldev->dev, "Failed to read %s refmon status: %pe\n",
pin->label, ERR_PTR(rc));
return false;
}
/* Do not report ffo changes if the reference monitor report errors */
if (status != ZL_REF_MON_STATUS_OK)
return false;
/* Get the latest measured ref's ffo */
ffo = zl3073x_ref_ffo_get(zldev, ref);
/* Compare with previous value */
if (pin->freq_offset != ffo) {
dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n",
pin->label, pin->freq_offset, ffo);
pin->freq_offset = ffo;
return true;
}
return false;
}
/**
* zl3073x_dpll_changes_check - check for changes and send notifications
* @zldpll: pointer to zl3073x_dpll structure
@@ -1343,6 +2129,8 @@ zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll)
struct zl3073x_dpll_pin *pin;
int rc;
zldpll->check_count++;
/* Get current lock status for the DPLL */
rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll,
&lock_status, NULL, NULL);
@@ -1365,8 +2153,22 @@ zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll)
zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK)
return;
/* Update phase offset latch registers for this DPLL if the phase
* offset monitor feature is enabled.
*/
if (zldpll->phase_monitor) {
rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id);
if (rc) {
dev_err(zldev->dev,
"Failed to update phase offsets: %pe\n",
ERR_PTR(rc));
return;
}
}
list_for_each_entry(pin, &zldpll->pins, list) {
enum dpll_pin_state state;
bool pin_changed = false;
/* Output pins change checks are not necessary because output
* states are constant.
@@ -1386,8 +2188,20 @@ zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll)
dev_dbg(dev, "%s state changed: %u->%u\n", pin->label,
pin->pin_state, state);
pin->pin_state = state;
dpll_pin_change_ntf(pin->dpll_pin);
pin_changed = true;
}
/* Check for phase offset and ffo change once per second */
if (zldpll->check_count % 2 == 0) {
if (zl3073x_dpll_pin_phase_offset_check(pin))
pin_changed = true;
if (zl3073x_dpll_pin_ffo_check(pin))
pin_changed = true;
}
if (pin_changed)
dpll_pin_change_ntf(pin->dpll_pin);
}
}

4
drivers/dpll/zl3073x/dpll.h
View File

@@ -15,6 +15,8 @@
* @id: DPLL index
* @refsel_mode: reference selection mode
* @forced_ref: selected reference in forced reference lock mode
* @check_count: periodic check counter
* @phase_monitor: is phase offset monitor enabled
* @dpll_dev: pointer to registered DPLL device
* @lock_status: last saved DPLL lock status
* @pins: list of pins
@@ -25,6 +27,8 @@ struct zl3073x_dpll {
u8 id;
u8 refsel_mode;
u8 forced_ref;
u8 check_count;
bool phase_monitor;
struct dpll_device *dpll_dev;
enum dpll_lock_status lock_status;
struct list_head pins;

55
drivers/dpll/zl3073x/regs.h
View File

@@ -94,6 +94,35 @@
#define ZL_DPLL_REFSEL_STATUS_STATE GENMASK(6, 4)
#define ZL_DPLL_REFSEL_STATUS_STATE_LOCK 4
#define ZL_REG_REF_FREQ(_idx) \
ZL_REG_IDX(_idx, 2, 0x44, 4, ZL3073X_NUM_REFS, 4)
/**********************
* Register Page 4, Ref
**********************/
#define ZL_REG_REF_PHASE_ERR_READ_RQST ZL_REG(4, 0x0f, 1)
#define ZL_REF_PHASE_ERR_READ_RQST_RD BIT(0)
#define ZL_REG_REF_FREQ_MEAS_CTRL ZL_REG(4, 0x1c, 1)
#define ZL_REF_FREQ_MEAS_CTRL GENMASK(1, 0)
#define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ 1
#define ZL_REF_FREQ_MEAS_CTRL_REF_FREQ_OFF 2
#define ZL_REF_FREQ_MEAS_CTRL_DPLL_FREQ_OFF 3
#define ZL_REG_REF_FREQ_MEAS_MASK_3_0 ZL_REG(4, 0x1d, 1)
#define ZL_REF_FREQ_MEAS_MASK_3_0(_ref) BIT(_ref)
#define ZL_REG_REF_FREQ_MEAS_MASK_4 ZL_REG(4, 0x1e, 1)
#define ZL_REF_FREQ_MEAS_MASK_4(_ref) BIT((_ref) - 8)
#define ZL_REG_DPLL_MEAS_REF_FREQ_CTRL ZL_REG(4, 0x1f, 1)
#define ZL_DPLL_MEAS_REF_FREQ_CTRL_EN BIT(0)
#define ZL_DPLL_MEAS_REF_FREQ_CTRL_IDX GENMASK(6, 4)
#define ZL_REG_REF_PHASE(_idx) \
ZL_REG_IDX(_idx, 4, 0x20, 6, ZL3073X_NUM_REFS, 6)
/***********************
* Register Page 5, DPLL
***********************/
@@ -108,6 +137,18 @@
#define ZL_DPLL_MODE_REFSEL_MODE_NCO 4
#define ZL_DPLL_MODE_REFSEL_REF GENMASK(7, 4)
#define ZL_REG_DPLL_MEAS_CTRL ZL_REG(5, 0x50, 1)
#define ZL_DPLL_MEAS_CTRL_EN BIT(0)
#define ZL_DPLL_MEAS_CTRL_AVG_FACTOR GENMASK(7, 4)
#define ZL_REG_DPLL_MEAS_IDX ZL_REG(5, 0x51, 1)
#define ZL_DPLL_MEAS_IDX GENMASK(2, 0)
#define ZL_REG_DPLL_PHASE_ERR_READ_MASK ZL_REG(5, 0x54, 1)
#define ZL_REG_DPLL_PHASE_ERR_DATA(_idx) \
ZL_REG_IDX(_idx, 5, 0x55, 6, ZL3073X_MAX_CHANNELS, 6)
/***********************************
* Register Page 9, Synth and Output
***********************************/
@@ -146,6 +187,16 @@
#define ZL_REF_CONFIG_ENABLE BIT(0)
#define ZL_REF_CONFIG_DIFF_EN BIT(2)
#define ZL_REG_REF_PHASE_OFFSET_COMP ZL_REG(10, 0x28, 6)
#define ZL_REG_REF_SYNC_CTRL ZL_REG(10, 0x2e, 1)
#define ZL_REF_SYNC_CTRL_MODE GENMASK(2, 0)
#define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF 0
#define ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75 2
#define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4)
#define ZL_REF_ESYNC_DIV_1HZ 0
/********************************
* Register Page 12, DPLL Mailbox
********************************/
@@ -188,6 +239,9 @@
#define ZL_OUTPUT_MB_SEM_RD BIT(1)
#define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1)
#define ZL_OUTPUT_MODE_CLOCK_TYPE GENMASK(2, 0)
#define ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL 0
#define ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC 1
#define ZL_OUTPUT_MODE_SIGNAL_FORMAT GENMASK(7, 4)
#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DISABLED 0
#define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LVDS 1
@@ -204,5 +258,6 @@
#define ZL_REG_OUTPUT_WIDTH ZL_REG(14, 0x10, 4)
#define ZL_REG_OUTPUT_ESYNC_PERIOD ZL_REG(14, 0x14, 4)
#define ZL_REG_OUTPUT_ESYNC_WIDTH ZL_REG(14, 0x18, 4)
#define ZL_REG_OUTPUT_PHASE_COMP ZL_REG(14, 0x20, 4)
#endif /* _ZL3073X_REGS_H */