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Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next

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* clk-renesas: (42 commits)
  clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
  clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
  clk: renesas: r9a09g057: Add XSPI clock/reset
  clk: renesas: r9a09g056: Add XSPI clock/reset
  clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
  clk: renesas: r9a09g057: Add support for xspi mux and divider
  clk: renesas: r9a09g056: Add support for xspi mux and divider
  clk: renesas: r9a09g077: Add RIIC module clocks
  clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
  clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
  clk: renesas: r9a09g057: Add entries for the RSPIs
  dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
  dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
  clk: renesas: rzv2h: Add missing include file
  clk: renesas: rzv2h: Use devm_kmemdup_array()
  clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
  clk: renesas: r9a09g077: Add PCLKL core clock
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
  dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
  dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
  ...

* clk-samsung:
  clk: samsung: exynosautov920: add block hsi2 clock support
  dt-bindings: clock: exynosautov920: add hsi2 clock definitions
  dt-bindings: clock: exynosautov920: sort clock definitions
  clk: samsung: exynos850: fix a comment
  clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
  clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD

* clk-spacemit:
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  reset: spacemit: add support for SpacemiT CCU resets
  clk: spacemit: mark K1 pll1_d8 as critical
  clk: spacemit: define three reset-only CCUs
  clk: spacemit: set up reset auxiliary devices
  soc: spacemit: create a header for clock/reset registers
  dt-bindings: soc: spacemit: define spacemit,k1-ccu resets

* clk-allwinner:
  clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
  clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
  clk: sunxi-ng: v3s: Fix de clock definition
  clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
  dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset

* clk-amlogic:
  clk: amlogic: s4: remove unused data
  clk: amlogic: drop clk_regmap tables
  clk: amlogic: get regmap with clk_regmap_init
  clk: amlogic: remove unnecessary headers
  clk: amlogic: axg-audio: use the auxiliary reset driver
This commit is contained in:
Stephen Boyd
2025-07-29 15:18:33 -07:00
parent f7887ee4ee b1712f94f7 2a5cebd0fc c60b95389d 0b4ff5bc7d 8e76682359
commit e3abdd1870
96 changed files with 3346 additions and 4250 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
View File

@@ -52,9 +52,16 @@ properties:
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
- renesas,r8a779g0-cpg-mssr # R-Car V4H
- renesas,r8a779h0-cpg-mssr # R-Car V4M
- renesas,r9a09g077-cpg-mssr # RZ/T2H
- renesas,r9a09g087-cpg-mssr # RZ/N2H
reg:
maxItems: 1
minItems: 1
items:
- description: base address of register block 0
- description: base address of register block 1
description: base addresses of clock controller. Some controllers
(like r9a09g077) use two blocks instead of a single one.
clocks:
minItems: 1
@@ -92,16 +99,6 @@ properties:
the datasheet.
const: 1
if:
not:
properties:
compatible:
items:
enum:
- renesas,r7s9210-cpg-mssr
then:
required:
- '#reset-cells'
required:
- compatible
@@ -111,6 +108,36 @@ required:
- '#clock-cells'
- '#power-domain-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- renesas,r9a09g077-cpg-mssr
- renesas,r9a09g087-cpg-mssr
then:
properties:
reg:
minItems: 2
clock-names:
items:
- const: extal
else:
properties:
reg:
maxItems: 1
- if:
not:
properties:
compatible:
items:
enum:
- renesas,r7s9210-cpg-mssr
then:
required:
- '#reset-cells'
additionalProperties: false
examples:

18
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
View File

@@ -57,8 +57,7 @@ properties:
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
be used to reference individual CPG power domains.
const: 0
'#reset-cells':
description:
@@ -77,21 +76,6 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a08g045-cpg
then:
properties:
'#power-domain-cells':
const: 1
else:
properties:
'#power-domain-cells':
const: 0
examples:
- |
cpg: clock-controller@11010000 {

37
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
View File

@@ -32,23 +32,24 @@ description: |
properties:
compatible:
enum:
- samsung,exynosautov920-cmu-top
- samsung,exynosautov920-cmu-cpucl0
- samsung,exynosautov920-cmu-cpucl1
- samsung,exynosautov920-cmu-cpucl2
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-hsi0
- samsung,exynosautov920-cmu-hsi1
- samsung,exynosautov920-cmu-hsi2
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- samsung,exynosautov920-cmu-top
clocks:
minItems: 1
maxItems: 4
maxItems: 5
clock-names:
minItems: 1
maxItems: 4
maxItems: 5
"#clock-cells":
const: 1
@@ -201,6 +202,30 @@ allOf:
- const: usbdrd
- const: mmc_card
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-hsi2
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_HSI2 NOC clock (from CMU_TOP)
- description: CMU_HSI2 NOC UFS clock (from CMU_TOP)
- description: CMU_HSI2 UFS EMBD clock (from CMU_TOP)
- description: CMU_HSI2 ETHERNET clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: ufs
- const: embd
- const: ethernet
required:
- compatible
- "#clock-cells"

10
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
View File

@@ -602,6 +602,16 @@ properties:
- renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
- const: renesas,r9a09g077
- description: RZ/N2H (R9A09G087)
items:
- enum:
- renesas,rzn2h-evk # RZ/N2H Evaluation Board (RTK9RZN2H0S00000BJ)
- enum:
- renesas,r9a09g087m04 # RZ/N2H with Single Cortex-A55 + Dual Cortex-R52 - no security
- renesas,r9a09g087m24 # RZ/N2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
- renesas,r9a09g087m44 # RZ/N2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
- const: renesas,r9a09g087
additionalProperties: true
...

29
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
View File

@@ -19,6 +19,9 @@ properties:
- spacemit,k1-syscon-apbc
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
- spacemit,k1-syscon-rcpu
- spacemit,k1-syscon-rcpu2
- spacemit,k1-syscon-apbc2
reg:
maxItems: 1
@@ -47,9 +50,6 @@ properties:
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
- "#reset-cells"
allOf:
@@ -57,13 +57,28 @@ allOf:
properties:
compatible:
contains:
const: spacemit,k1-syscon-apbc
enum:
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
then:
properties:
"#power-domain-cells": false
else:
required:
- "#power-domain-cells"
else:
properties:
"#power-domain-cells": false
- if:
properties:
compatible:
contains:
enum:
- spacemit,k1-syscon-apbc
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
then:
required:
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false

4
drivers/clk/meson/Kconfig
View File

@@ -5,6 +5,7 @@ menu "Clock support for Amlogic platforms"
config COMMON_CLK_MESON_REGMAP
tristate
select REGMAP
select MFD_SYSCON
config COMMON_CLK_MESON_DUALDIV
tristate
@@ -106,7 +107,8 @@ config COMMON_CLK_AXG_AUDIO
select COMMON_CLK_MESON_SCLK_DIV
select COMMON_CLK_MESON_CLKC_UTILS
select REGMAP_MMIO
select RESET_CONTROLLER
select AUXILIARY_BUS
imply RESET_MESON_AUX
help
Support for the audio clock controller on AmLogic A113D devices,
aka axg, Say Y if you want audio subsystem to work.

194
drivers/clk/meson/a1-peripherals.c
View File

@@ -10,13 +10,42 @@
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "a1-peripherals.h"
#include "clk-dualdiv.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
#define SYS_OSCIN_CTRL 0x0
#define RTC_BY_OSCIN_CTRL0 0x4
#define RTC_BY_OSCIN_CTRL1 0x8
#define RTC_CTRL 0xc
#define SYS_CLK_CTRL0 0x10
#define SYS_CLK_EN0 0x1c
#define SYS_CLK_EN1 0x20
#define AXI_CLK_EN 0x24
#define DSPA_CLK_EN 0x28
#define DSPB_CLK_EN 0x2c
#define DSPA_CLK_CTRL0 0x30
#define DSPB_CLK_CTRL0 0x34
#define CLK12_24_CTRL 0x38
#define GEN_CLK_CTRL 0x3c
#define SAR_ADC_CLK_CTRL 0xc0
#define PWM_CLK_AB_CTRL 0xc4
#define PWM_CLK_CD_CTRL 0xc8
#define PWM_CLK_EF_CTRL 0xcc
#define SPICC_CLK_CTRL 0xd0
#define TS_CLK_CTRL 0xd4
#define SPIFC_CLK_CTRL 0xd8
#define USB_BUSCLK_CTRL 0xdc
#define SD_EMMC_CLK_CTRL 0xe0
#define CECA_CLK_CTRL0 0xe4
#define CECA_CLK_CTRL1 0xe8
#define CECB_CLK_CTRL0 0xec
#define CECB_CLK_CTRL1 0xf0
#define PSRAM_CLK_CTRL 0xf4
#define DMC_CLK_CTRL 0xf8
static struct clk_regmap xtal_in = {
.data = &(struct clk_regmap_gate_data){
.offset = SYS_OSCIN_CTRL,
@@ -2026,163 +2055,6 @@ static struct clk_hw *a1_periphs_hw_clks[] = {
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
};
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const a1_periphs_regmaps[] = {
&xtal_in,
&fixpll_in,
&usb_phy_in,
&usb_ctrl_in,
&hifipll_in,
&syspll_in,
&dds_in,
&sys,
&clktree,
&reset_ctrl,
&analog_ctrl,
&pwr_ctrl,
&pad_ctrl,
&sys_ctrl,
&temp_sensor,
&am2axi_dev,
&spicc_b,
&spicc_a,
&msr,
&audio,
&jtag_ctrl,
&saradc_en,
&pwm_ef,
&pwm_cd,
&pwm_ab,
&cec,
&i2c_s,
&ir_ctrl,
&i2c_m_d,
&i2c_m_c,
&i2c_m_b,
&i2c_m_a,
&acodec,
&otp,
&sd_emmc_a,
&usb_phy,
&usb_ctrl,
&sys_dspb,
&sys_dspa,
&dma,
&irq_ctrl,
&nic,
&gic,
&uart_c,
&uart_b,
&uart_a,
&sys_psram,
&rsa,
&coresight,
&am2axi_vad,
&audio_vad,
&axi_dmc,
&axi_psram,
&ramb,
&rama,
&axi_spifc,
&axi_nic,
&axi_dma,
&cpu_ctrl,
&rom,
&prod_i2c,
&dspa_sel,
&dspb_sel,
&dspa_en,
&dspa_en_nic,
&dspb_en,
&dspb_en_nic,
&rtc,
&ceca_32k_out,
&cecb_32k_out,
&clk_24m,
&clk_12m,
&fclk_div2_divn,
&gen,
&saradc_sel,
&saradc,
&pwm_a,
&pwm_b,
&pwm_c,
&pwm_d,
&pwm_e,
&pwm_f,
&spicc,
&ts,
&spifc,
&usb_bus,
&sd_emmc,
&psram,
&dmc,
&sys_a_sel,
&sys_a_div,
&sys_a,
&sys_b_sel,
&sys_b_div,
&sys_b,
&dspa_a_sel,
&dspa_a_div,
&dspa_a,
&dspa_b_sel,
&dspa_b_div,
&dspa_b,
&dspb_a_sel,
&dspb_a_div,
&dspb_a,
&dspb_b_sel,
&dspb_b_div,
&dspb_b,
&rtc_32k_in,
&rtc_32k_div,
&rtc_32k_xtal,
&rtc_32k_sel,
&cecb_32k_in,
&cecb_32k_div,
&cecb_32k_sel_pre,
&cecb_32k_sel,
&ceca_32k_in,
&ceca_32k_div,
&ceca_32k_sel_pre,
&ceca_32k_sel,
&fclk_div2_divn_pre,
&gen_sel,
&gen_div,
&saradc_div,
&pwm_a_sel,
&pwm_a_div,
&pwm_b_sel,
&pwm_b_div,
&pwm_c_sel,
&pwm_c_div,
&pwm_d_sel,
&pwm_d_div,
&pwm_e_sel,
&pwm_e_div,
&pwm_f_sel,
&pwm_f_div,
&spicc_sel,
&spicc_div,
&spicc_sel2,
&ts_div,
&spifc_sel,
&spifc_div,
&spifc_sel2,
&usb_bus_sel,
&usb_bus_div,
&sd_emmc_sel,
&sd_emmc_div,
&sd_emmc_sel2,
&psram_sel,
&psram_div,
&psram_sel2,
&dmc_sel,
&dmc_div,
&dmc_sel2,
};
static const struct regmap_config a1_periphs_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
@@ -2200,7 +2072,7 @@ static int meson_a1_periphs_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
void __iomem *base;
struct regmap *map;
int clkid, i, err;
int clkid, err;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -2212,10 +2084,6 @@ static int meson_a1_periphs_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(map),
"can't init regmap mmio region\n");
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++)
a1_periphs_regmaps[i]->map = map;
for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) {
err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]);
if (err)

46
drivers/clk/meson/a1-peripherals.h
View File

@@ -1,46 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Amlogic A1 Peripherals Clock Controller internals
*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Author: Jian Hu <jian.hu@amlogic.com>
*
* Copyright (c) 2023, SberDevices. All Rights Reserved.
* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
*/
#ifndef __A1_PERIPHERALS_H
#define __A1_PERIPHERALS_H
/* peripherals clock controller register offset */
#define SYS_OSCIN_CTRL 0x0
#define RTC_BY_OSCIN_CTRL0 0x4
#define RTC_BY_OSCIN_CTRL1 0x8
#define RTC_CTRL 0xc
#define SYS_CLK_CTRL0 0x10
#define SYS_CLK_EN0 0x1c
#define SYS_CLK_EN1 0x20
#define AXI_CLK_EN 0x24
#define DSPA_CLK_EN 0x28
#define DSPB_CLK_EN 0x2c
#define DSPA_CLK_CTRL0 0x30
#define DSPB_CLK_CTRL0 0x34
#define CLK12_24_CTRL 0x38
#define GEN_CLK_CTRL 0x3c
#define SAR_ADC_CLK_CTRL 0xc0
#define PWM_CLK_AB_CTRL 0xc4
#define PWM_CLK_CD_CTRL 0xc8
#define PWM_CLK_EF_CTRL 0xcc
#define SPICC_CLK_CTRL 0xd0
#define TS_CLK_CTRL 0xd4
#define SPIFC_CLK_CTRL 0xd8
#define USB_BUSCLK_CTRL 0xdc
#define SD_EMMC_CLK_CTRL 0xe0
#define CECA_CLK_CTRL0 0xe4
#define CECA_CLK_CTRL1 0xe8
#define CECB_CLK_CTRL0 0xec
#define CECB_CLK_CTRL1 0xf0
#define PSRAM_CLK_CTRL 0xf4
#define DMC_CLK_CTRL 0xf8
#endif /* __A1_PERIPHERALS_H */

28
drivers/clk/meson/a1-pll.c
View File

@@ -10,10 +10,20 @@
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "a1-pll.h"
#include "clk-pll.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
#define ANACTRL_FIXPLL_CTRL0 0x0
#define ANACTRL_FIXPLL_CTRL1 0x4
#define ANACTRL_FIXPLL_STS 0x14
#define ANACTRL_HIFIPLL_CTRL0 0xc0
#define ANACTRL_HIFIPLL_CTRL1 0xc4
#define ANACTRL_HIFIPLL_CTRL2 0xc8
#define ANACTRL_HIFIPLL_CTRL3 0xcc
#define ANACTRL_HIFIPLL_CTRL4 0xd0
#define ANACTRL_HIFIPLL_STS 0xd4
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
static struct clk_regmap fixed_pll_dco = {
@@ -285,16 +295,6 @@ static struct clk_hw *a1_pll_hw_clks[] = {
[CLKID_HIFI_PLL] = &hifi_pll.hw,
};
static struct clk_regmap *const a1_pll_regmaps[] = {
&fixed_pll_dco,
&fixed_pll,
&fclk_div2,
&fclk_div3,
&fclk_div5,
&fclk_div7,
&hifi_pll,
};
static const struct regmap_config a1_pll_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
@@ -312,7 +312,7 @@ static int meson_a1_pll_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
void __iomem *base;
struct regmap *map;
int clkid, i, err;
int clkid, err;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -324,10 +324,6 @@ static int meson_a1_pll_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(map),
"can't init regmap mmio region\n");
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(a1_pll_regmaps); i++)
a1_pll_regmaps[i]->map = map;
/* Register clocks */
for (clkid = 0; clkid < a1_pll_clks.num; clkid++) {
err = devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]);

28
drivers/clk/meson/a1-pll.h
View File

@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Amlogic A1 PLL Clock Controller internals
*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
* Author: Jian Hu <jian.hu@amlogic.com>
*
* Copyright (c) 2023, SberDevices. All Rights Reserved.
* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
*/
#ifndef __A1_PLL_H
#define __A1_PLL_H
#include "clk-pll.h"
/* PLL register offset */
#define ANACTRL_FIXPLL_CTRL0 0x0
#define ANACTRL_FIXPLL_CTRL1 0x4
#define ANACTRL_FIXPLL_STS 0x14
#define ANACTRL_HIFIPLL_CTRL0 0xc0
#define ANACTRL_HIFIPLL_CTRL1 0xc4
#define ANACTRL_HIFIPLL_CTRL2 0xc8
#define ANACTRL_HIFIPLL_CTRL3 0xcc
#define ANACTRL_HIFIPLL_CTRL4 0xd0
#define ANACTRL_HIFIPLL_STS 0xd4
#endif /* __A1_PLL_H */

22
drivers/clk/meson/axg-aoclk.c
View File

@@ -270,26 +270,6 @@ static const unsigned int axg_aoclk_reset[] = {
[RESET_AO_IR_BLASTER] = 23,
};
static struct clk_regmap *axg_aoclk_regmap[] = {
&axg_aoclk_remote,
&axg_aoclk_i2c_master,
&axg_aoclk_i2c_slave,
&axg_aoclk_uart1,
&axg_aoclk_uart2,
&axg_aoclk_ir_blaster,
&axg_aoclk_saradc,
&axg_aoclk_cts_oscin,
&axg_aoclk_32k_pre,
&axg_aoclk_32k_div,
&axg_aoclk_32k_sel,
&axg_aoclk_32k,
&axg_aoclk_cts_rtc_oscin,
&axg_aoclk_clk81,
&axg_aoclk_saradc_mux,
&axg_aoclk_saradc_div,
&axg_aoclk_saradc_gate,
};
static struct clk_hw *axg_aoclk_hw_clks[] = {
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
@@ -314,8 +294,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(axg_aoclk_reset),
.reset = axg_aoclk_reset,
.num_clks = ARRAY_SIZE(axg_aoclk_regmap),
.clks = axg_aoclk_regmap,
.hw_clks = {
.hws = axg_aoclk_hw_clks,
.num = ARRAY_SIZE(axg_aoclk_hw_clks),

603
drivers/clk/meson/axg-audio.c
View File

@@ -4,6 +4,7 @@
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#include <linux/auxiliary_bus.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
@@ -12,17 +13,70 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "meson-clkc-utils.h"
#include "axg-audio.h"
#include "clk-regmap.h"
#include "clk-phase.h"
#include "sclk-div.h"
#include <dt-bindings/clock/axg-audio-clkc.h>
/* Audio clock register offsets */
#define AUDIO_CLK_GATE_EN 0x000
#define AUDIO_MCLK_A_CTRL 0x004
#define AUDIO_MCLK_B_CTRL 0x008
#define AUDIO_MCLK_C_CTRL 0x00C
#define AUDIO_MCLK_D_CTRL 0x010
#define AUDIO_MCLK_E_CTRL 0x014
#define AUDIO_MCLK_F_CTRL 0x018
#define AUDIO_MST_PAD_CTRL0 0x01c
#define AUDIO_MST_PAD_CTRL1 0x020
#define AUDIO_SW_RESET 0x024
#define AUDIO_MST_A_SCLK_CTRL0 0x040
#define AUDIO_MST_A_SCLK_CTRL1 0x044
#define AUDIO_MST_B_SCLK_CTRL0 0x048
#define AUDIO_MST_B_SCLK_CTRL1 0x04C
#define AUDIO_MST_C_SCLK_CTRL0 0x050
#define AUDIO_MST_C_SCLK_CTRL1 0x054
#define AUDIO_MST_D_SCLK_CTRL0 0x058
#define AUDIO_MST_D_SCLK_CTRL1 0x05C
#define AUDIO_MST_E_SCLK_CTRL0 0x060
#define AUDIO_MST_E_SCLK_CTRL1 0x064
#define AUDIO_MST_F_SCLK_CTRL0 0x068
#define AUDIO_MST_F_SCLK_CTRL1 0x06C
#define AUDIO_CLK_TDMIN_A_CTRL 0x080
#define AUDIO_CLK_TDMIN_B_CTRL 0x084
#define AUDIO_CLK_TDMIN_C_CTRL 0x088
#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
#define AUDIO_CLK_TDMOUT_A_CTRL 0x090
#define AUDIO_CLK_TDMOUT_B_CTRL 0x094
#define AUDIO_CLK_TDMOUT_C_CTRL 0x098
#define AUDIO_CLK_SPDIFIN_CTRL 0x09C
#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
#define AUDIO_CLK_LOCKER_CTRL 0x0A8
#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
/* SM1 introduce new register and some shifts :( */
#define AUDIO_CLK_GATE_EN1 0x004
#define AUDIO_SM1_MCLK_A_CTRL 0x008
#define AUDIO_SM1_MCLK_B_CTRL 0x00C
#define AUDIO_SM1_MCLK_C_CTRL 0x010
#define AUDIO_SM1_MCLK_D_CTRL 0x014
#define AUDIO_SM1_MCLK_E_CTRL 0x018
#define AUDIO_SM1_MCLK_F_CTRL 0x01C
#define AUDIO_SM1_MST_PAD_CTRL0 0x020
#define AUDIO_SM1_MST_PAD_CTRL1 0x024
#define AUDIO_SM1_SW_RESET0 0x028
#define AUDIO_SM1_SW_RESET1 0x02C
#define AUDIO_CLK81_CTRL 0x030
#define AUDIO_CLK81_EN 0x034
#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0
#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4
#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
.data = &(struct clk_regmap_gate_data){ \
.offset = (_reg), \
@@ -1257,505 +1311,6 @@ static struct clk_hw *sm1_audio_hw_clks[] = {
[AUD_CLKID_EARCRX_DMAC] = &sm1_earcrx_dmac_clk.hw,
};
/* Convenience table to populate regmap in .probe(). */
static struct clk_regmap *const axg_clk_regmaps[] = {
&ddr_arb,
&pdm,
&tdmin_a,
&tdmin_b,
&tdmin_c,
&tdmin_lb,
&tdmout_a,
&tdmout_b,
&tdmout_c,
&frddr_a,
&frddr_b,
&frddr_c,
&toddr_a,
&toddr_b,
&toddr_c,
&loopback,
&spdifin,
&spdifout,
&resample,
&power_detect,
&mst_a_mclk_sel,
&mst_b_mclk_sel,
&mst_c_mclk_sel,
&mst_d_mclk_sel,
&mst_e_mclk_sel,
&mst_f_mclk_sel,
&mst_a_mclk_div,
&mst_b_mclk_div,
&mst_c_mclk_div,
&mst_d_mclk_div,
&mst_e_mclk_div,
&mst_f_mclk_div,
&mst_a_mclk,
&mst_b_mclk,
&mst_c_mclk,
&mst_d_mclk,
&mst_e_mclk,
&mst_f_mclk,
&spdifout_clk_sel,
&spdifout_clk_div,
&spdifout_clk,
&spdifin_clk_sel,
&spdifin_clk_div,
&spdifin_clk,
&pdm_dclk_sel,
&pdm_dclk_div,
&pdm_dclk,
&pdm_sysclk_sel,
&pdm_sysclk_div,
&pdm_sysclk,
&mst_a_sclk_pre_en,
&mst_b_sclk_pre_en,
&mst_c_sclk_pre_en,
&mst_d_sclk_pre_en,
&mst_e_sclk_pre_en,
&mst_f_sclk_pre_en,
&mst_a_sclk_div,
&mst_b_sclk_div,
&mst_c_sclk_div,
&mst_d_sclk_div,
&mst_e_sclk_div,
&mst_f_sclk_div,
&mst_a_sclk_post_en,
&mst_b_sclk_post_en,
&mst_c_sclk_post_en,
&mst_d_sclk_post_en,
&mst_e_sclk_post_en,
&mst_f_sclk_post_en,
&mst_a_sclk,
&mst_b_sclk,
&mst_c_sclk,
&mst_d_sclk,
&mst_e_sclk,
&mst_f_sclk,
&mst_a_lrclk_div,
&mst_b_lrclk_div,
&mst_c_lrclk_div,
&mst_d_lrclk_div,
&mst_e_lrclk_div,
&mst_f_lrclk_div,
&mst_a_lrclk,
&mst_b_lrclk,
&mst_c_lrclk,
&mst_d_lrclk,
&mst_e_lrclk,
&mst_f_lrclk,
&tdmin_a_sclk_sel,
&tdmin_b_sclk_sel,
&tdmin_c_sclk_sel,
&tdmin_lb_sclk_sel,
&tdmout_a_sclk_sel,
&tdmout_b_sclk_sel,
&tdmout_c_sclk_sel,
&tdmin_a_sclk_pre_en,
&tdmin_b_sclk_pre_en,
&tdmin_c_sclk_pre_en,
&tdmin_lb_sclk_pre_en,
&tdmout_a_sclk_pre_en,
&tdmout_b_sclk_pre_en,
&tdmout_c_sclk_pre_en,
&tdmin_a_sclk_post_en,
&tdmin_b_sclk_post_en,
&tdmin_c_sclk_post_en,
&tdmin_lb_sclk_post_en,
&tdmout_a_sclk_post_en,
&tdmout_b_sclk_post_en,
&tdmout_c_sclk_post_en,
&tdmin_a_sclk,
&tdmin_b_sclk,
&tdmin_c_sclk,
&tdmin_lb_sclk,
&axg_tdmout_a_sclk,
&axg_tdmout_b_sclk,
&axg_tdmout_c_sclk,
&tdmin_a_lrclk,
&tdmin_b_lrclk,
&tdmin_c_lrclk,
&tdmin_lb_lrclk,
&tdmout_a_lrclk,
&tdmout_b_lrclk,
&tdmout_c_lrclk,
};
static struct clk_regmap *const g12a_clk_regmaps[] = {
&ddr_arb,
&pdm,
&tdmin_a,
&tdmin_b,
&tdmin_c,
&tdmin_lb,
&tdmout_a,
&tdmout_b,
&tdmout_c,
&frddr_a,
&frddr_b,
&frddr_c,
&toddr_a,
&toddr_b,
&toddr_c,
&loopback,
&spdifin,
&spdifout,
&resample,
&power_detect,
&spdifout_b,
&mst_a_mclk_sel,
&mst_b_mclk_sel,
&mst_c_mclk_sel,
&mst_d_mclk_sel,
&mst_e_mclk_sel,
&mst_f_mclk_sel,
&mst_a_mclk_div,
&mst_b_mclk_div,
&mst_c_mclk_div,
&mst_d_mclk_div,
&mst_e_mclk_div,
&mst_f_mclk_div,
&mst_a_mclk,
&mst_b_mclk,
&mst_c_mclk,
&mst_d_mclk,
&mst_e_mclk,
&mst_f_mclk,
&spdifout_clk_sel,
&spdifout_clk_div,
&spdifout_clk,
&spdifin_clk_sel,
&spdifin_clk_div,
&spdifin_clk,
&pdm_dclk_sel,
&pdm_dclk_div,
&pdm_dclk,
&pdm_sysclk_sel,
&pdm_sysclk_div,
&pdm_sysclk,
&mst_a_sclk_pre_en,
&mst_b_sclk_pre_en,
&mst_c_sclk_pre_en,
&mst_d_sclk_pre_en,
&mst_e_sclk_pre_en,
&mst_f_sclk_pre_en,
&mst_a_sclk_div,
&mst_b_sclk_div,
&mst_c_sclk_div,
&mst_d_sclk_div,
&mst_e_sclk_div,
&mst_f_sclk_div,
&mst_a_sclk_post_en,
&mst_b_sclk_post_en,
&mst_c_sclk_post_en,
&mst_d_sclk_post_en,
&mst_e_sclk_post_en,
&mst_f_sclk_post_en,
&mst_a_sclk,
&mst_b_sclk,
&mst_c_sclk,
&mst_d_sclk,
&mst_e_sclk,
&mst_f_sclk,
&mst_a_lrclk_div,
&mst_b_lrclk_div,
&mst_c_lrclk_div,
&mst_d_lrclk_div,
&mst_e_lrclk_div,
&mst_f_lrclk_div,
&mst_a_lrclk,
&mst_b_lrclk,
&mst_c_lrclk,
&mst_d_lrclk,
&mst_e_lrclk,
&mst_f_lrclk,
&tdmin_a_sclk_sel,
&tdmin_b_sclk_sel,
&tdmin_c_sclk_sel,
&tdmin_lb_sclk_sel,
&tdmout_a_sclk_sel,
&tdmout_b_sclk_sel,
&tdmout_c_sclk_sel,
&tdmin_a_sclk_pre_en,
&tdmin_b_sclk_pre_en,
&tdmin_c_sclk_pre_en,
&tdmin_lb_sclk_pre_en,
&tdmout_a_sclk_pre_en,
&tdmout_b_sclk_pre_en,
&tdmout_c_sclk_pre_en,
&tdmin_a_sclk_post_en,
&tdmin_b_sclk_post_en,
&tdmin_c_sclk_post_en,
&tdmin_lb_sclk_post_en,
&tdmout_a_sclk_post_en,
&tdmout_b_sclk_post_en,
&tdmout_c_sclk_post_en,
&tdmin_a_sclk,
&tdmin_b_sclk,
&tdmin_c_sclk,
&tdmin_lb_sclk,
&g12a_tdmout_a_sclk,
&g12a_tdmout_b_sclk,
&g12a_tdmout_c_sclk,
&tdmin_a_lrclk,
&tdmin_b_lrclk,
&tdmin_c_lrclk,
&tdmin_lb_lrclk,
&tdmout_a_lrclk,
&tdmout_b_lrclk,
&tdmout_c_lrclk,
&spdifout_b_clk_sel,
&spdifout_b_clk_div,
&spdifout_b_clk,
&g12a_tdm_mclk_pad_0,
&g12a_tdm_mclk_pad_1,
&g12a_tdm_lrclk_pad_0,
&g12a_tdm_lrclk_pad_1,
&g12a_tdm_lrclk_pad_2,
&g12a_tdm_sclk_pad_0,
&g12a_tdm_sclk_pad_1,
&g12a_tdm_sclk_pad_2,
&toram,
&eqdrc,
};
static struct clk_regmap *const sm1_clk_regmaps[] = {
&ddr_arb,
&pdm,
&tdmin_a,
&tdmin_b,
&tdmin_c,
&tdmin_lb,
&tdmout_a,
&tdmout_b,
&tdmout_c,
&frddr_a,
&frddr_b,
&frddr_c,
&toddr_a,
&toddr_b,
&toddr_c,
&loopback,
&spdifin,
&spdifout,
&resample,
&spdifout_b,
&sm1_mst_a_mclk_sel,
&sm1_mst_b_mclk_sel,
&sm1_mst_c_mclk_sel,
&sm1_mst_d_mclk_sel,
&sm1_mst_e_mclk_sel,
&sm1_mst_f_mclk_sel,
&sm1_mst_a_mclk_div,
&sm1_mst_b_mclk_div,
&sm1_mst_c_mclk_div,
&sm1_mst_d_mclk_div,
&sm1_mst_e_mclk_div,
&sm1_mst_f_mclk_div,
&sm1_mst_a_mclk,
&sm1_mst_b_mclk,
&sm1_mst_c_mclk,
&sm1_mst_d_mclk,
&sm1_mst_e_mclk,
&sm1_mst_f_mclk,
&spdifout_clk_sel,
&spdifout_clk_div,
&spdifout_clk,
&spdifin_clk_sel,
&spdifin_clk_div,
&spdifin_clk,
&pdm_dclk_sel,
&pdm_dclk_div,
&pdm_dclk,
&pdm_sysclk_sel,
&pdm_sysclk_div,
&pdm_sysclk,
&mst_a_sclk_pre_en,
&mst_b_sclk_pre_en,
&mst_c_sclk_pre_en,
&mst_d_sclk_pre_en,
&mst_e_sclk_pre_en,
&mst_f_sclk_pre_en,
&mst_a_sclk_div,
&mst_b_sclk_div,
&mst_c_sclk_div,
&mst_d_sclk_div,
&mst_e_sclk_div,
&mst_f_sclk_div,
&mst_a_sclk_post_en,
&mst_b_sclk_post_en,
&mst_c_sclk_post_en,
&mst_d_sclk_post_en,
&mst_e_sclk_post_en,
&mst_f_sclk_post_en,
&mst_a_sclk,
&mst_b_sclk,
&mst_c_sclk,
&mst_d_sclk,
&mst_e_sclk,
&mst_f_sclk,
&mst_a_lrclk_div,
&mst_b_lrclk_div,
&mst_c_lrclk_div,
&mst_d_lrclk_div,
&mst_e_lrclk_div,
&mst_f_lrclk_div,
&mst_a_lrclk,
&mst_b_lrclk,
&mst_c_lrclk,
&mst_d_lrclk,
&mst_e_lrclk,
&mst_f_lrclk,
&tdmin_a_sclk_sel,
&tdmin_b_sclk_sel,
&tdmin_c_sclk_sel,
&tdmin_lb_sclk_sel,
&tdmout_a_sclk_sel,
&tdmout_b_sclk_sel,
&tdmout_c_sclk_sel,
&tdmin_a_sclk_pre_en,
&tdmin_b_sclk_pre_en,
&tdmin_c_sclk_pre_en,
&tdmin_lb_sclk_pre_en,
&tdmout_a_sclk_pre_en,
&tdmout_b_sclk_pre_en,
&tdmout_c_sclk_pre_en,
&tdmin_a_sclk_post_en,
&tdmin_b_sclk_post_en,
&tdmin_c_sclk_post_en,
&tdmin_lb_sclk_post_en,
&tdmout_a_sclk_post_en,
&tdmout_b_sclk_post_en,
&tdmout_c_sclk_post_en,
&tdmin_a_sclk,
&tdmin_b_sclk,
&tdmin_c_sclk,
&tdmin_lb_sclk,
&g12a_tdmout_a_sclk,
&g12a_tdmout_b_sclk,
&g12a_tdmout_c_sclk,
&tdmin_a_lrclk,
&tdmin_b_lrclk,
&tdmin_c_lrclk,
&tdmin_lb_lrclk,
&tdmout_a_lrclk,
&tdmout_b_lrclk,
&tdmout_c_lrclk,
&spdifout_b_clk_sel,
&spdifout_b_clk_div,
&spdifout_b_clk,
&sm1_tdm_mclk_pad_0,
&sm1_tdm_mclk_pad_1,
&sm1_tdm_lrclk_pad_0,
&sm1_tdm_lrclk_pad_1,
&sm1_tdm_lrclk_pad_2,
&sm1_tdm_sclk_pad_0,
&sm1_tdm_sclk_pad_1,
&sm1_tdm_sclk_pad_2,
&sm1_aud_top,
&toram,
&eqdrc,
&resample_b,
&tovad,
&locker,
&spdifin_lb,
&frddr_d,
&toddr_d,
&loopback_b,
&sm1_clk81_en,
&sm1_sysclk_a_div,
&sm1_sysclk_a_en,
&sm1_sysclk_b_div,
&sm1_sysclk_b_en,
&earcrx,
&sm1_earcrx_cmdc_clk_sel,
&sm1_earcrx_cmdc_clk_div,
&sm1_earcrx_cmdc_clk,
&sm1_earcrx_dmac_clk_sel,
&sm1_earcrx_dmac_clk_div,
&sm1_earcrx_dmac_clk,
};
struct axg_audio_reset_data {
struct reset_controller_dev rstc;
struct regmap *map;
unsigned int offset;
};
static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
unsigned long id,
unsigned int *reg,
unsigned int *bit)
{
unsigned int stride = regmap_get_reg_stride(rst->map);
*reg = (id / (stride * BITS_PER_BYTE)) * stride;
*reg += rst->offset;
*bit = id % (stride * BITS_PER_BYTE);
}
static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct axg_audio_reset_data *rst =
container_of(rcdev, struct axg_audio_reset_data, rstc);
unsigned int offset, bit;
axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
regmap_update_bits(rst->map, offset, BIT(bit),
assert ? BIT(bit) : 0);
return 0;
}
static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct axg_audio_reset_data *rst =
container_of(rcdev, struct axg_audio_reset_data, rstc);
unsigned int val, offset, bit;
axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
regmap_read(rst->map, offset, &val);
return !!(val & BIT(bit));
}
static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return axg_audio_reset_update(rcdev, id, true);
}
static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return axg_audio_reset_update(rcdev, id, false);
}
static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
ret = axg_audio_reset_assert(rcdev, id);
if (ret)
return ret;
return axg_audio_reset_deassert(rcdev, id);
}
static const struct reset_control_ops axg_audio_rstc_ops = {
.assert = axg_audio_reset_assert,
.deassert = axg_audio_reset_deassert,
.reset = axg_audio_reset_toggle,
.status = axg_audio_reset_status,
};
static struct regmap_config axg_audio_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
@@ -1763,11 +1318,8 @@ static struct regmap_config axg_audio_regmap_cfg = {
};
struct audioclk_data {
struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num;
struct meson_clk_hw_data hw_clks;
unsigned int reset_offset;
unsigned int reset_num;
const char *rst_drvname;
unsigned int max_register;
};
@@ -1775,7 +1327,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct audioclk_data *data;
struct axg_audio_reset_data *rst;
struct auxiliary_device *auxdev;
struct regmap *map;
void __iomem *regs;
struct clk_hw *hw;
@@ -1808,10 +1360,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
return ret;
}
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < data->regmap_clk_num; i++)
data->regmap_clks[i]->map = map;
/* Take care to skip the registered input clocks */
for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
const char *name;
@@ -1834,27 +1382,18 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
if (ret)
return ret;
/* Stop here if there is no reset */
if (!data->reset_num)
return 0;
/* Register auxiliary reset driver when applicable */
if (data->rst_drvname) {
auxdev = __devm_auxiliary_device_create(dev, dev->driver->name,
data->rst_drvname, NULL, 0);
if (!auxdev)
return -ENODEV;
}
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
if (!rst)
return -ENOMEM;
rst->map = map;
rst->offset = data->reset_offset;
rst->rstc.nr_resets = data->reset_num;
rst->rstc.ops = &axg_audio_rstc_ops;
rst->rstc.of_node = dev->of_node;
rst->rstc.owner = THIS_MODULE;
return devm_reset_controller_register(dev, &rst->rstc);
return 0;
}
static const struct audioclk_data axg_audioclk_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
.hw_clks = {
.hws = axg_audio_hw_clks,
.num = ARRAY_SIZE(axg_audio_hw_clks),
@@ -1863,26 +1402,20 @@ static const struct audioclk_data axg_audioclk_data = {
};
static const struct audioclk_data g12a_audioclk_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_clks = {
.hws = g12a_audio_hw_clks,
.num = ARRAY_SIZE(g12a_audio_hw_clks),
},
.reset_offset = AUDIO_SW_RESET,
.reset_num = 26,
.rst_drvname = "rst-g12a",
.max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
};
static const struct audioclk_data sm1_audioclk_data = {
.regmap_clks = sm1_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
.hw_clks = {
.hws = sm1_audio_hw_clks,
.num = ARRAY_SIZE(sm1_audio_hw_clks),
},
.reset_offset = AUDIO_SM1_SW_RESET0,
.reset_num = 39,
.rst_drvname = "rst-sm1",
.max_register = AUDIO_EARCRX_DMAC_CLK_CTRL,
};

70
drivers/clk/meson/axg-audio.h
View File

@@ -1,70 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (c) 2018 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __AXG_AUDIO_CLKC_H
#define __AXG_AUDIO_CLKC_H
/*
* Audio Clock register offsets
*
* Register offsets from the datasheet must be multiplied by 4 before
* to get the right offset
*/
#define AUDIO_CLK_GATE_EN 0x000
#define AUDIO_MCLK_A_CTRL 0x004
#define AUDIO_MCLK_B_CTRL 0x008
#define AUDIO_MCLK_C_CTRL 0x00C
#define AUDIO_MCLK_D_CTRL 0x010
#define AUDIO_MCLK_E_CTRL 0x014
#define AUDIO_MCLK_F_CTRL 0x018
#define AUDIO_MST_PAD_CTRL0 0x01c
#define AUDIO_MST_PAD_CTRL1 0x020
#define AUDIO_SW_RESET 0x024
#define AUDIO_MST_A_SCLK_CTRL0 0x040
#define AUDIO_MST_A_SCLK_CTRL1 0x044
#define AUDIO_MST_B_SCLK_CTRL0 0x048
#define AUDIO_MST_B_SCLK_CTRL1 0x04C
#define AUDIO_MST_C_SCLK_CTRL0 0x050
#define AUDIO_MST_C_SCLK_CTRL1 0x054
#define AUDIO_MST_D_SCLK_CTRL0 0x058
#define AUDIO_MST_D_SCLK_CTRL1 0x05C
#define AUDIO_MST_E_SCLK_CTRL0 0x060
#define AUDIO_MST_E_SCLK_CTRL1 0x064
#define AUDIO_MST_F_SCLK_CTRL0 0x068
#define AUDIO_MST_F_SCLK_CTRL1 0x06C
#define AUDIO_CLK_TDMIN_A_CTRL 0x080
#define AUDIO_CLK_TDMIN_B_CTRL 0x084
#define AUDIO_CLK_TDMIN_C_CTRL 0x088
#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
#define AUDIO_CLK_TDMOUT_A_CTRL 0x090
#define AUDIO_CLK_TDMOUT_B_CTRL 0x094
#define AUDIO_CLK_TDMOUT_C_CTRL 0x098
#define AUDIO_CLK_SPDIFIN_CTRL 0x09C
#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
#define AUDIO_CLK_LOCKER_CTRL 0x0A8
#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
/* SM1 introduce new register and some shifts :( */
#define AUDIO_CLK_GATE_EN1 0x004
#define AUDIO_SM1_MCLK_A_CTRL 0x008
#define AUDIO_SM1_MCLK_B_CTRL 0x00C
#define AUDIO_SM1_MCLK_C_CTRL 0x010
#define AUDIO_SM1_MCLK_D_CTRL 0x014
#define AUDIO_SM1_MCLK_E_CTRL 0x018
#define AUDIO_SM1_MCLK_F_CTRL 0x01C
#define AUDIO_SM1_MST_PAD_CTRL0 0x020
#define AUDIO_SM1_MST_PAD_CTRL1 0x024
#define AUDIO_SM1_SW_RESET0 0x028
#define AUDIO_SM1_SW_RESET1 0x02C
#define AUDIO_CLK81_CTRL 0x030
#define AUDIO_CLK81_EN 0x034
#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0
#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4
#endif /*__AXG_AUDIO_CLKC_H */

218
drivers/clk/meson/axg.c
View File

@@ -18,11 +18,96 @@
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-mpll.h"
#include "axg.h"
#include "meson-eeclk.h"
#include <dt-bindings/clock/axg-clkc.h>
#define HHI_GP0_PLL_CNTL 0x40
#define HHI_GP0_PLL_CNTL2 0x44
#define HHI_GP0_PLL_CNTL3 0x48
#define HHI_GP0_PLL_CNTL4 0x4c
#define HHI_GP0_PLL_CNTL5 0x50
#define HHI_GP0_PLL_STS 0x54
#define HHI_GP0_PLL_CNTL1 0x58
#define HHI_HIFI_PLL_CNTL 0x80
#define HHI_HIFI_PLL_CNTL2 0x84
#define HHI_HIFI_PLL_CNTL3 0x88
#define HHI_HIFI_PLL_CNTL4 0x8C
#define HHI_HIFI_PLL_CNTL5 0x90
#define HHI_HIFI_PLL_STS 0x94
#define HHI_HIFI_PLL_CNTL1 0x98
#define HHI_XTAL_DIVN_CNTL 0xbc
#define HHI_GCLK2_MPEG0 0xc0
#define HHI_GCLK2_MPEG1 0xc4
#define HHI_GCLK2_MPEG2 0xc8
#define HHI_GCLK2_OTHER 0xd0
#define HHI_GCLK2_AO 0xd4
#define HHI_PCIE_PLL_CNTL 0xd8
#define HHI_PCIE_PLL_CNTL1 0xdC
#define HHI_PCIE_PLL_CNTL2 0xe0
#define HHI_PCIE_PLL_CNTL3 0xe4
#define HHI_PCIE_PLL_CNTL4 0xe8
#define HHI_PCIE_PLL_CNTL5 0xec
#define HHI_PCIE_PLL_CNTL6 0xf0
#define HHI_PCIE_PLL_STS 0xf4
#define HHI_MEM_PD_REG0 0x100
#define HHI_VPU_MEM_PD_REG0 0x104
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12c
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_AO 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_SYS_CPU_RESET_CNTL 0x160
#define HHI_VID_CLK_DIV 0x164
#define HHI_SPICC_HCLK_CNTL 0x168
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1a0
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_VAPBCLK_CNTL 0x1F4
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_NAND_CLK_CNTL 0x25C
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL 0x280
#define HHI_MPLL_CNTL2 0x284
#define HHI_MPLL_CNTL3 0x288
#define HHI_MPLL_CNTL4 0x28C
#define HHI_MPLL_CNTL5 0x290
#define HHI_MPLL_CNTL6 0x294
#define HHI_MPLL_CNTL7 0x298
#define HHI_MPLL_CNTL8 0x29C
#define HHI_MPLL_CNTL9 0x2A0
#define HHI_MPLL_CNTL10 0x2A4
#define HHI_MPLL3_CNTL0 0x2E0
#define HHI_MPLL3_CNTL1 0x2E4
#define HHI_PLL_TOP_MISC 0x2E8
#define HHI_SYS_PLL_CNTL1 0x2FC
#define HHI_SYS_PLL_CNTL 0x300
#define HHI_SYS_PLL_CNTL2 0x304
#define HHI_SYS_PLL_CNTL3 0x308
#define HHI_SYS_PLL_CNTL4 0x30c
#define HHI_SYS_PLL_CNTL5 0x310
#define HHI_SYS_PLL_STS 0x314
#define HHI_DPLL_TOP_I 0x318
#define HHI_DPLL_TOP2_I 0x31C
static struct clk_regmap axg_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@@ -2025,138 +2110,7 @@ static struct clk_hw *axg_hw_clks[] = {
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
};
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_clk81,
&axg_ddr,
&axg_audio_locker,
&axg_mipi_dsi_host,
&axg_isa,
&axg_pl301,
&axg_periphs,
&axg_spicc_0,
&axg_i2c,
&axg_rng0,
&axg_uart0,
&axg_mipi_dsi_phy,
&axg_spicc_1,
&axg_pcie_a,
&axg_pcie_b,
&axg_hiu_reg,
&axg_assist_misc,
&axg_emmc_b,
&axg_emmc_c,
&axg_dma,
&axg_spi,
&axg_audio,
&axg_eth_core,
&axg_uart1,
&axg_g2d,
&axg_usb0,
&axg_usb1,
&axg_reset,
&axg_usb_general,
&axg_ahb_arb0,
&axg_efuse,
&axg_boot_rom,
&axg_ahb_data_bus,
&axg_ahb_ctrl_bus,
&axg_usb1_to_ddr,
&axg_usb0_to_ddr,
&axg_mmc_pclk,
&axg_vpu_intr,
&axg_sec_ahb_ahb3_bridge,
&axg_gic,
&axg_ao_media_cpu,
&axg_ao_ahb_sram,
&axg_ao_ahb_bus,
&axg_ao_iface,
&axg_ao_i2c,
&axg_sd_emmc_b_clk0,
&axg_sd_emmc_c_clk0,
&axg_mpeg_clk_div,
&axg_sd_emmc_b_clk0_div,
&axg_sd_emmc_c_clk0_div,
&axg_mpeg_clk_sel,
&axg_sd_emmc_b_clk0_sel,
&axg_sd_emmc_c_clk0_sel,
&axg_mpll0,
&axg_mpll1,
&axg_mpll2,
&axg_mpll3,
&axg_mpll0_div,
&axg_mpll1_div,
&axg_mpll2_div,
&axg_mpll3_div,
&axg_fixed_pll,
&axg_sys_pll,
&axg_gp0_pll,
&axg_hifi_pll,
&axg_mpll_prediv,
&axg_fclk_div2,
&axg_fclk_div3,
&axg_fclk_div4,
&axg_fclk_div5,
&axg_fclk_div7,
&axg_pcie_pll_dco,
&axg_pcie_pll_od,
&axg_pcie_pll,
&axg_pcie_mux,
&axg_pcie_ref,
&axg_pcie_cml_en0,
&axg_pcie_cml_en1,
&axg_gen_clk_sel,
&axg_gen_clk_div,
&axg_gen_clk,
&axg_fixed_pll_dco,
&axg_sys_pll_dco,
&axg_gp0_pll_dco,
&axg_hifi_pll_dco,
&axg_pcie_pll_dco,
&axg_pcie_pll_od,
&axg_vpu_0_div,
&axg_vpu_0_sel,
&axg_vpu_0,
&axg_vpu_1_div,
&axg_vpu_1_sel,
&axg_vpu_1,
&axg_vpu,
&axg_vapb_0_div,
&axg_vapb_0_sel,
&axg_vapb_0,
&axg_vapb_1_div,
&axg_vapb_1_sel,
&axg_vapb_1,
&axg_vapb_sel,
&axg_vapb,
&axg_vclk,
&axg_vclk2,
&axg_vclk_sel,
&axg_vclk2_sel,
&axg_vclk_input,
&axg_vclk2_input,
&axg_vclk_div,
&axg_vclk_div1,
&axg_vclk2_div,
&axg_vclk2_div1,
&axg_vclk_div2_en,
&axg_vclk_div4_en,
&axg_vclk_div6_en,
&axg_vclk_div12_en,
&axg_vclk2_div2_en,
&axg_vclk2_div4_en,
&axg_vclk2_div6_en,
&axg_vclk2_div12_en,
&axg_cts_encl_sel,
&axg_cts_encl,
&axg_vdin_meas_sel,
&axg_vdin_meas_div,
&axg_vdin_meas,
};
static const struct meson_eeclkc_data axg_clkc_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
.hw_clks = {
.hws = axg_hw_clks,
.num = ARRAY_SIZE(axg_hw_clks),

105
drivers/clk/meson/axg.h
View File

@@ -1,105 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2016 AmLogic, Inc.
* Author: Michael Turquette <mturquette@baylibre.com>
*
* Copyright (c) 2017 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
*
*/
#ifndef __AXG_H
#define __AXG_H
/*
* Clock controller register offsets
*
* Register offsets from the data sheet must be multiplied by 4 before
* adding them to the base address to get the right value.
*/
#define HHI_GP0_PLL_CNTL 0x40
#define HHI_GP0_PLL_CNTL2 0x44
#define HHI_GP0_PLL_CNTL3 0x48
#define HHI_GP0_PLL_CNTL4 0x4c
#define HHI_GP0_PLL_CNTL5 0x50
#define HHI_GP0_PLL_STS 0x54
#define HHI_GP0_PLL_CNTL1 0x58
#define HHI_HIFI_PLL_CNTL 0x80
#define HHI_HIFI_PLL_CNTL2 0x84
#define HHI_HIFI_PLL_CNTL3 0x88
#define HHI_HIFI_PLL_CNTL4 0x8C
#define HHI_HIFI_PLL_CNTL5 0x90
#define HHI_HIFI_PLL_STS 0x94
#define HHI_HIFI_PLL_CNTL1 0x98
#define HHI_XTAL_DIVN_CNTL 0xbc
#define HHI_GCLK2_MPEG0 0xc0
#define HHI_GCLK2_MPEG1 0xc4
#define HHI_GCLK2_MPEG2 0xc8
#define HHI_GCLK2_OTHER 0xd0
#define HHI_GCLK2_AO 0xd4
#define HHI_PCIE_PLL_CNTL 0xd8
#define HHI_PCIE_PLL_CNTL1 0xdC
#define HHI_PCIE_PLL_CNTL2 0xe0
#define HHI_PCIE_PLL_CNTL3 0xe4
#define HHI_PCIE_PLL_CNTL4 0xe8
#define HHI_PCIE_PLL_CNTL5 0xec
#define HHI_PCIE_PLL_CNTL6 0xf0
#define HHI_PCIE_PLL_STS 0xf4
#define HHI_MEM_PD_REG0 0x100
#define HHI_VPU_MEM_PD_REG0 0x104
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12c
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_AO 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_SYS_CPU_RESET_CNTL 0x160
#define HHI_VID_CLK_DIV 0x164
#define HHI_SPICC_HCLK_CNTL 0x168
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1a0
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_VAPBCLK_CNTL 0x1F4
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_NAND_CLK_CNTL 0x25C
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL 0x280
#define HHI_MPLL_CNTL2 0x284
#define HHI_MPLL_CNTL3 0x288
#define HHI_MPLL_CNTL4 0x28C
#define HHI_MPLL_CNTL5 0x290
#define HHI_MPLL_CNTL6 0x294
#define HHI_MPLL_CNTL7 0x298
#define HHI_MPLL_CNTL8 0x29C
#define HHI_MPLL_CNTL9 0x2A0
#define HHI_MPLL_CNTL10 0x2A4
#define HHI_MPLL3_CNTL0 0x2E0
#define HHI_MPLL3_CNTL1 0x2E4
#define HHI_PLL_TOP_MISC 0x2E8
#define HHI_SYS_PLL_CNTL1 0x2FC
#define HHI_SYS_PLL_CNTL 0x300
#define HHI_SYS_PLL_CNTL2 0x304
#define HHI_SYS_PLL_CNTL3 0x308
#define HHI_SYS_PLL_CNTL4 0x30c
#define HHI_SYS_PLL_CNTL5 0x310
#define HHI_SYS_PLL_STS 0x314
#define HHI_DPLL_TOP_I 0x318
#define HHI_DPLL_TOP2_I 0x31C
#endif /* __AXG_H */

210
drivers/clk/meson/c3-peripherals.c
View File

@@ -2092,210 +2092,6 @@ static struct clk_hw *c3_periphs_hw_clks[] = {
[CLKID_VAPB] = &vapb.hw,
};
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const c3_periphs_clk_regmaps[] = {
&rtc_xtal_clkin,
&rtc_32k_div,
&rtc_32k_mux,
&rtc_32k,
&rtc_clk,
&sys_reset_ctrl,
&sys_pwr_ctrl,
&sys_pad_ctrl,
&sys_ctrl,
&sys_ts_pll,
&sys_dev_arb,
&sys_mmc_pclk,
&sys_cpu_ctrl,
&sys_jtag_ctrl,
&sys_ir_ctrl,
&sys_irq_ctrl,
&sys_msr_clk,
&sys_rom,
&sys_uart_f,
&sys_cpu_apb,
&sys_rsa,
&sys_sar_adc,
&sys_startup,
&sys_secure,
&sys_spifc,
&sys_nna,
&sys_eth_mac,
&sys_gic,
&sys_rama,
&sys_big_nic,
&sys_ramb,
&sys_audio_pclk,
&sys_pwm_kl,
&sys_pwm_ij,
&sys_usb,
&sys_sd_emmc_a,
&sys_sd_emmc_c,
&sys_pwm_ab,
&sys_pwm_cd,
&sys_pwm_ef,
&sys_pwm_gh,
&sys_spicc_1,
&sys_spicc_0,
&sys_uart_a,
&sys_uart_b,
&sys_uart_c,
&sys_uart_d,
&sys_uart_e,
&sys_i2c_m_a,
&sys_i2c_m_b,
&sys_i2c_m_c,
&sys_i2c_m_d,
&sys_i2c_s_a,
&sys_rtc,
&sys_ge2d,
&sys_isp,
&sys_gpv_isp_nic,
&sys_gpv_cve_nic,
&sys_mipi_dsi_host,
&sys_mipi_dsi_phy,
&sys_eth_phy,
&sys_acodec,
&sys_dwap,
&sys_dos,
&sys_cve,
&sys_vout,
&sys_vc9000e,
&sys_pwm_mn,
&sys_sd_emmc_b,
&axi_sys_nic,
&axi_isp_nic,
&axi_cve_nic,
&axi_ramb,
&axi_rama,
&axi_cpu_dmc,
&axi_nic,
&axi_dma,
&axi_mux_nic,
&axi_cve,
&axi_dev1_dmc,
&axi_dev0_dmc,
&axi_dsp_dmc,
&clk_12_24m_in,
&clk_12_24m,
&fclk_25m_div,
&fclk_25m,
&gen_sel,
&gen_div,
&gen,
&saradc_sel,
&saradc_div,
&saradc,
&pwm_a_sel,
&pwm_a_div,
&pwm_a,
&pwm_b_sel,
&pwm_b_div,
&pwm_b,
&pwm_c_sel,
&pwm_c_div,
&pwm_c,
&pwm_d_sel,
&pwm_d_div,
&pwm_d,
&pwm_e_sel,
&pwm_e_div,
&pwm_e,
&pwm_f_sel,
&pwm_f_div,
&pwm_f,
&pwm_g_sel,
&pwm_g_div,
&pwm_g,
&pwm_h_sel,
&pwm_h_div,
&pwm_h,
&pwm_i_sel,
&pwm_i_div,
&pwm_i,
&pwm_j_sel,
&pwm_j_div,
&pwm_j,
&pwm_k_sel,
&pwm_k_div,
&pwm_k,
&pwm_l_sel,
&pwm_l_div,
&pwm_l,
&pwm_m_sel,
&pwm_m_div,
&pwm_m,
&pwm_n_sel,
&pwm_n_div,
&pwm_n,
&spicc_a_sel,
&spicc_a_div,
&spicc_a,
&spicc_b_sel,
&spicc_b_div,
&spicc_b,
&spifc_sel,
&spifc_div,
&spifc,
&sd_emmc_a_sel,
&sd_emmc_a_div,
&sd_emmc_a,
&sd_emmc_b_sel,
&sd_emmc_b_div,
&sd_emmc_b,
&sd_emmc_c_sel,
&sd_emmc_c_div,
&sd_emmc_c,
&ts_div,
&ts,
&eth_125m,
&eth_rmii_div,
&eth_rmii,
&mipi_dsi_meas_sel,
&mipi_dsi_meas_div,
&mipi_dsi_meas,
&dsi_phy_sel,
&dsi_phy_div,
&dsi_phy,
&vout_mclk_sel,
&vout_mclk_div,
&vout_mclk,
&vout_enc_sel,
&vout_enc_div,
&vout_enc,
&hcodec_0_sel,
&hcodec_0_div,
&hcodec_0,
&hcodec_1_sel,
&hcodec_1_div,
&hcodec_1,
&hcodec,
&vc9000e_aclk_sel,
&vc9000e_aclk_div,
&vc9000e_aclk,
&vc9000e_core_sel,
&vc9000e_core_div,
&vc9000e_core,
&csi_phy0_sel,
&csi_phy0_div,
&csi_phy0,
&dewarpa_sel,
&dewarpa_div,
&dewarpa,
&isp0_sel,
&isp0_div,
&isp0,
&nna_core_sel,
&nna_core_div,
&nna_core,
&ge2d_sel,
&ge2d_div,
&ge2d,
&vapb_sel,
&vapb_div,
&vapb,
};
static const struct regmap_config clkc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -2313,7 +2109,7 @@ static int c3_peripherals_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
int clkid, ret, i;
int clkid, ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -2323,10 +2119,6 @@ static int c3_peripherals_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(c3_periphs_clk_regmaps); i++)
c3_periphs_clk_regmaps[i]->map = regmap;
for (clkid = 0; clkid < c3_periphs_clks.num; clkid++) {
/* array might be sparse */
if (!c3_periphs_clks.hws[clkid])

32
drivers/clk/meson/c3-pll.c
View File

@@ -653,32 +653,6 @@ static struct clk_hw *c3_pll_hw_clks[] = {
[CLKID_MCLK1] = &mclk1.hw
};
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const c3_pll_clk_regmaps[] = {
&fclk_50m_en,
&fclk_div2,
&fclk_div2p5,
&fclk_div3,
&fclk_div4,
&fclk_div5,
&fclk_div7,
&gp0_pll_dco,
&gp0_pll,
&hifi_pll_dco,
&hifi_pll,
&mclk_pll_dco,
&mclk_pll_od,
&mclk_pll,
&mclk0_sel,
&mclk0_div_en,
&mclk0_div,
&mclk0,
&mclk1_sel,
&mclk1_div_en,
&mclk1_div,
&mclk1,
};
static const struct regmap_config clkc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -696,7 +670,7 @@ static int c3_pll_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
int clkid, ret, i;
int clkid, ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -706,10 +680,6 @@ static int c3_pll_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(c3_pll_clk_regmaps); i++)
c3_pll_clk_regmaps[i]->map = regmap;
for (clkid = 0; clkid < c3_pll_clks.num; clkid++) {
/* array might be sparse */
if (!c3_pll_clks.hws[clkid])

1
drivers/clk/meson/clk-cpu-dyndiv.c
View File

@@ -61,6 +61,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
};
const struct clk_ops meson_clk_cpu_dyndiv_ops = {
.init = clk_regmap_init,
.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
.determine_rate = meson_clk_cpu_dyndiv_determine_rate,
.set_rate = meson_clk_cpu_dyndiv_set_rate,

2
drivers/clk/meson/clk-dualdiv.c
View File

@@ -126,6 +126,7 @@ static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate,
}
const struct clk_ops meson_clk_dualdiv_ops = {
.init = clk_regmap_init,
.recalc_rate = meson_clk_dualdiv_recalc_rate,
.determine_rate = meson_clk_dualdiv_determine_rate,
.set_rate = meson_clk_dualdiv_set_rate,
@@ -133,6 +134,7 @@ const struct clk_ops meson_clk_dualdiv_ops = {
EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ops, "CLK_MESON");
const struct clk_ops meson_clk_dualdiv_ro_ops = {
.init = clk_regmap_init,
.recalc_rate = meson_clk_dualdiv_recalc_rate,
};
EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ro_ops, "CLK_MESON");

6
drivers/clk/meson/clk-mpll.c
View File

@@ -128,6 +128,11 @@ static int mpll_init(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
int ret;
ret = clk_regmap_init(hw);
if (ret)
return ret;
if (mpll->init_count)
regmap_multi_reg_write(clk->map, mpll->init_regs,
@@ -151,6 +156,7 @@ static int mpll_init(struct clk_hw *hw)
}
const struct clk_ops meson_clk_mpll_ro_ops = {
.init = clk_regmap_init,
.recalc_rate = mpll_recalc_rate,
.determine_rate = mpll_determine_rate,
};

11
drivers/clk/meson/clk-phase.c
View File

@@ -58,6 +58,7 @@ static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
}
const struct clk_ops meson_clk_phase_ops = {
.init = clk_regmap_init,
.get_phase = meson_clk_phase_get_phase,
.set_phase = meson_clk_phase_set_phase,
};
@@ -83,6 +84,11 @@ static int meson_clk_triphase_sync(struct clk_hw *hw)
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
unsigned int val;
int ret;
ret = clk_regmap_init(hw);
if (ret)
return ret;
/* Get phase 0 and sync it to phase 1 and 2 */
val = meson_parm_read(clk->map, &tph->ph0);
@@ -142,6 +148,11 @@ static int meson_sclk_ws_inv_sync(struct clk_hw *hw)
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
unsigned int val;
int ret;
ret = clk_regmap_init(hw);
if (ret)
return ret;
/* Get phase and sync the inverted value to ws */
val = meson_parm_read(clk->map, &tph->ph);

7
drivers/clk/meson/clk-pll.c
View File

@@ -311,6 +311,11 @@ static int meson_clk_pll_init(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
int ret;
ret = clk_regmap_init(hw);
if (ret)
return ret;
/*
* Keep the clock running, which was already initialized and enabled
@@ -468,6 +473,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
* the other ops except set_rate since the rate is fixed.
*/
const struct clk_ops meson_clk_pcie_pll_ops = {
.init = clk_regmap_init,
.recalc_rate = meson_clk_pll_recalc_rate,
.determine_rate = meson_clk_pll_determine_rate,
.is_enabled = meson_clk_pll_is_enabled,
@@ -488,6 +494,7 @@ const struct clk_ops meson_clk_pll_ops = {
EXPORT_SYMBOL_NS_GPL(meson_clk_pll_ops, "CLK_MESON");
const struct clk_ops meson_clk_pll_ro_ops = {
.init = clk_regmap_init,
.recalc_rate = meson_clk_pll_recalc_rate,
.is_enabled = meson_clk_pll_is_enabled,
};

49
drivers/clk/meson/clk-regmap.c
View File

@@ -4,9 +4,52 @@
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include "clk-regmap.h"
int clk_regmap_init(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct device_node *np, *parent_np;
struct device *dev;
/* Allow regmap to be preset as it was historically done */
if (clk->map)
return 0;
/*
* FIXME: what follows couples the controller implementation
* and clk_regmap clock type. This situation is not desirable
* but temporary, until the controller is able to register
* a hook to initialize a clock type
*/
/* Check the usual dev enabled controller with an basic IO regmap */
dev = clk_hw_get_dev(hw);
if (dev) {
clk->map = dev_get_regmap(dev, NULL);
if (clk->map)
return 0;
}
/* Move on to early and syscon based controllers */
np = clk_hw_get_of_node(hw);
if (np) {
parent_np = of_get_parent(np);
clk->map = syscon_node_to_regmap(parent_np);
of_node_put(parent_np);
if (!IS_ERR_OR_NULL(clk->map))
return 0;
}
/* Bail out if regmap can't be found */
return -EINVAL;
}
EXPORT_SYMBOL_NS_GPL(clk_regmap_init, "CLK_MESON");
static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable)
{
struct clk_regmap *clk = to_clk_regmap(hw);
@@ -45,6 +88,7 @@ static int clk_regmap_gate_is_enabled(struct clk_hw *hw)
}
const struct clk_ops clk_regmap_gate_ops = {
.init = clk_regmap_init,
.enable = clk_regmap_gate_enable,
.disable = clk_regmap_gate_disable,
.is_enabled = clk_regmap_gate_is_enabled,
@@ -52,6 +96,7 @@ const struct clk_ops clk_regmap_gate_ops = {
EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ops, "CLK_MESON");
const struct clk_ops clk_regmap_gate_ro_ops = {
.init = clk_regmap_init,
.is_enabled = clk_regmap_gate_is_enabled,
};
EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ro_ops, "CLK_MESON");
@@ -121,6 +166,7 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */
const struct clk_ops clk_regmap_divider_ops = {
.init = clk_regmap_init,
.recalc_rate = clk_regmap_div_recalc_rate,
.determine_rate = clk_regmap_div_determine_rate,
.set_rate = clk_regmap_div_set_rate,
@@ -128,6 +174,7 @@ const struct clk_ops clk_regmap_divider_ops = {
EXPORT_SYMBOL_NS_GPL(clk_regmap_divider_ops, "CLK_MESON");
const struct clk_ops clk_regmap_divider_ro_ops = {
.init = clk_regmap_init,
.recalc_rate = clk_regmap_div_recalc_rate,
.determine_rate = clk_regmap_div_determine_rate,
};
@@ -170,6 +217,7 @@ static int clk_regmap_mux_determine_rate(struct clk_hw *hw,
}
const struct clk_ops clk_regmap_mux_ops = {
.init = clk_regmap_init,
.get_parent = clk_regmap_mux_get_parent,
.set_parent = clk_regmap_mux_set_parent,
.determine_rate = clk_regmap_mux_determine_rate,
@@ -177,6 +225,7 @@ const struct clk_ops clk_regmap_mux_ops = {
EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ops, "CLK_MESON");
const struct clk_ops clk_regmap_mux_ro_ops = {
.init = clk_regmap_init,
.get_parent = clk_regmap_mux_get_parent,
};
EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ro_ops, "CLK_MESON");

4
drivers/clk/meson/clk-regmap.h
View File

@@ -7,6 +7,7 @@
#ifndef __CLK_REGMAP_H
#define __CLK_REGMAP_H
#include <linux/device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
@@ -31,6 +32,9 @@ static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw)
return container_of(hw, struct clk_regmap, hw);
}
/* clk_regmap init op to get and cache regmap from the controllers */
int clk_regmap_init(struct clk_hw *hw);
/**
* struct clk_regmap_gate_data - regmap backed gate specific data
*

34
drivers/clk/meson/g12a-aoclk.c
View File

@@ -381,38 +381,6 @@ static const unsigned int g12a_aoclk_reset[] = {
[RESET_AO_IR_OUT] = 23,
};
static struct clk_regmap *g12a_aoclk_regmap[] = {
&g12a_aoclk_ahb,
&g12a_aoclk_ir_in,
&g12a_aoclk_i2c_m0,
&g12a_aoclk_i2c_s0,
&g12a_aoclk_uart,
&g12a_aoclk_prod_i2c,
&g12a_aoclk_uart2,
&g12a_aoclk_ir_out,
&g12a_aoclk_saradc,
&g12a_aoclk_mailbox,
&g12a_aoclk_m3,
&g12a_aoclk_ahb_sram,
&g12a_aoclk_rti,
&g12a_aoclk_m4_fclk,
&g12a_aoclk_m4_hclk,
&g12a_aoclk_cts_oscin,
&g12a_aoclk_32k_by_oscin_pre,
&g12a_aoclk_32k_by_oscin_div,
&g12a_aoclk_32k_by_oscin_sel,
&g12a_aoclk_32k_by_oscin,
&g12a_aoclk_cec_pre,
&g12a_aoclk_cec_div,
&g12a_aoclk_cec_sel,
&g12a_aoclk_cec,
&g12a_aoclk_cts_rtc_oscin,
&g12a_aoclk_clk81,
&g12a_aoclk_saradc_mux,
&g12a_aoclk_saradc_div,
&g12a_aoclk_saradc_gate,
};
static struct clk_hw *g12a_aoclk_hw_clks[] = {
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
@@ -449,8 +417,6 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(g12a_aoclk_reset),
.reset = g12a_aoclk_reset,
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
.clks = g12a_aoclk_regmap,
.hw_clks = {
.hws = g12a_aoclk_hw_clks,
.num = ARRAY_SIZE(g12a_aoclk_hw_clks),

372
drivers/clk/meson/g12a.c
View File

@@ -24,10 +24,119 @@
#include "vid-pll-div.h"
#include "vclk.h"
#include "meson-eeclk.h"
#include "g12a.h"
#include <dt-bindings/clock/g12a-clkc.h>
#define HHI_MIPI_CNTL0 0x000
#define HHI_MIPI_CNTL1 0x004
#define HHI_MIPI_CNTL2 0x008
#define HHI_MIPI_STS 0x00c
#define HHI_GP0_PLL_CNTL0 0x040
#define HHI_GP0_PLL_CNTL1 0x044
#define HHI_GP0_PLL_CNTL2 0x048
#define HHI_GP0_PLL_CNTL3 0x04c
#define HHI_GP0_PLL_CNTL4 0x050
#define HHI_GP0_PLL_CNTL5 0x054
#define HHI_GP0_PLL_CNTL6 0x058
#define HHI_GP0_PLL_STS 0x05c
#define HHI_GP1_PLL_CNTL0 0x060
#define HHI_GP1_PLL_CNTL1 0x064
#define HHI_GP1_PLL_CNTL2 0x068
#define HHI_GP1_PLL_CNTL3 0x06c
#define HHI_GP1_PLL_CNTL4 0x070
#define HHI_GP1_PLL_CNTL5 0x074
#define HHI_GP1_PLL_CNTL6 0x078
#define HHI_GP1_PLL_STS 0x07c
#define HHI_PCIE_PLL_CNTL0 0x098
#define HHI_PCIE_PLL_CNTL1 0x09c
#define HHI_PCIE_PLL_CNTL2 0x0a0
#define HHI_PCIE_PLL_CNTL3 0x0a4
#define HHI_PCIE_PLL_CNTL4 0x0a8
#define HHI_PCIE_PLL_CNTL5 0x0ac
#define HHI_PCIE_PLL_STS 0x0b8
#define HHI_HIFI_PLL_CNTL0 0x0d8
#define HHI_HIFI_PLL_CNTL1 0x0dc
#define HHI_HIFI_PLL_CNTL2 0x0e0
#define HHI_HIFI_PLL_CNTL3 0x0e4
#define HHI_HIFI_PLL_CNTL4 0x0e8
#define HHI_HIFI_PLL_CNTL5 0x0ec
#define HHI_HIFI_PLL_CNTL6 0x0f0
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12c
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_OTHER2 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1a0
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLKC_CNTL 0x1b4
#define HHI_VPU_CLK_CNTL 0x1bc
#define HHI_ISP_CLK_CNTL 0x1c0
#define HHI_NNA_CLK_CNTL 0x1c8
#define HHI_HDMI_CLK_CNTL 0x1cc
#define HHI_VDEC_CLK_CNTL 0x1e0
#define HHI_VDEC2_CLK_CNTL 0x1e4
#define HHI_VDEC3_CLK_CNTL 0x1e8
#define HHI_VDEC4_CLK_CNTL 0x1ec
#define HHI_HDCP22_CLK_CNTL 0x1f0
#define HHI_VAPBCLK_CNTL 0x1f4
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
#define HHI_SYS_CPUB_CLK_CNTL 0x208
#define HHI_VPU_CLKB_CNTL 0x20c
#define HHI_SYS_CPU_CLK_CNTL2 0x210
#define HHI_SYS_CPU_CLK_CNTL3 0x214
#define HHI_SYS_CPU_CLK_CNTL4 0x218
#define HHI_SYS_CPU_CLK_CNTL5 0x21c
#define HHI_SYS_CPU_CLK_CNTL6 0x220
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
#define HHI_NAND_CLK_CNTL 0x25c
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL0 0x278
#define HHI_MPLL_CNTL1 0x27c
#define HHI_MPLL_CNTL2 0x280
#define HHI_MPLL_CNTL3 0x284
#define HHI_MPLL_CNTL4 0x288
#define HHI_MPLL_CNTL5 0x28c
#define HHI_MPLL_CNTL6 0x290
#define HHI_MPLL_CNTL7 0x294
#define HHI_MPLL_CNTL8 0x298
#define HHI_FIX_PLL_CNTL0 0x2a0
#define HHI_FIX_PLL_CNTL1 0x2a4
#define HHI_FIX_PLL_CNTL3 0x2ac
#define HHI_SYS_PLL_CNTL0 0x2f4
#define HHI_SYS_PLL_CNTL1 0x2f8
#define HHI_SYS_PLL_CNTL2 0x2fc
#define HHI_SYS_PLL_CNTL3 0x300
#define HHI_SYS_PLL_CNTL4 0x304
#define HHI_SYS_PLL_CNTL5 0x308
#define HHI_SYS_PLL_CNTL6 0x30c
#define HHI_HDMI_PLL_CNTL0 0x320
#define HHI_HDMI_PLL_CNTL1 0x324
#define HHI_HDMI_PLL_CNTL2 0x328
#define HHI_HDMI_PLL_CNTL3 0x32c
#define HHI_HDMI_PLL_CNTL4 0x330
#define HHI_HDMI_PLL_CNTL5 0x334
#define HHI_HDMI_PLL_CNTL6 0x338
#define HHI_SPICC_CLK_CNTL 0x3dc
#define HHI_SYS1_PLL_CNTL0 0x380
#define HHI_SYS1_PLL_CNTL1 0x384
#define HHI_SYS1_PLL_CNTL2 0x388
#define HHI_SYS1_PLL_CNTL3 0x38c
#define HHI_SYS1_PLL_CNTL4 0x390
#define HHI_SYS1_PLL_CNTL5 0x394
#define HHI_SYS1_PLL_CNTL6 0x398
static struct clk_regmap g12a_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
@@ -5126,261 +5235,6 @@ static struct clk_hw *sm1_hw_clks[] = {
[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
};
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12a_clk81,
&g12a_dos,
&g12a_ddr,
&g12a_audio_locker,
&g12a_mipi_dsi_host,
&g12a_eth_phy,
&g12a_isa,
&g12a_pl301,
&g12a_periphs,
&g12a_spicc_0,
&g12a_i2c,
&g12a_sana,
&g12a_sd,
&g12a_rng0,
&g12a_uart0,
&g12a_spicc_1,
&g12a_hiu_reg,
&g12a_mipi_dsi_phy,
&g12a_assist_misc,
&g12a_emmc_a,
&g12a_emmc_b,
&g12a_emmc_c,
&g12a_audio_codec,
&g12a_audio,
&g12a_eth_core,
&g12a_demux,
&g12a_audio_ififo,
&g12a_adc,
&g12a_uart1,
&g12a_g2d,
&g12a_reset,
&g12a_pcie_comb,
&g12a_parser,
&g12a_usb_general,
&g12a_pcie_phy,
&g12a_ahb_arb0,
&g12a_ahb_data_bus,
&g12a_ahb_ctrl_bus,
&g12a_htx_hdcp22,
&g12a_htx_pclk,
&g12a_bt656,
&g12a_usb1_to_ddr,
&g12a_mmc_pclk,
&g12a_uart2,
&g12a_vpu_intr,
&g12a_gic,
&g12a_sd_emmc_a_clk0,
&g12a_sd_emmc_b_clk0,
&g12a_sd_emmc_c_clk0,
&g12a_mpeg_clk_div,
&g12a_sd_emmc_a_clk0_div,
&g12a_sd_emmc_b_clk0_div,
&g12a_sd_emmc_c_clk0_div,
&g12a_mpeg_clk_sel,
&g12a_sd_emmc_a_clk0_sel,
&g12a_sd_emmc_b_clk0_sel,
&g12a_sd_emmc_c_clk0_sel,
&g12a_mpll0,
&g12a_mpll1,
&g12a_mpll2,
&g12a_mpll3,
&g12a_mpll0_div,
&g12a_mpll1_div,
&g12a_mpll2_div,
&g12a_mpll3_div,
&g12a_fixed_pll,
&g12a_sys_pll,
&g12a_gp0_pll,
&g12a_hifi_pll,
&g12a_vclk2_venci0,
&g12a_vclk2_venci1,
&g12a_vclk2_vencp0,
&g12a_vclk2_vencp1,
&g12a_vclk2_venct0,
&g12a_vclk2_venct1,
&g12a_vclk2_other,
&g12a_vclk2_enci,
&g12a_vclk2_encp,
&g12a_dac_clk,
&g12a_aoclk_gate,
&g12a_iec958_gate,
&g12a_enc480p,
&g12a_rng1,
&g12a_vclk2_enct,
&g12a_vclk2_encl,
&g12a_vclk2_venclmmc,
&g12a_vclk2_vencl,
&g12a_vclk2_other1,
&g12a_fixed_pll_dco,
&g12a_sys_pll_dco,
&g12a_gp0_pll_dco,
&g12a_hifi_pll_dco,
&g12a_fclk_div2,
&g12a_fclk_div3,
&g12a_fclk_div4,
&g12a_fclk_div5,
&g12a_fclk_div7,
&g12a_fclk_div2p5,
&g12a_dma,
&g12a_efuse,
&g12a_rom_boot,
&g12a_reset_sec,
&g12a_sec_ahb_apb3,
&g12a_vpu_0_sel,
&g12a_vpu_0_div,
&g12a_vpu_0,
&g12a_vpu_1_sel,
&g12a_vpu_1_div,
&g12a_vpu_1,
&g12a_vpu,
&g12a_vapb_0_sel,
&g12a_vapb_0_div,
&g12a_vapb_0,
&g12a_vapb_1_sel,
&g12a_vapb_1_div,
&g12a_vapb_1,
&g12a_vapb_sel,
&g12a_vapb,
&g12a_hdmi_pll_dco,
&g12a_hdmi_pll_od,
&g12a_hdmi_pll_od2,
&g12a_hdmi_pll,
&g12a_vid_pll_div,
&g12a_vid_pll_sel,
&g12a_vid_pll,
&g12a_vclk_sel,
&g12a_vclk2_sel,
&g12a_vclk_input,
&g12a_vclk2_input,
&g12a_vclk_div,
&g12a_vclk2_div,
&g12a_vclk,
&g12a_vclk2,
&g12a_vclk_div1,
&g12a_vclk_div2_en,
&g12a_vclk_div4_en,
&g12a_vclk_div6_en,
&g12a_vclk_div12_en,
&g12a_vclk2_div1,
&g12a_vclk2_div2_en,
&g12a_vclk2_div4_en,
&g12a_vclk2_div6_en,
&g12a_vclk2_div12_en,
&g12a_cts_enci_sel,
&g12a_cts_encp_sel,
&g12a_cts_encl_sel,
&g12a_cts_vdac_sel,
&g12a_hdmi_tx_sel,
&g12a_cts_enci,
&g12a_cts_encp,
&g12a_cts_encl,
&g12a_cts_vdac,
&g12a_hdmi_tx,
&g12a_hdmi_sel,
&g12a_hdmi_div,
&g12a_hdmi,
&g12a_mali_0_sel,
&g12a_mali_0_div,
&g12a_mali_0,
&g12a_mali_1_sel,
&g12a_mali_1_div,
&g12a_mali_1,
&g12a_mali,
&g12a_mpll_50m,
&g12a_sys_pll_div16_en,
&g12a_cpu_clk_premux0,
&g12a_cpu_clk_mux0_div,
&g12a_cpu_clk_postmux0,
&g12a_cpu_clk_premux1,
&g12a_cpu_clk_mux1_div,
&g12a_cpu_clk_postmux1,
&g12a_cpu_clk_dyn,
&g12a_cpu_clk,
&g12a_cpu_clk_div16_en,
&g12a_cpu_clk_apb_div,
&g12a_cpu_clk_apb,
&g12a_cpu_clk_atb_div,
&g12a_cpu_clk_atb,
&g12a_cpu_clk_axi_div,
&g12a_cpu_clk_axi,
&g12a_cpu_clk_trace_div,
&g12a_cpu_clk_trace,
&g12a_pcie_pll_od,
&g12a_pcie_pll_dco,
&g12a_vdec_1_sel,
&g12a_vdec_1_div,
&g12a_vdec_1,
&g12a_vdec_hevc_sel,
&g12a_vdec_hevc_div,
&g12a_vdec_hevc,
&g12a_vdec_hevcf_sel,
&g12a_vdec_hevcf_div,
&g12a_vdec_hevcf,
&g12a_ts_div,
&g12a_ts,
&g12b_cpu_clk,
&g12b_sys1_pll_dco,
&g12b_sys1_pll,
&g12b_sys1_pll_div16_en,
&g12b_cpub_clk_premux0,
&g12b_cpub_clk_mux0_div,
&g12b_cpub_clk_postmux0,
&g12b_cpub_clk_premux1,
&g12b_cpub_clk_mux1_div,
&g12b_cpub_clk_postmux1,
&g12b_cpub_clk_dyn,
&g12b_cpub_clk,
&g12b_cpub_clk_div16_en,
&g12b_cpub_clk_apb_sel,
&g12b_cpub_clk_apb,
&g12b_cpub_clk_atb_sel,
&g12b_cpub_clk_atb,
&g12b_cpub_clk_axi_sel,
&g12b_cpub_clk_axi,
&g12b_cpub_clk_trace_sel,
&g12b_cpub_clk_trace,
&sm1_gp1_pll_dco,
&sm1_gp1_pll,
&sm1_dsu_clk_premux0,
&sm1_dsu_clk_premux1,
&sm1_dsu_clk_mux0_div,
&sm1_dsu_clk_postmux0,
&sm1_dsu_clk_mux1_div,
&sm1_dsu_clk_postmux1,
&sm1_dsu_clk_dyn,
&sm1_dsu_final_clk,
&sm1_dsu_clk,
&sm1_cpu1_clk,
&sm1_cpu2_clk,
&sm1_cpu3_clk,
&g12a_spicc0_sclk_sel,
&g12a_spicc0_sclk_div,
&g12a_spicc0_sclk,
&g12a_spicc1_sclk_sel,
&g12a_spicc1_sclk_div,
&g12a_spicc1_sclk,
&sm1_nna_axi_clk_sel,
&sm1_nna_axi_clk_div,
&sm1_nna_axi_clk,
&sm1_nna_core_clk_sel,
&sm1_nna_core_clk_div,
&sm1_nna_core_clk,
&g12a_mipi_dsi_pxclk_sel,
&g12a_mipi_dsi_pxclk_div,
&g12a_mipi_dsi_pxclk,
&g12b_mipi_isp_sel,
&g12b_mipi_isp_div,
&g12b_mipi_isp,
&g12b_mipi_isp_gate,
&g12b_csi_phy1,
&g12b_csi_phy0,
};
static const struct reg_sequence g12a_init_regs[] = {
{ .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
};
@@ -5559,8 +5413,6 @@ static int meson_g12a_probe(struct platform_device *pdev)
static const struct meson_g12a_data g12a_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_clks = {
.hws = g12a_hw_clks,
.num = ARRAY_SIZE(g12a_hw_clks),
@@ -5573,8 +5425,6 @@ static const struct meson_g12a_data g12a_clkc_data = {
static const struct meson_g12a_data g12b_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_clks = {
.hws = g12b_hw_clks,
.num = ARRAY_SIZE(g12b_hw_clks),
@@ -5585,8 +5435,6 @@ static const struct meson_g12a_data g12b_clkc_data = {
static const struct meson_g12a_data sm1_clkc_data = {
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
.hw_clks = {
.hws = sm1_hw_clks,
.num = ARRAY_SIZE(sm1_hw_clks),

130
drivers/clk/meson/g12a.h
View File

@@ -1,130 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2016 Amlogic, Inc.
* Author: Michael Turquette <mturquette@baylibre.com>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
* Author: Jian Hu <jian.hu@amlogic.com>
*
*/
#ifndef __G12A_H
#define __G12A_H
/*
* Clock controller register offsets
*
* Register offsets from the data sheet must be multiplied by 4 before
* adding them to the base address to get the right value.
*/
#define HHI_MIPI_CNTL0 0x000
#define HHI_MIPI_CNTL1 0x004
#define HHI_MIPI_CNTL2 0x008
#define HHI_MIPI_STS 0x00C
#define HHI_GP0_PLL_CNTL0 0x040
#define HHI_GP0_PLL_CNTL1 0x044
#define HHI_GP0_PLL_CNTL2 0x048
#define HHI_GP0_PLL_CNTL3 0x04C
#define HHI_GP0_PLL_CNTL4 0x050
#define HHI_GP0_PLL_CNTL5 0x054
#define HHI_GP0_PLL_CNTL6 0x058
#define HHI_GP0_PLL_STS 0x05C
#define HHI_GP1_PLL_CNTL0 0x060
#define HHI_GP1_PLL_CNTL1 0x064
#define HHI_GP1_PLL_CNTL2 0x068
#define HHI_GP1_PLL_CNTL3 0x06C
#define HHI_GP1_PLL_CNTL4 0x070
#define HHI_GP1_PLL_CNTL5 0x074
#define HHI_GP1_PLL_CNTL6 0x078
#define HHI_GP1_PLL_STS 0x07C
#define HHI_PCIE_PLL_CNTL0 0x098
#define HHI_PCIE_PLL_CNTL1 0x09C
#define HHI_PCIE_PLL_CNTL2 0x0A0
#define HHI_PCIE_PLL_CNTL3 0x0A4
#define HHI_PCIE_PLL_CNTL4 0x0A8
#define HHI_PCIE_PLL_CNTL5 0x0AC
#define HHI_PCIE_PLL_STS 0x0B8
#define HHI_HIFI_PLL_CNTL0 0x0D8
#define HHI_HIFI_PLL_CNTL1 0x0DC
#define HHI_HIFI_PLL_CNTL2 0x0E0
#define HHI_HIFI_PLL_CNTL3 0x0E4
#define HHI_HIFI_PLL_CNTL4 0x0E8
#define HHI_HIFI_PLL_CNTL5 0x0EC
#define HHI_HIFI_PLL_CNTL6 0x0F0
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12C
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_OTHER2 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_TS_CLK_CNTL 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1A0
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLKC_CNTL 0x1b4
#define HHI_VPU_CLK_CNTL 0x1bC
#define HHI_ISP_CLK_CNTL 0x1C0
#define HHI_NNA_CLK_CNTL 0x1C8
#define HHI_HDMI_CLK_CNTL 0x1CC
#define HHI_VDEC_CLK_CNTL 0x1E0
#define HHI_VDEC2_CLK_CNTL 0x1E4
#define HHI_VDEC3_CLK_CNTL 0x1E8
#define HHI_VDEC4_CLK_CNTL 0x1EC
#define HHI_HDCP22_CLK_CNTL 0x1F0
#define HHI_VAPBCLK_CNTL 0x1F4
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
#define HHI_SYS_CPUB_CLK_CNTL 0x208
#define HHI_VPU_CLKB_CNTL 0x20C
#define HHI_SYS_CPU_CLK_CNTL2 0x210
#define HHI_SYS_CPU_CLK_CNTL3 0x214
#define HHI_SYS_CPU_CLK_CNTL4 0x218
#define HHI_SYS_CPU_CLK_CNTL5 0x21c
#define HHI_SYS_CPU_CLK_CNTL6 0x220
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
#define HHI_NAND_CLK_CNTL 0x25C
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL0 0x278
#define HHI_MPLL_CNTL1 0x27C
#define HHI_MPLL_CNTL2 0x280
#define HHI_MPLL_CNTL3 0x284
#define HHI_MPLL_CNTL4 0x288
#define HHI_MPLL_CNTL5 0x28c
#define HHI_MPLL_CNTL6 0x290
#define HHI_MPLL_CNTL7 0x294
#define HHI_MPLL_CNTL8 0x298
#define HHI_FIX_PLL_CNTL0 0x2A0
#define HHI_FIX_PLL_CNTL1 0x2A4
#define HHI_FIX_PLL_CNTL3 0x2AC
#define HHI_SYS_PLL_CNTL0 0x2f4
#define HHI_SYS_PLL_CNTL1 0x2f8
#define HHI_SYS_PLL_CNTL2 0x2fc
#define HHI_SYS_PLL_CNTL3 0x300
#define HHI_SYS_PLL_CNTL4 0x304
#define HHI_SYS_PLL_CNTL5 0x308
#define HHI_SYS_PLL_CNTL6 0x30c
#define HHI_HDMI_PLL_CNTL0 0x320
#define HHI_HDMI_PLL_CNTL1 0x324
#define HHI_HDMI_PLL_CNTL2 0x328
#define HHI_HDMI_PLL_CNTL3 0x32c
#define HHI_HDMI_PLL_CNTL4 0x330
#define HHI_HDMI_PLL_CNTL5 0x334
#define HHI_HDMI_PLL_CNTL6 0x338
#define HHI_SPICC_CLK_CNTL 0x3dc
#define HHI_SYS1_PLL_CNTL0 0x380
#define HHI_SYS1_PLL_CNTL1 0x384
#define HHI_SYS1_PLL_CNTL2 0x388
#define HHI_SYS1_PLL_CNTL3 0x38c
#define HHI_SYS1_PLL_CNTL4 0x390
#define HHI_SYS1_PLL_CNTL5 0x394
#define HHI_SYS1_PLL_CNTL6 0x398
#endif /* __G12A_H */

19
drivers/clk/meson/gxbb-aoclk.c
View File

@@ -237,23 +237,6 @@ static const unsigned int gxbb_aoclk_reset[] = {
[RESET_AO_IR_BLASTER] = 23,
};
static struct clk_regmap *gxbb_aoclk[] = {
&remote_ao,
&i2c_master_ao,
&i2c_slave_ao,
&uart1_ao,
&uart2_ao,
&ir_blaster_ao,
&ao_cts_oscin,
&ao_32k_pre,
&ao_32k_div,
&ao_32k_sel,
&ao_32k,
&ao_cts_rtc_oscin,
&ao_clk81,
&ao_cts_cec,
};
static struct clk_hw *gxbb_aoclk_hw_clks[] = {
[CLKID_AO_REMOTE] = &remote_ao.hw,
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -275,8 +258,6 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
.reset_reg = AO_RTI_GEN_CNTL_REG0,
.num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
.reset = gxbb_aoclk_reset,
.num_clks = ARRAY_SIZE(gxbb_aoclk),
.clks = gxbb_aoclk,
.hw_clks = {
.hws = gxbb_aoclk_hw_clks,
.num = ARRAY_SIZE(gxbb_aoclk_hw_clks),

492
drivers/clk/meson/gxbb.c
View File

@@ -10,7 +10,6 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include "gxbb.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-mpll.h"
@@ -19,6 +18,104 @@
#include <dt-bindings/clock/gxbb-clkc.h>
#define SCR 0x2c
#define TIMEOUT_VALUE 0x3c
#define HHI_GP0_PLL_CNTL 0x40
#define HHI_GP0_PLL_CNTL2 0x44
#define HHI_GP0_PLL_CNTL3 0x48
#define HHI_GP0_PLL_CNTL4 0x4c
#define HHI_GP0_PLL_CNTL5 0x50
#define HHI_GP0_PLL_CNTL1 0x58
#define HHI_XTAL_DIVN_CNTL 0xbc
#define HHI_TIMER90K 0xec
#define HHI_MEM_PD_REG0 0x100
#define HHI_MEM_PD_REG1 0x104
#define HHI_VPU_MEM_PD_REG1 0x108
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12c
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_AO 0x154
#define HHI_SYS_OSCIN_CNTL 0x158
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_SYS_CPU_RESET_CNTL 0x160
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_AUD_CLK_CNTL2 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_VID_PLL_CLK_DIV 0x1a0
#define HHI_AUD_CLK_CNTL3 0x1a4
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLK_CNTL 0x1bc
#define HHI_HDMI_CLK_CNTL 0x1cc
#define HHI_VDEC_CLK_CNTL 0x1e0
#define HHI_VDEC2_CLK_CNTL 0x1e4
#define HHI_VDEC3_CLK_CNTL 0x1e8
#define HHI_VDEC4_CLK_CNTL 0x1ec
#define HHI_HDCP22_CLK_CNTL 0x1f0
#define HHI_VAPBCLK_CNTL 0x1f4
#define HHI_VPU_CLKB_CNTL 0x20c
#define HHI_USB_CLK_CNTL 0x220
#define HHI_32K_CLK_CNTL 0x224
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_PCM_CLK_CNTL 0x258
#define HHI_NAND_CLK_CNTL 0x25c
#define HHI_SD_EMMC_CLK_CNTL 0x264
#define HHI_MPLL_CNTL 0x280
#define HHI_MPLL_CNTL2 0x284
#define HHI_MPLL_CNTL3 0x288
#define HHI_MPLL_CNTL4 0x28c
#define HHI_MPLL_CNTL5 0x290
#define HHI_MPLL_CNTL6 0x294
#define HHI_MPLL_CNTL7 0x298
#define HHI_MPLL_CNTL8 0x29c
#define HHI_MPLL_CNTL9 0x2a0
#define HHI_MPLL_CNTL10 0x2a4
#define HHI_MPLL3_CNTL0 0x2e0
#define HHI_MPLL3_CNTL1 0x2e4
#define HHI_VDAC_CNTL0 0x2f4
#define HHI_VDAC_CNTL1 0x2f8
#define HHI_SYS_PLL_CNTL 0x300
#define HHI_SYS_PLL_CNTL2 0x304
#define HHI_SYS_PLL_CNTL3 0x308
#define HHI_SYS_PLL_CNTL4 0x30c
#define HHI_SYS_PLL_CNTL5 0x310
#define HHI_DPLL_TOP_I 0x318
#define HHI_DPLL_TOP2_I 0x31c
#define HHI_HDMI_PLL_CNTL 0x320
#define HHI_HDMI_PLL_CNTL2 0x324
#define HHI_HDMI_PLL_CNTL3 0x328
#define HHI_HDMI_PLL_CNTL4 0x32c
#define HHI_HDMI_PLL_CNTL5 0x330
#define HHI_HDMI_PLL_CNTL6 0x334
#define HHI_HDMI_PLL_CNTL_I 0x338
#define HHI_HDMI_PLL_CNTL7 0x33c
#define HHI_HDMI_PHY_CNTL0 0x3a0
#define HHI_HDMI_PHY_CNTL1 0x3a4
#define HHI_HDMI_PHY_CNTL2 0x3a8
#define HHI_HDMI_PHY_CNTL3 0x3ac
#define HHI_VID_LOCK_CLK_CNTL 0x3c8
#define HHI_BT656_CLK_CNTL 0x3d4
#define HHI_SAR_CLK_CNTL 0x3d8
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
PLL_PARAMS(32, 1),
PLL_PARAMS(33, 1),
@@ -3140,398 +3237,7 @@ static struct clk_hw *gxl_hw_clks[] = {
[CLKID_ACODEC] = &gxl_acodec.hw,
};
static struct clk_regmap *const gxbb_clk_regmaps[] = {
&gxbb_clk81,
&gxbb_ddr,
&gxbb_dos,
&gxbb_isa,
&gxbb_pl301,
&gxbb_periphs,
&gxbb_spicc,
&gxbb_i2c,
&gxbb_sar_adc,
&gxbb_smart_card,
&gxbb_rng0,
&gxbb_uart0,
&gxbb_sdhc,
&gxbb_stream,
&gxbb_async_fifo,
&gxbb_sdio,
&gxbb_abuf,
&gxbb_hiu_iface,
&gxbb_assist_misc,
&gxbb_spi,
&gxbb_i2s_spdif,
&gxbb_eth,
&gxbb_demux,
&gxbb_aiu_glue,
&gxbb_iec958,
&gxbb_i2s_out,
&gxbb_amclk,
&gxbb_aififo2,
&gxbb_mixer,
&gxbb_mixer_iface,
&gxbb_adc,
&gxbb_blkmv,
&gxbb_aiu,
&gxbb_uart1,
&gxbb_g2d,
&gxbb_usb0,
&gxbb_usb1,
&gxbb_reset,
&gxbb_nand,
&gxbb_dos_parser,
&gxbb_usb,
&gxbb_vdin1,
&gxbb_ahb_arb0,
&gxbb_efuse,
&gxbb_boot_rom,
&gxbb_ahb_data_bus,
&gxbb_ahb_ctrl_bus,
&gxbb_hdmi_intr_sync,
&gxbb_hdmi_pclk,
&gxbb_usb1_ddr_bridge,
&gxbb_usb0_ddr_bridge,
&gxbb_mmc_pclk,
&gxbb_dvin,
&gxbb_uart2,
&gxbb_sana,
&gxbb_vpu_intr,
&gxbb_sec_ahb_ahb3_bridge,
&gxbb_clk81_a53,
&gxbb_vclk2_venci0,
&gxbb_vclk2_venci1,
&gxbb_vclk2_vencp0,
&gxbb_vclk2_vencp1,
&gxbb_gclk_venci_int0,
&gxbb_gclk_vencp_int,
&gxbb_dac_clk,
&gxbb_aoclk_gate,
&gxbb_iec958_gate,
&gxbb_enc480p,
&gxbb_rng1,
&gxbb_gclk_venci_int1,
&gxbb_vclk2_venclmcc,
&gxbb_vclk2_vencl,
&gxbb_vclk_other,
&gxbb_edp,
&gxbb_ao_media_cpu,
&gxbb_ao_ahb_sram,
&gxbb_ao_ahb_bus,
&gxbb_ao_iface,
&gxbb_ao_i2c,
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
&gxbb_sar_adc_clk,
&gxbb_mali_0,
&gxbb_mali_1,
&gxbb_cts_amclk,
&gxbb_cts_mclk_i958,
&gxbb_32k_clk,
&gxbb_sd_emmc_a_clk0,
&gxbb_sd_emmc_b_clk0,
&gxbb_sd_emmc_c_clk0,
&gxbb_vpu_0,
&gxbb_vpu_1,
&gxbb_vapb_0,
&gxbb_vapb_1,
&gxbb_vapb,
&gxbb_mpeg_clk_div,
&gxbb_sar_adc_clk_div,
&gxbb_mali_0_div,
&gxbb_mali_1_div,
&gxbb_cts_mclk_i958_div,
&gxbb_32k_clk_div,
&gxbb_sd_emmc_a_clk0_div,
&gxbb_sd_emmc_b_clk0_div,
&gxbb_sd_emmc_c_clk0_div,
&gxbb_vpu_0_div,
&gxbb_vpu_1_div,
&gxbb_vapb_0_div,
&gxbb_vapb_1_div,
&gxbb_mpeg_clk_sel,
&gxbb_sar_adc_clk_sel,
&gxbb_mali_0_sel,
&gxbb_mali_1_sel,
&gxbb_mali,
&gxbb_cts_amclk_sel,
&gxbb_cts_mclk_i958_sel,
&gxbb_cts_i958,
&gxbb_32k_clk_sel,
&gxbb_sd_emmc_a_clk0_sel,
&gxbb_sd_emmc_b_clk0_sel,
&gxbb_sd_emmc_c_clk0_sel,
&gxbb_vpu_0_sel,
&gxbb_vpu_1_sel,
&gxbb_vpu,
&gxbb_vapb_0_sel,
&gxbb_vapb_1_sel,
&gxbb_vapb_sel,
&gxbb_mpll0,
&gxbb_mpll1,
&gxbb_mpll2,
&gxbb_mpll0_div,
&gxbb_mpll1_div,
&gxbb_mpll2_div,
&gxbb_cts_amclk_div,
&gxbb_fixed_pll,
&gxbb_sys_pll,
&gxbb_mpll_prediv,
&gxbb_fclk_div2,
&gxbb_fclk_div3,
&gxbb_fclk_div4,
&gxbb_fclk_div5,
&gxbb_fclk_div7,
&gxbb_vdec_1_sel,
&gxbb_vdec_1_div,
&gxbb_vdec_1,
&gxbb_vdec_hevc_sel,
&gxbb_vdec_hevc_div,
&gxbb_vdec_hevc,
&gxbb_gen_clk_sel,
&gxbb_gen_clk_div,
&gxbb_gen_clk,
&gxbb_fixed_pll_dco,
&gxbb_sys_pll_dco,
&gxbb_gp0_pll,
&gxbb_vid_pll,
&gxbb_vid_pll_sel,
&gxbb_vid_pll_div,
&gxbb_vclk,
&gxbb_vclk_sel,
&gxbb_vclk_div,
&gxbb_vclk_input,
&gxbb_vclk_div1,
&gxbb_vclk_div2_en,
&gxbb_vclk_div4_en,
&gxbb_vclk_div6_en,
&gxbb_vclk_div12_en,
&gxbb_vclk2,
&gxbb_vclk2_sel,
&gxbb_vclk2_div,
&gxbb_vclk2_input,
&gxbb_vclk2_div1,
&gxbb_vclk2_div2_en,
&gxbb_vclk2_div4_en,
&gxbb_vclk2_div6_en,
&gxbb_vclk2_div12_en,
&gxbb_cts_enci,
&gxbb_cts_enci_sel,
&gxbb_cts_encp,
&gxbb_cts_encp_sel,
&gxbb_cts_vdac,
&gxbb_cts_vdac_sel,
&gxbb_hdmi_tx,
&gxbb_hdmi_tx_sel,
&gxbb_hdmi_sel,
&gxbb_hdmi_div,
&gxbb_hdmi,
&gxbb_gp0_pll_dco,
&gxbb_hdmi_pll,
&gxbb_hdmi_pll_od,
&gxbb_hdmi_pll_od2,
&gxbb_hdmi_pll_dco,
};
static struct clk_regmap *const gxl_clk_regmaps[] = {
&gxbb_clk81,
&gxbb_ddr,
&gxbb_dos,
&gxbb_isa,
&gxbb_pl301,
&gxbb_periphs,
&gxbb_spicc,
&gxbb_i2c,
&gxbb_sar_adc,
&gxbb_smart_card,
&gxbb_rng0,
&gxbb_uart0,
&gxbb_sdhc,
&gxbb_stream,
&gxbb_async_fifo,
&gxbb_sdio,
&gxbb_abuf,
&gxbb_hiu_iface,
&gxbb_assist_misc,
&gxbb_spi,
&gxbb_i2s_spdif,
&gxbb_eth,
&gxbb_demux,
&gxbb_aiu_glue,
&gxbb_iec958,
&gxbb_i2s_out,
&gxbb_amclk,
&gxbb_aififo2,
&gxbb_mixer,
&gxbb_mixer_iface,
&gxbb_adc,
&gxbb_blkmv,
&gxbb_aiu,
&gxbb_uart1,
&gxbb_g2d,
&gxbb_usb0,
&gxbb_usb1,
&gxbb_reset,
&gxbb_nand,
&gxbb_dos_parser,
&gxbb_usb,
&gxbb_vdin1,
&gxbb_ahb_arb0,
&gxbb_efuse,
&gxbb_boot_rom,
&gxbb_ahb_data_bus,
&gxbb_ahb_ctrl_bus,
&gxbb_hdmi_intr_sync,
&gxbb_hdmi_pclk,
&gxbb_usb1_ddr_bridge,
&gxbb_usb0_ddr_bridge,
&gxbb_mmc_pclk,
&gxbb_dvin,
&gxbb_uart2,
&gxbb_sana,
&gxbb_vpu_intr,
&gxbb_sec_ahb_ahb3_bridge,
&gxbb_clk81_a53,
&gxbb_vclk2_venci0,
&gxbb_vclk2_venci1,
&gxbb_vclk2_vencp0,
&gxbb_vclk2_vencp1,
&gxbb_gclk_venci_int0,
&gxbb_gclk_vencp_int,
&gxbb_dac_clk,
&gxbb_aoclk_gate,
&gxbb_iec958_gate,
&gxbb_enc480p,
&gxbb_rng1,
&gxbb_gclk_venci_int1,
&gxbb_vclk2_venclmcc,
&gxbb_vclk2_vencl,
&gxbb_vclk_other,
&gxbb_edp,
&gxbb_ao_media_cpu,
&gxbb_ao_ahb_sram,
&gxbb_ao_ahb_bus,
&gxbb_ao_iface,
&gxbb_ao_i2c,
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
&gxbb_sar_adc_clk,
&gxbb_mali_0,
&gxbb_mali_1,
&gxbb_cts_amclk,
&gxbb_cts_mclk_i958,
&gxbb_32k_clk,
&gxbb_sd_emmc_a_clk0,
&gxbb_sd_emmc_b_clk0,
&gxbb_sd_emmc_c_clk0,
&gxbb_vpu_0,
&gxbb_vpu_1,
&gxbb_vapb_0,
&gxbb_vapb_1,
&gxbb_vapb,
&gxbb_mpeg_clk_div,
&gxbb_sar_adc_clk_div,
&gxbb_mali_0_div,
&gxbb_mali_1_div,
&gxbb_cts_mclk_i958_div,
&gxbb_32k_clk_div,
&gxbb_sd_emmc_a_clk0_div,
&gxbb_sd_emmc_b_clk0_div,
&gxbb_sd_emmc_c_clk0_div,
&gxbb_vpu_0_div,
&gxbb_vpu_1_div,
&gxbb_vapb_0_div,
&gxbb_vapb_1_div,
&gxbb_mpeg_clk_sel,
&gxbb_sar_adc_clk_sel,
&gxbb_mali_0_sel,
&gxbb_mali_1_sel,
&gxbb_mali,
&gxbb_cts_amclk_sel,
&gxbb_cts_mclk_i958_sel,
&gxbb_cts_i958,
&gxbb_32k_clk_sel,
&gxbb_sd_emmc_a_clk0_sel,
&gxbb_sd_emmc_b_clk0_sel,
&gxbb_sd_emmc_c_clk0_sel,
&gxbb_vpu_0_sel,
&gxbb_vpu_1_sel,
&gxbb_vpu,
&gxbb_vapb_0_sel,
&gxbb_vapb_1_sel,
&gxbb_vapb_sel,
&gxbb_mpll0,
&gxbb_mpll1,
&gxbb_mpll2,
&gxl_mpll0_div,
&gxbb_mpll1_div,
&gxbb_mpll2_div,
&gxbb_cts_amclk_div,
&gxbb_fixed_pll,
&gxbb_sys_pll,
&gxbb_mpll_prediv,
&gxbb_fclk_div2,
&gxbb_fclk_div3,
&gxbb_fclk_div4,
&gxbb_fclk_div5,
&gxbb_fclk_div7,
&gxbb_vdec_1_sel,
&gxbb_vdec_1_div,
&gxbb_vdec_1,
&gxbb_vdec_hevc_sel,
&gxbb_vdec_hevc_div,
&gxbb_vdec_hevc,
&gxbb_gen_clk_sel,
&gxbb_gen_clk_div,
&gxbb_gen_clk,
&gxbb_fixed_pll_dco,
&gxbb_sys_pll_dco,
&gxbb_gp0_pll,
&gxbb_vid_pll,
&gxbb_vid_pll_sel,
&gxbb_vid_pll_div,
&gxbb_vclk,
&gxbb_vclk_sel,
&gxbb_vclk_div,
&gxbb_vclk_input,
&gxbb_vclk_div1,
&gxbb_vclk_div2_en,
&gxbb_vclk_div4_en,
&gxbb_vclk_div6_en,
&gxbb_vclk_div12_en,
&gxbb_vclk2,
&gxbb_vclk2_sel,
&gxbb_vclk2_div,
&gxbb_vclk2_input,
&gxbb_vclk2_div1,
&gxbb_vclk2_div2_en,
&gxbb_vclk2_div4_en,
&gxbb_vclk2_div6_en,
&gxbb_vclk2_div12_en,
&gxbb_cts_enci,
&gxbb_cts_enci_sel,
&gxbb_cts_encp,
&gxbb_cts_encp_sel,
&gxbb_cts_vdac,
&gxbb_cts_vdac_sel,
&gxbb_hdmi_tx,
&gxbb_hdmi_tx_sel,
&gxbb_hdmi_sel,
&gxbb_hdmi_div,
&gxbb_hdmi,
&gxl_gp0_pll_dco,
&gxl_hdmi_pll,
&gxl_hdmi_pll_od,
&gxl_hdmi_pll_od2,
&gxl_hdmi_pll_dco,
&gxl_acodec,
};
static const struct meson_eeclkc_data gxbb_clkc_data = {
.regmap_clks = gxbb_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
.hw_clks = {
.hws = gxbb_hw_clks,
.num = ARRAY_SIZE(gxbb_hw_clks),
@@ -3539,8 +3245,6 @@ static const struct meson_eeclkc_data gxbb_clkc_data = {
};
static const struct meson_eeclkc_data gxl_clkc_data = {
.regmap_clks = gxl_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
.hw_clks = {
.hws = gxl_hw_clks,
.num = ARRAY_SIZE(gxl_hw_clks),

115
drivers/clk/meson/gxbb.h
View File

@@ -1,115 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
* Copyright (c) 2016 AmLogic, Inc.
* Author: Michael Turquette <mturquette@baylibre.com>
*/
#ifndef __GXBB_H
#define __GXBB_H
/*
* Clock controller register offsets
*
* Register offsets from the data sheet are listed in comment blocks below.
* Those offsets must be multiplied by 4 before adding them to the base address
* to get the right value
*/
#define SCR 0x2C /* 0x0b offset in data sheet */
#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */
#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */
#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */
#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */
#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */
#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */
#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */
#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */
#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */
#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */
#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */
#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */
#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */
#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */
#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */
#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
#endif /* __GXBB_H */

5
drivers/clk/meson/meson-aoclk.c
View File

@@ -18,6 +18,7 @@
#include <linux/slab.h>
#include "meson-aoclk.h"
#include "clk-regmap.h"
static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
unsigned long id)
@@ -70,10 +71,6 @@ int meson_aoclkc_probe(struct platform_device *pdev)
return ret;
}
/* Populate regmap */
for (clkid = 0; clkid < data->num_clks; clkid++)
data->clks[clkid]->map = regmap;
/* Register all clks */
for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
if (!data->hw_clks.hws[clkid])

2
drivers/clk/meson/meson-aoclk.h
View File

@@ -23,8 +23,6 @@ struct meson_aoclk_data {
const unsigned int reset_reg;
const int num_reset;
const unsigned int *reset;
const int num_clks;
struct clk_regmap **clks;
struct meson_clk_hw_data hw_clks;
};

4
drivers/clk/meson/meson-eeclk.c
View File

@@ -39,10 +39,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
if (data->init_count)
regmap_multi_reg_write(map, data->init_regs, data->init_count);
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < data->regmap_clk_num; i++)
data->regmap_clks[i]->map = map;
for (i = 0; i < data->hw_clks.num; i++) {
/* array might be sparse */
if (!data->hw_clks.hws[i])

2
drivers/clk/meson/meson-eeclk.h
View File

@@ -14,8 +14,6 @@
struct platform_device;
struct meson_eeclkc_data {
struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num;
const struct reg_sequence *init_regs;
unsigned int init_count;
struct meson_clk_hw_data hw_clks;

9
drivers/clk/meson/meson8-ddr.c
View File

@@ -85,11 +85,6 @@ static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
.num = 2,
};
static struct clk_regmap *const meson8_ddr_clk_regmaps[] = {
&meson8_ddr_pll_dco,
&meson8_ddr_pll,
};
static const struct regmap_config meson8_ddr_clkc_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
@@ -113,10 +108,6 @@ static int meson8_ddr_clkc_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Populate regmap */
for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++)
meson8_ddr_clk_regmaps[i]->map = regmap;
/* Register all clks */
for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) {
hw = meson8_ddr_clk_hw_onecell_data.hws[i];

267
drivers/clk/meson/meson8b.c
View File

@@ -16,7 +16,6 @@
#include <linux/slab.h>
#include <linux/regmap.h>
#include "meson8b.h"
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
#include "clk-pll.h"
@@ -25,6 +24,72 @@
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
/*
* Clock controller register offsets
*
* Register offsets from the HardKernel[0] data sheet must be multiplied
* by 4 before adding them to the base address to get the right value
*
* [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
*/
#define HHI_GP_PLL_CNTL 0x40
#define HHI_GP_PLL_CNTL2 0x44
#define HHI_GP_PLL_CNTL3 0x48
#define HHI_GP_PLL_CNTL4 0x4C
#define HHI_GP_PLL_CNTL5 0x50
#define HHI_VIID_CLK_DIV 0x128
#define HHI_VIID_CLK_CNTL 0x12c
#define HHI_GCLK_MPEG0 0x140
#define HHI_GCLK_MPEG1 0x144
#define HHI_GCLK_MPEG2 0x148
#define HHI_GCLK_OTHER 0x150
#define HHI_GCLK_AO 0x154
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
#define HHI_VID_CLK_DIV 0x164
#define HHI_MPEG_CLK_CNTL 0x174
#define HHI_AUD_CLK_CNTL 0x178
#define HHI_VID_CLK_CNTL 0x17c
#define HHI_AUD_CLK_CNTL2 0x190
#define HHI_VID_CLK_CNTL2 0x194
#define HHI_VID_DIVIDER_CNTL 0x198
#define HHI_SYS_CPU_CLK_CNTL0 0x19c
#define HHI_MALI_CLK_CNTL 0x1b0
#define HHI_VPU_CLK_CNTL 0x1bc
#define HHI_HDMI_CLK_CNTL 0x1cc
#define HHI_VDEC_CLK_CNTL 0x1e0
#define HHI_VDEC2_CLK_CNTL 0x1e4
#define HHI_VDEC3_CLK_CNTL 0x1e8
#define HHI_NAND_CLK_CNTL 0x25c
#define HHI_MPLL_CNTL 0x280
#define HHI_SYS_PLL_CNTL 0x300
#define HHI_VID_PLL_CNTL 0x320
#define HHI_VID_PLL_CNTL2 0x324
#define HHI_VID_PLL_CNTL3 0x328
#define HHI_VID_PLL_CNTL4 0x32c
#define HHI_VID_PLL_CNTL5 0x330
#define HHI_VID_PLL_CNTL6 0x334
#define HHI_VID2_PLL_CNTL 0x380
#define HHI_VID2_PLL_CNTL2 0x384
#define HHI_VID2_PLL_CNTL3 0x388
#define HHI_VID2_PLL_CNTL4 0x38c
#define HHI_VID2_PLL_CNTL5 0x390
#define HHI_VID2_PLL_CNTL6 0x394
/*
* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
* confirm these are the same for the S805.
*/
#define HHI_MPLL_CNTL 0x280
#define HHI_MPLL_CNTL2 0x284
#define HHI_MPLL_CNTL3 0x288
#define HHI_MPLL_CNTL4 0x28c
#define HHI_MPLL_CNTL5 0x290
#define HHI_MPLL_CNTL6 0x294
#define HHI_MPLL_CNTL7 0x298
#define HHI_MPLL_CNTL8 0x29c
#define HHI_MPLL_CNTL9 0x2a0
#define HHI_MPLL_CNTL10 0x2a4
struct meson8b_clk_reset {
struct reset_controller_dev reset;
struct regmap *regmap;
@@ -3407,202 +3472,6 @@ static struct clk_hw *meson8m2_hw_clks[] = {
[CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw,
};
static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_clk81,
&meson8b_ddr,
&meson8b_dos,
&meson8b_isa,
&meson8b_pl301,
&meson8b_periphs,
&meson8b_spicc,
&meson8b_i2c,
&meson8b_sar_adc,
&meson8b_smart_card,
&meson8b_rng0,
&meson8b_uart0,
&meson8b_sdhc,
&meson8b_stream,
&meson8b_async_fifo,
&meson8b_sdio,
&meson8b_abuf,
&meson8b_hiu_iface,
&meson8b_assist_misc,
&meson8b_spi,
&meson8b_i2s_spdif,
&meson8b_eth,
&meson8b_demux,
&meson8b_aiu_glue,
&meson8b_iec958,
&meson8b_i2s_out,
&meson8b_amclk,
&meson8b_aififo2,
&meson8b_mixer,
&meson8b_mixer_iface,
&meson8b_adc,
&meson8b_blkmv,
&meson8b_aiu,
&meson8b_uart1,
&meson8b_g2d,
&meson8b_usb0,
&meson8b_usb1,
&meson8b_reset,
&meson8b_nand,
&meson8b_dos_parser,
&meson8b_usb,
&meson8b_vdin1,
&meson8b_ahb_arb0,
&meson8b_efuse,
&meson8b_boot_rom,
&meson8b_ahb_data_bus,
&meson8b_ahb_ctrl_bus,
&meson8b_hdmi_intr_sync,
&meson8b_hdmi_pclk,
&meson8b_usb1_ddr_bridge,
&meson8b_usb0_ddr_bridge,
&meson8b_mmc_pclk,
&meson8b_dvin,
&meson8b_uart2,
&meson8b_sana,
&meson8b_vpu_intr,
&meson8b_sec_ahb_ahb3_bridge,
&meson8b_clk81_a9,
&meson8b_vclk2_venci0,
&meson8b_vclk2_venci1,
&meson8b_vclk2_vencp0,
&meson8b_vclk2_vencp1,
&meson8b_gclk_venci_int,
&meson8b_gclk_vencp_int,
&meson8b_dac_clk,
&meson8b_aoclk_gate,
&meson8b_iec958_gate,
&meson8b_enc480p,
&meson8b_rng1,
&meson8b_gclk_vencl_int,
&meson8b_vclk2_venclmcc,
&meson8b_vclk2_vencl,
&meson8b_vclk2_other,
&meson8b_edp,
&meson8b_ao_media_cpu,
&meson8b_ao_ahb_sram,
&meson8b_ao_ahb_bus,
&meson8b_ao_iface,
&meson8b_mpeg_clk_div,
&meson8b_mpeg_clk_sel,
&meson8b_mpll0,
&meson8b_mpll1,
&meson8b_mpll2,
&meson8b_mpll0_div,
&meson8b_mpll1_div,
&meson8b_mpll2_div,
&meson8b_fixed_pll,
&meson8b_sys_pll,
&meson8b_cpu_in_sel,
&meson8b_cpu_scale_div,
&meson8b_cpu_scale_out_sel,
&meson8b_cpu_clk,
&meson8b_mpll_prediv,
&meson8b_fclk_div2,
&meson8b_fclk_div3,
&meson8b_fclk_div4,
&meson8b_fclk_div5,
&meson8b_fclk_div7,
&meson8b_nand_clk_sel,
&meson8b_nand_clk_div,
&meson8b_nand_clk_gate,
&meson8b_fixed_pll_dco,
&meson8b_hdmi_pll_dco,
&meson8b_sys_pll_dco,
&meson8b_apb_clk_sel,
&meson8b_apb_clk_gate,
&meson8b_periph_clk_sel,
&meson8b_periph_clk_gate,
&meson8b_axi_clk_sel,
&meson8b_axi_clk_gate,
&meson8b_l2_dram_clk_sel,
&meson8b_l2_dram_clk_gate,
&meson8b_hdmi_pll_lvds_out,
&meson8b_hdmi_pll_hdmi_out,
&meson8b_vid_pll_in_sel,
&meson8b_vid_pll_in_en,
&meson8b_vid_pll_pre_div,
&meson8b_vid_pll_post_div,
&meson8b_vid_pll,
&meson8b_vid_pll_final_div,
&meson8b_vclk_in_sel,
&meson8b_vclk_in_en,
&meson8b_vclk_en,
&meson8b_vclk_div1_gate,
&meson8b_vclk_div2_div_gate,
&meson8b_vclk_div4_div_gate,
&meson8b_vclk_div6_div_gate,
&meson8b_vclk_div12_div_gate,
&meson8b_vclk2_in_sel,
&meson8b_vclk2_clk_in_en,
&meson8b_vclk2_clk_en,
&meson8b_vclk2_div1_gate,
&meson8b_vclk2_div2_div_gate,
&meson8b_vclk2_div4_div_gate,
&meson8b_vclk2_div6_div_gate,
&meson8b_vclk2_div12_div_gate,
&meson8b_cts_enct_sel,
&meson8b_cts_enct,
&meson8b_cts_encp_sel,
&meson8b_cts_encp,
&meson8b_cts_enci_sel,
&meson8b_cts_enci,
&meson8b_hdmi_tx_pixel_sel,
&meson8b_hdmi_tx_pixel,
&meson8b_cts_encl_sel,
&meson8b_cts_encl,
&meson8b_cts_vdac0_sel,
&meson8b_cts_vdac0,
&meson8b_hdmi_sys_sel,
&meson8b_hdmi_sys_div,
&meson8b_hdmi_sys,
&meson8b_mali_0_sel,
&meson8b_mali_0_div,
&meson8b_mali_0,
&meson8b_mali_1_sel,
&meson8b_mali_1_div,
&meson8b_mali_1,
&meson8b_mali,
&meson8m2_gp_pll_dco,
&meson8m2_gp_pll,
&meson8b_vpu_0_sel,
&meson8m2_vpu_0_sel,
&meson8b_vpu_0_div,
&meson8b_vpu_0,
&meson8b_vpu_1_sel,
&meson8m2_vpu_1_sel,
&meson8b_vpu_1_div,
&meson8b_vpu_1,
&meson8b_vpu,
&meson8b_vdec_1_sel,
&meson8b_vdec_1_1_div,
&meson8b_vdec_1_1,
&meson8b_vdec_1_2_div,
&meson8b_vdec_1_2,
&meson8b_vdec_1,
&meson8b_vdec_hcodec_sel,
&meson8b_vdec_hcodec_div,
&meson8b_vdec_hcodec,
&meson8b_vdec_2_sel,
&meson8b_vdec_2_div,
&meson8b_vdec_2,
&meson8b_vdec_hevc_sel,
&meson8b_vdec_hevc_div,
&meson8b_vdec_hevc_en,
&meson8b_vdec_hevc,
&meson8b_cts_amclk,
&meson8b_cts_amclk_sel,
&meson8b_cts_amclk_div,
&meson8b_cts_mclk_i958_sel,
&meson8b_cts_mclk_i958_div,
&meson8b_cts_mclk_i958,
&meson8b_cts_i958,
&meson8b_vid_pll_lvds_en,
};
static const struct meson8b_clk_reset_line {
u32 reg;
u8 bit_idx;
@@ -3819,10 +3688,6 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
return;
}
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
meson8b_clk_regmaps[i]->map = map;
/*
* register all clks and start with the first used ID (which is
* CLKID_PLL_FIXED)

80
drivers/clk/meson/meson8b.h
View File

@@ -1,80 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Endless Mobile, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
*
* Copyright (c) 2016 BayLibre, Inc.
* Michael Turquette <mturquette@baylibre.com>
*/
#ifndef __MESON8B_H
#define __MESON8B_H
/*
* Clock controller register offsets
*
* Register offsets from the HardKernel[0] data sheet are listed in comment
* blocks below. Those offsets must be multiplied by 4 before adding them to
* the base address to get the right value
*
* [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
*/
#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
#define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
#define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
#define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */
#define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */
#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */
#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */
#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */
#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */
#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */
#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */
/*
* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
* confirm these are the same for the S805.
*/
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */
#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */
#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
#endif /* __MESON8B_H */

388
drivers/clk/meson/s4-peripherals.c
View File

@@ -13,10 +13,55 @@
#include "clk-regmap.h"
#include "vid-pll-div.h"
#include "clk-dualdiv.h"
#include "s4-peripherals.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008
#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c
#define CLKCTRL_RTC_CTRL 0x010
#define CLKCTRL_SYS_CLK_CTRL0 0x040
#define CLKCTRL_SYS_CLK_EN0_REG0 0x044
#define CLKCTRL_SYS_CLK_EN0_REG1 0x048
#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c
#define CLKCTRL_SYS_CLK_EN0_REG3 0x050
#define CLKCTRL_CECA_CTRL0 0x088
#define CLKCTRL_CECA_CTRL1 0x08c
#define CLKCTRL_CECB_CTRL0 0x090
#define CLKCTRL_CECB_CTRL1 0x094
#define CLKCTRL_SC_CLK_CTRL 0x098
#define CLKCTRL_CLK12_24_CTRL 0x0a8
#define CLKCTRL_VID_CLK_CTRL 0x0c0
#define CLKCTRL_VID_CLK_CTRL2 0x0c4
#define CLKCTRL_VID_CLK_DIV 0x0c8
#define CLKCTRL_VIID_CLK_DIV 0x0cc
#define CLKCTRL_VIID_CLK_CTRL 0x0d0
#define CLKCTRL_HDMI_CLK_CTRL 0x0e0
#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4
#define CLKCTRL_VPU_CLK_CTRL 0x0e8
#define CLKCTRL_VPU_CLKB_CTRL 0x0ec
#define CLKCTRL_VPU_CLKC_CTRL 0x0f0
#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4
#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
#define CLKCTRL_VAPBCLK_CTRL 0x0fc
#define CLKCTRL_HDCP22_CTRL 0x100
#define CLKCTRL_VDEC_CLK_CTRL 0x140
#define CLKCTRL_VDEC2_CLK_CTRL 0x144
#define CLKCTRL_VDEC3_CLK_CTRL 0x148
#define CLKCTRL_VDEC4_CLK_CTRL 0x14c
#define CLKCTRL_TS_CLK_CTRL 0x158
#define CLKCTRL_MALI_CLK_CTRL 0x15c
#define CLKCTRL_NAND_CLK_CTRL 0x168
#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c
#define CLKCTRL_SPICC_CLK_CTRL 0x174
#define CLKCTRL_GEN_CLK_CTRL 0x178
#define CLKCTRL_SAR_CLK_CTRL 0x17c
#define CLKCTRL_PWM_CLK_AB_CTRL 0x180
#define CLKCTRL_PWM_CLK_CD_CTRL 0x184
#define CLKCTRL_PWM_CLK_EF_CTRL 0x188
#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c
#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190
#define CLKCTRL_DEMOD_CLK_CTRL 0x200
static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
.data = &(struct clk_regmap_gate_data){
.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
@@ -3129,118 +3174,6 @@ static struct clk_regmap s4_gen_clk = {
},
};
static const struct clk_parent_data s4_adc_extclk_in_parent_data[] = {
{ .fw_name = "xtal", },
{ .fw_name = "fclk_div4", },
{ .fw_name = "fclk_div3", },
{ .fw_name = "fclk_div5", },
{ .fw_name = "fclk_div7", },
{ .fw_name = "mpll2", },
{ .fw_name = "gp0_pll", },
{ .fw_name = "hifi_pll", },
};
static struct clk_regmap s4_adc_extclk_in_mux = {
.data = &(struct clk_regmap_mux_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.mask = 0x7,
.shift = 25,
},
.hw.init = &(struct clk_init_data){
.name = "adc_extclk_in_mux",
.ops = &clk_regmap_mux_ops,
.parent_data = s4_adc_extclk_in_parent_data,
.num_parents = ARRAY_SIZE(s4_adc_extclk_in_parent_data),
.flags = 0,
},
};
static struct clk_regmap s4_adc_extclk_in_div = {
.data = &(struct clk_regmap_div_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.shift = 16,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "adc_extclk_in_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_adc_extclk_in_mux.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_adc_extclk_in_gate = {
.data = &(struct clk_regmap_gate_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data){
.name = "adc_extclk_in",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_adc_extclk_in_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_demod_core_clk_mux = {
.data = &(struct clk_regmap_mux_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.mask = 0x3,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "demod_core_clk_mux",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .fw_name = "fclk_div7", },
{ .fw_name = "fclk_div4", },
{ .hw = &s4_adc_extclk_in_gate.hw }
},
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_demod_core_clk_div = {
.data = &(struct clk_regmap_div_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.shift = 0,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "demod_core_clk_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_demod_core_clk_mux.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_demod_core_clk_gate = {
.data = &(struct clk_regmap_gate_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data){
.name = "demod_core_clk",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_demod_core_clk_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
#define MESON_GATE(_name, _reg, _bit) \
MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)
@@ -3522,231 +3455,6 @@ static struct clk_hw *s4_periphs_hw_clks[] = {
[CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk_gate.hw,
};
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const s4_periphs_clk_regmaps[] = {
&s4_rtc_32k_by_oscin_clkin,
&s4_rtc_32k_by_oscin_div,
&s4_rtc_32k_by_oscin_sel,
&s4_rtc_32k_by_oscin,
&s4_rtc_clk,
&s4_sysclk_b_sel,
&s4_sysclk_b_div,
&s4_sysclk_b,
&s4_sysclk_a_sel,
&s4_sysclk_a_div,
&s4_sysclk_a,
&s4_sys_clk,
&s4_ceca_32k_clkin,
&s4_ceca_32k_div,
&s4_ceca_32k_sel_pre,
&s4_ceca_32k_sel,
&s4_ceca_32k_clkout,
&s4_cecb_32k_clkin,
&s4_cecb_32k_div,
&s4_cecb_32k_sel_pre,
&s4_cecb_32k_sel,
&s4_cecb_32k_clkout,
&s4_sc_clk_mux,
&s4_sc_clk_div,
&s4_sc_clk_gate,
&s4_12_24M_clk_gate,
&s4_12_24M_clk,
&s4_vid_pll_div,
&s4_vid_pll_sel,
&s4_vid_pll,
&s4_vclk_sel,
&s4_vclk2_sel,
&s4_vclk_input,
&s4_vclk2_input,
&s4_vclk_div,
&s4_vclk2_div,
&s4_vclk,
&s4_vclk2,
&s4_vclk_div1,
&s4_vclk_div2_en,
&s4_vclk_div4_en,
&s4_vclk_div6_en,
&s4_vclk_div12_en,
&s4_vclk2_div1,
&s4_vclk2_div2_en,
&s4_vclk2_div4_en,
&s4_vclk2_div6_en,
&s4_vclk2_div12_en,
&s4_cts_enci_sel,
&s4_cts_encp_sel,
&s4_cts_vdac_sel,
&s4_hdmi_tx_sel,
&s4_cts_enci,
&s4_cts_encp,
&s4_cts_vdac,
&s4_hdmi_tx,
&s4_hdmi_sel,
&s4_hdmi_div,
&s4_hdmi,
&s4_ts_clk_div,
&s4_ts_clk_gate,
&s4_mali_0_sel,
&s4_mali_0_div,
&s4_mali_0,
&s4_mali_1_sel,
&s4_mali_1_div,
&s4_mali_1,
&s4_mali_mux,
&s4_vdec_p0_mux,
&s4_vdec_p0_div,
&s4_vdec_p0,
&s4_vdec_p1_mux,
&s4_vdec_p1_div,
&s4_vdec_p1,
&s4_vdec_mux,
&s4_hevcf_p0_mux,
&s4_hevcf_p0_div,
&s4_hevcf_p0,
&s4_hevcf_p1_mux,
&s4_hevcf_p1_div,
&s4_hevcf_p1,
&s4_hevcf_mux,
&s4_vpu_0_sel,
&s4_vpu_0_div,
&s4_vpu_0,
&s4_vpu_1_sel,
&s4_vpu_1_div,
&s4_vpu_1,
&s4_vpu,
&s4_vpu_clkb_tmp_mux,
&s4_vpu_clkb_tmp_div,
&s4_vpu_clkb_tmp,
&s4_vpu_clkb_div,
&s4_vpu_clkb,
&s4_vpu_clkc_p0_mux,
&s4_vpu_clkc_p0_div,
&s4_vpu_clkc_p0,
&s4_vpu_clkc_p1_mux,
&s4_vpu_clkc_p1_div,
&s4_vpu_clkc_p1,
&s4_vpu_clkc_mux,
&s4_vapb_0_sel,
&s4_vapb_0_div,
&s4_vapb_0,
&s4_vapb_1_sel,
&s4_vapb_1_div,
&s4_vapb_1,
&s4_vapb,
&s4_ge2d_gate,
&s4_hdcp22_esmclk_mux,
&s4_hdcp22_esmclk_div,
&s4_hdcp22_esmclk_gate,
&s4_hdcp22_skpclk_mux,
&s4_hdcp22_skpclk_div,
&s4_hdcp22_skpclk_gate,
&s4_vdin_meas_mux,
&s4_vdin_meas_div,
&s4_vdin_meas_gate,
&s4_sd_emmc_c_clk0_sel,
&s4_sd_emmc_c_clk0_div,
&s4_sd_emmc_c_clk0,
&s4_sd_emmc_a_clk0_sel,
&s4_sd_emmc_a_clk0_div,
&s4_sd_emmc_a_clk0,
&s4_sd_emmc_b_clk0_sel,
&s4_sd_emmc_b_clk0_div,
&s4_sd_emmc_b_clk0,
&s4_spicc0_mux,
&s4_spicc0_div,
&s4_spicc0_gate,
&s4_pwm_a_mux,
&s4_pwm_a_div,
&s4_pwm_a_gate,
&s4_pwm_b_mux,
&s4_pwm_b_div,
&s4_pwm_b_gate,
&s4_pwm_c_mux,
&s4_pwm_c_div,
&s4_pwm_c_gate,
&s4_pwm_d_mux,
&s4_pwm_d_div,
&s4_pwm_d_gate,
&s4_pwm_e_mux,
&s4_pwm_e_div,
&s4_pwm_e_gate,
&s4_pwm_f_mux,
&s4_pwm_f_div,
&s4_pwm_f_gate,
&s4_pwm_g_mux,
&s4_pwm_g_div,
&s4_pwm_g_gate,
&s4_pwm_h_mux,
&s4_pwm_h_div,
&s4_pwm_h_gate,
&s4_pwm_i_mux,
&s4_pwm_i_div,
&s4_pwm_i_gate,
&s4_pwm_j_mux,
&s4_pwm_j_div,
&s4_pwm_j_gate,
&s4_saradc_mux,
&s4_saradc_div,
&s4_saradc_gate,
&s4_gen_clk_sel,
&s4_gen_clk_div,
&s4_gen_clk,
&s4_ddr,
&s4_dos,
&s4_ethphy,
&s4_mali,
&s4_aocpu,
&s4_aucpu,
&s4_cec,
&s4_sdemmca,
&s4_sdemmcb,
&s4_nand,
&s4_smartcard,
&s4_acodec,
&s4_spifc,
&s4_msr_clk,
&s4_ir_ctrl,
&s4_audio,
&s4_eth,
&s4_uart_a,
&s4_uart_b,
&s4_uart_c,
&s4_uart_d,
&s4_uart_e,
&s4_aififo,
&s4_ts_ddr,
&s4_ts_pll,
&s4_g2d,
&s4_spicc0,
&s4_usb,
&s4_i2c_m_a,
&s4_i2c_m_b,
&s4_i2c_m_c,
&s4_i2c_m_d,
&s4_i2c_m_e,
&s4_hdmitx_apb,
&s4_i2c_s_a,
&s4_usb1_to_ddr,
&s4_hdcp22,
&s4_mmc_apb,
&s4_rsa,
&s4_cpu_debug,
&s4_vpu_intr,
&s4_demod,
&s4_sar_adc,
&s4_gic,
&s4_pwm_ab,
&s4_pwm_cd,
&s4_pwm_ef,
&s4_pwm_gh,
&s4_pwm_ij,
&s4_demod_core_clk_mux,
&s4_demod_core_clk_div,
&s4_demod_core_clk_gate,
&s4_adc_extclk_in_mux,
&s4_adc_extclk_in_div,
&s4_adc_extclk_in_gate,
};
static const struct regmap_config clkc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -3776,10 +3484,6 @@ static int meson_s4_periphs_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(regmap),
"can't init regmap mmio region\n");
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(s4_periphs_clk_regmaps); i++)
s4_periphs_clk_regmaps[i]->map = regmap;
for (i = 0; i < s4_periphs_clks.num; i++) {
/* array might be sparse */
if (!s4_periphs_clks.hws[i])

56
drivers/clk/meson/s4-peripherals.h
View File

@@ -1,56 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
* Author: Yu Tu <yu.tu@amlogic.com>
*/
#ifndef __MESON_S4_PERIPHERALS_H__
#define __MESON_S4_PERIPHERALS_H__
#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008
#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c
#define CLKCTRL_RTC_CTRL 0x010
#define CLKCTRL_SYS_CLK_CTRL0 0x040
#define CLKCTRL_SYS_CLK_EN0_REG0 0x044
#define CLKCTRL_SYS_CLK_EN0_REG1 0x048
#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c
#define CLKCTRL_SYS_CLK_EN0_REG3 0x050
#define CLKCTRL_CECA_CTRL0 0x088
#define CLKCTRL_CECA_CTRL1 0x08c
#define CLKCTRL_CECB_CTRL0 0x090
#define CLKCTRL_CECB_CTRL1 0x094
#define CLKCTRL_SC_CLK_CTRL 0x098
#define CLKCTRL_CLK12_24_CTRL 0x0a8
#define CLKCTRL_VID_CLK_CTRL 0x0c0
#define CLKCTRL_VID_CLK_CTRL2 0x0c4
#define CLKCTRL_VID_CLK_DIV 0x0c8
#define CLKCTRL_VIID_CLK_DIV 0x0cc
#define CLKCTRL_VIID_CLK_CTRL 0x0d0
#define CLKCTRL_HDMI_CLK_CTRL 0x0e0
#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4
#define CLKCTRL_VPU_CLK_CTRL 0x0e8
#define CLKCTRL_VPU_CLKB_CTRL 0x0ec
#define CLKCTRL_VPU_CLKC_CTRL 0x0f0
#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4
#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
#define CLKCTRL_VAPBCLK_CTRL 0x0fc
#define CLKCTRL_HDCP22_CTRL 0x100
#define CLKCTRL_VDEC_CLK_CTRL 0x140
#define CLKCTRL_VDEC2_CLK_CTRL 0x144
#define CLKCTRL_VDEC3_CLK_CTRL 0x148
#define CLKCTRL_VDEC4_CLK_CTRL 0x14c
#define CLKCTRL_TS_CLK_CTRL 0x158
#define CLKCTRL_MALI_CLK_CTRL 0x15c
#define CLKCTRL_NAND_CLK_CTRL 0x168
#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c
#define CLKCTRL_SPICC_CLK_CTRL 0x174
#define CLKCTRL_GEN_CLK_CTRL 0x178
#define CLKCTRL_SAR_CLK_CTRL 0x17c
#define CLKCTRL_PWM_CLK_AB_CTRL 0x180
#define CLKCTRL_PWM_CLK_CD_CTRL 0x184
#define CLKCTRL_PWM_CLK_EF_CTRL 0x188
#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c
#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190
#define CLKCTRL_DEMOD_CLK_CTRL 0x200
#endif /* __MESON_S4_PERIPHERALS_H__ */

60
drivers/clk/meson/s4-pll.c
View File

@@ -13,10 +13,37 @@
#include "clk-mpll.h"
#include "clk-pll.h"
#include "clk-regmap.h"
#include "s4-pll.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
#define ANACTRL_FIXPLL_CTRL0 0x040
#define ANACTRL_FIXPLL_CTRL1 0x044
#define ANACTRL_FIXPLL_CTRL3 0x04c
#define ANACTRL_GP0PLL_CTRL0 0x080
#define ANACTRL_GP0PLL_CTRL1 0x084
#define ANACTRL_GP0PLL_CTRL2 0x088
#define ANACTRL_GP0PLL_CTRL3 0x08c
#define ANACTRL_GP0PLL_CTRL4 0x090
#define ANACTRL_GP0PLL_CTRL5 0x094
#define ANACTRL_GP0PLL_CTRL6 0x098
#define ANACTRL_HIFIPLL_CTRL0 0x100
#define ANACTRL_HIFIPLL_CTRL1 0x104
#define ANACTRL_HIFIPLL_CTRL2 0x108
#define ANACTRL_HIFIPLL_CTRL3 0x10c
#define ANACTRL_HIFIPLL_CTRL4 0x110
#define ANACTRL_HIFIPLL_CTRL5 0x114
#define ANACTRL_HIFIPLL_CTRL6 0x118
#define ANACTRL_MPLL_CTRL0 0x180
#define ANACTRL_MPLL_CTRL1 0x184
#define ANACTRL_MPLL_CTRL2 0x188
#define ANACTRL_MPLL_CTRL3 0x18c
#define ANACTRL_MPLL_CTRL4 0x190
#define ANACTRL_MPLL_CTRL5 0x194
#define ANACTRL_MPLL_CTRL6 0x198
#define ANACTRL_MPLL_CTRL7 0x19c
#define ANACTRL_MPLL_CTRL8 0x1a0
#define ANACTRL_HDMIPLL_CTRL0 0x1c0
/*
* These clock are a fixed value (fixed_pll is 2GHz) that is initialized by ROMcode.
* The chip was changed fixed pll for security reasons. Fixed PLL registers are not writable
@@ -767,33 +794,6 @@ static struct clk_hw *s4_pll_hw_clks[] = {
[CLKID_MPLL3] = &s4_mpll3.hw,
};
static struct clk_regmap *const s4_pll_clk_regmaps[] = {
&s4_fixed_pll_dco,
&s4_fixed_pll,
&s4_fclk_div2,
&s4_fclk_div3,
&s4_fclk_div4,
&s4_fclk_div5,
&s4_fclk_div7,
&s4_fclk_div2p5,
&s4_gp0_pll_dco,
&s4_gp0_pll,
&s4_hifi_pll_dco,
&s4_hifi_pll,
&s4_hdmi_pll_dco,
&s4_hdmi_pll_od,
&s4_hdmi_pll,
&s4_mpll_50m,
&s4_mpll0_div,
&s4_mpll0,
&s4_mpll1_div,
&s4_mpll1,
&s4_mpll2_div,
&s4_mpll2,
&s4_mpll3_div,
&s4_mpll3,
};
static const struct reg_sequence s4_init_regs[] = {
{ .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
};
@@ -832,10 +832,6 @@ static int meson_s4_pll_probe(struct platform_device *pdev)
return dev_err_probe(dev, ret,
"Failed to init registers\n");
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
s4_pll_clk_regmaps[i]->map = regmap;
/* Register clocks */
for (i = 0; i < s4_pll_clks.num; i++) {
/* array might be sparse */

38
drivers/clk/meson/s4-pll.h
View File

@@ -1,38 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
* Author: Yu Tu <yu.tu@amlogic.com>
*/
#ifndef __MESON_S4_PLL_H__
#define __MESON_S4_PLL_H__
#define ANACTRL_FIXPLL_CTRL0 0x040
#define ANACTRL_FIXPLL_CTRL1 0x044
#define ANACTRL_FIXPLL_CTRL3 0x04c
#define ANACTRL_GP0PLL_CTRL0 0x080
#define ANACTRL_GP0PLL_CTRL1 0x084
#define ANACTRL_GP0PLL_CTRL2 0x088
#define ANACTRL_GP0PLL_CTRL3 0x08c
#define ANACTRL_GP0PLL_CTRL4 0x090
#define ANACTRL_GP0PLL_CTRL5 0x094
#define ANACTRL_GP0PLL_CTRL6 0x098
#define ANACTRL_HIFIPLL_CTRL0 0x100
#define ANACTRL_HIFIPLL_CTRL1 0x104
#define ANACTRL_HIFIPLL_CTRL2 0x108
#define ANACTRL_HIFIPLL_CTRL3 0x10c
#define ANACTRL_HIFIPLL_CTRL4 0x110
#define ANACTRL_HIFIPLL_CTRL5 0x114
#define ANACTRL_HIFIPLL_CTRL6 0x118
#define ANACTRL_MPLL_CTRL0 0x180
#define ANACTRL_MPLL_CTRL1 0x184
#define ANACTRL_MPLL_CTRL2 0x188
#define ANACTRL_MPLL_CTRL3 0x18c
#define ANACTRL_MPLL_CTRL4 0x190
#define ANACTRL_MPLL_CTRL5 0x194
#define ANACTRL_MPLL_CTRL6 0x198
#define ANACTRL_MPLL_CTRL7 0x19c
#define ANACTRL_MPLL_CTRL8 0x1a0
#define ANACTRL_HDMIPLL_CTRL0 0x1c0
#endif /* __MESON_S4_PLL_H__ */

5
drivers/clk/meson/sclk-div.c
View File

@@ -222,6 +222,11 @@ static int sclk_div_init(struct clk_hw *hw)
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
unsigned int val;
int ret;
ret = clk_regmap_init(hw);
if (ret)
return ret;
val = meson_parm_read(clk->map, &sclk->div);

2
drivers/clk/meson/vclk.c
View File

@@ -45,6 +45,7 @@ static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
}
const struct clk_ops meson_vclk_gate_ops = {
.init = clk_regmap_init,
.enable = meson_vclk_gate_enable,
.disable = meson_vclk_gate_disable,
.is_enabled = meson_vclk_gate_is_enabled,
@@ -127,6 +128,7 @@ static int meson_vclk_div_is_enabled(struct clk_hw *hw)
}
const struct clk_ops meson_vclk_div_ops = {
.init = clk_regmap_init,
.recalc_rate = meson_vclk_div_recalc_rate,
.determine_rate = meson_vclk_div_determine_rate,
.set_rate = meson_vclk_div_set_rate,

1
drivers/clk/meson/vid-pll-div.c
View File

@@ -90,6 +90,7 @@ static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw,
}
const struct clk_ops meson_vid_pll_div_ro_ops = {
.init = clk_regmap_init,
.recalc_rate = meson_vid_pll_div_recalc_rate,
};
EXPORT_SYMBOL_NS_GPL(meson_vid_pll_div_ro_ops, "CLK_MESON");

10
drivers/clk/renesas/Kconfig
View File

@@ -43,6 +43,8 @@ config CLK_RENESAS
select CLK_R9A09G047 if ARCH_R9A09G047
select CLK_R9A09G056 if ARCH_R9A09G056
select CLK_R9A09G057 if ARCH_R9A09G057
select CLK_R9A09G077 if ARCH_R9A09G077
select CLK_R9A09G087 if ARCH_R9A09G087
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@@ -208,6 +210,14 @@ config CLK_R9A09G057
bool "RZ/V2H(P) clock support" if COMPILE_TEST
select CLK_RZV2H
config CLK_R9A09G077
bool "RZ/T2H clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSSR
config CLK_R9A09G087
bool "RZ/N2H clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSSR
config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP

2
drivers/clk/renesas/Makefile
View File

@@ -40,6 +40,8 @@ obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
obj-$(CONFIG_CLK_R9A09G077) += r9a09g077-cpg.o
obj-$(CONFIG_CLK_R9A09G087) += r9a09g077-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
# Family

7
drivers/clk/renesas/r7s9210-cpg-mssr.c
View File

@@ -159,12 +159,13 @@ static void __init r7s9210_update_clk_table(struct clk *extal_clk,
static struct clk * __init rza2_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers)
struct cpg_mssr_pub *pub)
{
struct clk *parent;
void __iomem *base = pub->base0;
struct clk **clks = pub->clks;
unsigned int mult = 1;
unsigned int div = 1;
struct clk *parent;
parent = clks[core->parent];
if (IS_ERR(parent))

8
drivers/clk/renesas/r8a77970-cpg-mssr.c
View File

@@ -219,10 +219,11 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev)
static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers)
struct cpg_mssr_pub *pub)
{
const struct clk_div_table *table;
void __iomem *base = pub->base0;
struct clk **clks = pub->clks;
const struct clk *parent;
unsigned int shift;
@@ -236,8 +237,7 @@ static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
shift = 4;
break;
default:
return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
notifiers);
return rcar_gen3_cpg_clk_register(dev, core, info, pub);
}
parent = clks[core->parent];

132
drivers/clk/renesas/r9a07g043-cpg.c
View File

@@ -164,143 +164,143 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
#ifdef CONFIG_ARM64
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
0x514, 0),
0x514, 0, 0),
DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
0x518, 0),
0x518, 0, 0),
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
0x518, 1),
0x518, 1, 0),
#endif
#ifdef CONFIG_RISCV
DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
0x518, 0),
0x518, 0, 0),
DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
0x518, 1),
0x518, 1, 0),
#endif
DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
0x52c, 0),
0x52c, 0, 0),
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
0x52c, 1),
0x52c, 1, 0),
DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
0x534, 0),
0x534, 0, 0),
DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
0x534, 1),
0x534, 1, 0),
DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
0x534, 2),
0x534, 2, 0),
DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,
0x538, 0),
0x538, 0, 0),
DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
0x548, 0),
0x548, 0, 0),
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
0x548, 1),
0x548, 1, 0),
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
0x550, 0),
0x550, 0, 0),
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
0x550, 1),
0x550, 1, 0),
DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
0x554, 0),
0x554, 0, 0),
DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
0x554, 1),
0x554, 1, 0),
DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,
0x554, 2),
0x554, 2, 0),
DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,
0x554, 3),
0x554, 3, 0),
DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,
0x554, 4),
0x554, 4, 0),
DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,
0x554, 5),
0x554, 5, 0),
DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,
0x554, 6),
0x554, 6, 0),
DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
0x554, 7),
0x554, 7, 0),
#ifdef CONFIG_ARM64
DEF_MOD("cru_sysclk", R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,
0x564, 0),
0x564, 0, 0),
DEF_MOD("cru_vclk", R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,
0x564, 1),
0x564, 1, 0),
DEF_MOD("cru_pclk", R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,
0x564, 2),
0x564, 2, 0),
DEF_MOD("cru_aclk", R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,
0x564, 3),
0x564, 3, 0),
DEF_COUPLED("lcdc_clk_a", R9A07G043_LCDC_CLK_A, R9A07G043_CLK_M0,
0x56c, 0),
0x56c, 0, 0),
DEF_COUPLED("lcdc_clk_p", R9A07G043_LCDC_CLK_P, R9A07G043_CLK_ZT,
0x56c, 0),
0x56c, 0, 0),
DEF_MOD("lcdc_clk_d", R9A07G043_LCDC_CLK_D, R9A07G043_CLK_M3,
0x56c, 1),
0x56c, 1, 0),
#endif
DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
0x570, 0),
0x570, 0, 0),
DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
0x570, 1),
0x570, 1, 0),
DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
0x570, 2),
0x570, 2, 0),
DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
0x570, 3),
0x570, 3, 0),
DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
0x570, 4),
0x570, 4, 0),
DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
0x570, 5),
0x570, 5, 0),
DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
0x570, 6),
0x570, 6, 0),
DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
0x570, 7),
0x570, 7, 0),
DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
0x578, 0),
0x578, 0, 0),
DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
0x578, 1),
0x578, 1, 0),
DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
0x578, 2),
0x578, 2, 0),
DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
0x578, 3),
0x578, 3, 0),
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
0x57c, 0),
0x57c, 0, 0),
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
0x57c, 0),
0x57c, 0, 0),
DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
0x57c, 1),
0x57c, 1, 0),
DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
0x57c, 1),
0x57c, 1, 0),
DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,
0x580, 0),
0x580, 0, 0),
DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,
0x580, 1),
0x580, 1, 0),
DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,
0x580, 2),
0x580, 2, 0),
DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,
0x580, 3),
0x580, 3, 0),
DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
0x584, 0),
0x584, 0, 0),
DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
0x584, 1),
0x584, 1, 0),
DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
0x584, 2),
0x584, 2, 0),
DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
0x584, 3),
0x584, 3, 0),
DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
0x584, 4),
0x584, 4, 0),
DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
0x588, 0),
0x588, 0, 0),
DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
0x588, 1),
0x588, 1, 0),
DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,
0x590, 0),
0x590, 0, 0),
DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,
0x590, 1),
0x590, 1, 0),
DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,
0x590, 2),
0x590, 2, 0),
DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
0x594, 0),
0x594, 0, 0),
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
0x598, 0),
0x598, 0, 0),
DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
0x5a8, 0),
0x5a8, 0, 0),
DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,
0x5a8, 1),
0x5a8, 1, 0),
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
0x5ac, 0),
0x5ac, 0, 0),
#ifdef CONFIG_RISCV
DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
0x608, 0),
0x608, 0, 0),
#endif
};

168
drivers/clk/renesas/r9a07g044-cpg.c
View File

@@ -242,176 +242,176 @@ static const struct {
} mod_clks = {
.common = {
DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
0x514, 0),
0x514, 0, 0),
DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
0x518, 0),
0x518, 0, 0),
DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
0x518, 1),
0x518, 1, 0),
DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
0x52c, 0),
0x52c, 0, 0),
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
0x52c, 1),
0x52c, 1, 0),
DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
0x534, 0),
0x534, 0, 0),
DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
0x534, 1),
0x534, 1, 0),
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
0x534, 2),
0x534, 2, 0),
DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
0x538, 0),
0x538, 0, 0),
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
0x540, 0),
0x540, 0, 0),
DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
0x544, 0),
0x544, 0, 0),
DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
0x544, 1),
0x544, 1, 0),
DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
0x544, 2),
0x544, 2, 0),
DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
0x544, 3),
0x544, 3, 0),
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
0x548, 0),
0x548, 0, 0),
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
0x548, 1),
0x548, 1, 0),
DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
0x548, 2),
0x548, 2, 0),
DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
0x548, 3),
0x548, 3, 0),
DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
0x550, 0),
0x550, 0, 0),
DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
0x550, 1),
0x550, 1, 0),
DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
0x554, 0),
0x554, 0, 0),
DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
0x554, 1),
0x554, 1, 0),
DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
0x554, 2),
0x554, 2, 0),
DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
0x554, 3),
0x554, 3, 0),
DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
0x554, 4),
0x554, 4, 0),
DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
0x554, 5),
0x554, 5, 0),
DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
0x554, 6),
0x554, 6, 0),
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
0x554, 7),
0x554, 7, 0),
DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
0x558, 0),
0x558, 0, 0),
DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
0x558, 1),
0x558, 1, 0),
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
0x558, 2),
0x558, 2, 0),
DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
0x564, 0),
0x564, 0, 0),
DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
0x564, 1),
0x564, 1, 0),
DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
0x564, 2),
0x564, 2, 0),
DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
0x564, 3),
0x564, 3, 0),
DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
0x568, 0),
0x568, 0, 0),
DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
0x568, 1),
0x568, 1, 0),
DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
0x568, 2),
0x568, 2, 0),
DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
0x568, 3),
0x568, 3, 0),
DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
0x568, 4),
0x568, 4, 0),
DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
0x568, 5),
0x568, 5, 0),
DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
0x56c, 0),
0x56c, 0, 0),
DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
0x56c, 0),
0x56c, 0, 0),
DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
0x56c, 1),
0x56c, 1, 0),
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
0x570, 0),
0x570, 0, 0),
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 1),
0x570, 1, 0),
DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
0x570, 2),
0x570, 2, 0),
DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 3),
0x570, 3, 0),
DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
0x570, 4),
0x570, 4, 0),
DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 5),
0x570, 5, 0),
DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
0x570, 6),
0x570, 6, 0),
DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
0x570, 7),
0x570, 7, 0),
DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
0x578, 0),
0x578, 0, 0),
DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
0x578, 1),
0x578, 1, 0),
DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
0x578, 2),
0x578, 2, 0),
DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
0x578, 3),
0x578, 3, 0),
DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
0x57c, 0),
0x57c, 0, 0),
DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
0x57c, 0),
0x57c, 0, 0),
DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
0x57c, 1),
0x57c, 1, 0),
DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
0x57c, 1),
0x57c, 1, 0),
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
0x580, 0),
0x580, 0, 0),
DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
0x580, 1),
0x580, 1, 0),
DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
0x580, 2),
0x580, 2, 0),
DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
0x580, 3),
0x580, 3, 0),
DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
0x584, 0),
0x584, 0, 0),
DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
0x584, 1),
0x584, 1, 0),
DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
0x584, 2),
0x584, 2, 0),
DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
0x584, 3),
0x584, 3, 0),
DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
0x584, 4),
0x584, 4, 0),
DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
0x588, 0),
0x588, 0, 0),
DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
0x588, 1),
0x588, 1, 0),
DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
0x590, 0),
0x590, 0, 0),
DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
0x590, 1),
0x590, 1, 0),
DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
0x590, 2),
0x590, 2, 0),
DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
0x594, 0),
0x594, 0, 0),
DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
0x598, 0),
0x598, 0, 0),
DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
0x5a8, 0),
0x5a8, 0, 0),
DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
0x5a8, 1),
0x5a8, 1, 0),
DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
0x5ac, 0),
0x5ac, 0, 0),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK,
0x5e8, 0),
0x5e8, 0, 0),
DEF_MOD("stpai_aclk", R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1,
0x5e8, 1),
0x5e8, 1, 0),
DEF_MOD("stpai_mclk", R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M,
0x5e8, 2),
0x5e8, 2, 0),
DEF_MOD("stpai_dclkin", R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D,
0x5e8, 3),
0x5e8, 3, 0),
DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A,
0x5e8, 4),
0x5e8, 4, 0),
},
#endif
};

229
drivers/clk/renesas/r9a08g045-cpg.c
View File

@@ -192,58 +192,107 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
};
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1),
DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0),
DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1),
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1),
DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2),
DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3),
DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4),
DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5),
DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6),
DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7),
DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8),
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0),
DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1),
DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2),
DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3),
DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4),
DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5),
DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6),
DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7),
DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3),
DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1),
DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2),
DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3),
DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4),
DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5),
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),
DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0),
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0,
MSTOP(BUS_ACPU, BIT(3))),
DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0,
MSTOP(BUS_PERI_CPU, BIT(13))),
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1,
MSTOP(BUS_PERI_CPU, BIT(13))),
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0,
MSTOP(BUS_REG1, BIT(2))),
DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1,
MSTOP(BUS_REG1, BIT(3))),
DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0,
MSTOP(BUS_REG0, BIT(0))),
DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1,
MSTOP(BUS_REG0, BIT(0))),
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0,
MSTOP(BUS_PERI_COM, BIT(0))),
DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1,
MSTOP(BUS_PERI_COM, BIT(0))),
DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2,
MSTOP(BUS_PERI_COM, BIT(0))),
DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3,
MSTOP(BUS_PERI_COM, BIT(0))),
DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4,
MSTOP(BUS_PERI_COM, BIT(1))),
DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5,
MSTOP(BUS_PERI_COM, BIT(1))),
DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6,
MSTOP(BUS_PERI_COM, BIT(1))),
DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7,
MSTOP(BUS_PERI_COM, BIT(1))),
DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8,
MSTOP(BUS_PERI_COM, BIT(11))),
DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9,
MSTOP(BUS_PERI_COM, BIT(11))),
DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10,
MSTOP(BUS_PERI_COM, BIT(11))),
DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11,
MSTOP(BUS_PERI_COM, BIT(11))),
DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0,
MSTOP(BUS_MCPU1, BIT(10))),
DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1,
MSTOP(BUS_MCPU1, BIT(10))),
DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2,
MSTOP(BUS_MCPU1, BIT(11))),
DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3,
MSTOP(BUS_MCPU1, BIT(11))),
DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4,
MSTOP(BUS_MCPU1, BIT(12))),
DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5,
MSTOP(BUS_MCPU1, BIT(12))),
DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6,
MSTOP(BUS_MCPU1, BIT(13))),
DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7,
MSTOP(BUS_MCPU1, BIT(13))),
DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0,
MSTOP(BUS_PERI_COM, BIT(5))),
DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1,
MSTOP(BUS_PERI_COM, BIT(7))),
DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2,
MSTOP(BUS_PERI_COM, BIT(6))),
DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3,
MSTOP(BUS_PERI_COM, BIT(4))),
DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0,
MSTOP(BUS_PERI_COM, BIT(2))),
DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0,
MSTOP(BUS_PERI_COM, BIT(2))),
DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8, 0),
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1,
MSTOP(BUS_PERI_COM, BIT(3))),
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1,
MSTOP(BUS_PERI_COM, BIT(3))),
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9, 0),
DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0,
MSTOP(BUS_MCPU2, BIT(10))),
DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1,
MSTOP(BUS_MCPU2, BIT(11))),
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2,
MSTOP(BUS_MCPU2, BIT(12))),
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3,
MSTOP(BUS_MCPU2, BIT(13))),
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0,
MSTOP(BUS_MCPU2, BIT(1))),
DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1,
MSTOP(BUS_MCPU2, BIT(2))),
DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2,
MSTOP(BUS_MCPU2, BIT(3))),
DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3,
MSTOP(BUS_MCPU2, BIT(4))),
DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4,
MSTOP(BUS_MCPU2, BIT(5))),
DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5,
MSTOP(BUS_MCPU3, BIT(4))),
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0),
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0,
MSTOP(BUS_MCPU2, BIT(14))),
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1,
MSTOP(BUS_MCPU2, BIT(14))),
DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0,
MSTOP(BUS_MCPU2, BIT(15))),
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0,
MSTOP(BUS_MCPU3, GENMASK(8, 7))),
};
static const struct rzg2l_reset r9a08g045_resets[] = {
@@ -293,78 +342,6 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
};
static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
/* Keep always-on domain on the first position for proper domains registration. */
DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
DEF_REG_CONF(0, 0),
GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE),
DEF_PD("gic", R9A08G045_PD_GIC,
DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
GENPD_FLAG_ALWAYS_ON),
DEF_PD("ia55", R9A08G045_PD_IA55,
DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
GENPD_FLAG_ALWAYS_ON),
DEF_PD("dmac", R9A08G045_PD_DMAC,
DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
GENPD_FLAG_ALWAYS_ON),
DEF_PD("wdt0", R9A08G045_PD_WDT0,
DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
GENPD_FLAG_IRQ_SAFE),
DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0),
DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0),
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0),
DEF_PD("ssi0", R9A08G045_PD_SSI0,
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0),
DEF_PD("ssi1", R9A08G045_PD_SSI1,
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0),
DEF_PD("ssi2", R9A08G045_PD_SSI2,
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0),
DEF_PD("ssi3", R9A08G045_PD_SSI3,
DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0),
DEF_PD("usb0", R9A08G045_PD_USB0,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0),
DEF_PD("usb1", R9A08G045_PD_USB1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), 0),
DEF_PD("usb-phy", R9A08G045_PD_USB_PHY,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), 0),
DEF_PD("eth0", R9A08G045_PD_ETHER0,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0),
DEF_PD("eth1", R9A08G045_PD_ETHER1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0),
DEF_PD("i2c0", R9A08G045_PD_I2C0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0),
DEF_PD("i2c1", R9A08G045_PD_I2C1,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0),
DEF_PD("i2c2", R9A08G045_PD_I2C2,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0),
DEF_PD("i2c3", R9A08G045_PD_I2C3,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0),
DEF_PD("scif0", R9A08G045_PD_SCIF0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0),
DEF_PD("scif1", R9A08G045_PD_SCIF1,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0),
DEF_PD("scif2", R9A08G045_PD_SCIF2,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0),
DEF_PD("scif3", R9A08G045_PD_SCIF3,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0),
DEF_PD("scif4", R9A08G045_PD_SCIF4,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0),
DEF_PD("scif5", R9A08G045_PD_SCIF5,
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),
DEF_PD("adc", R9A08G045_PD_ADC,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),
DEF_PD("tsu", R9A08G045_PD_TSU,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0),
DEF_PD("vbat", R9A08G045_PD_VBAT,
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
GENPD_FLAG_ALWAYS_ON),
DEF_PD("rtc", R9A08G045_PD_RTC,
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0),
};
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
/* Core Clocks */
.core_clks = r9a08g045_core_clks,
@@ -385,9 +362,5 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
/* Power domains */
.pm_domains = r9a08g045_pm_domains,
.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
.has_clk_mon_regs = true,
};

116
drivers/clk/renesas/r9a09g011-cpg.c
View File

@@ -151,64 +151,64 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
};
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0),
DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1),
DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2),
DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3),
DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4),
DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5),
DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6),
DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7),
DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8),
DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9),
DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10),
DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11),
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4),
DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5),
DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6),
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12),
DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0),
DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4),
DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5),
DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6),
DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7),
DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8),
DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9),
DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10),
DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11),
DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12),
DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0),
DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4),
DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5),
DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6),
DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7),
DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8),
DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9),
DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10),
DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11),
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0),
DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4),
DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5),
DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6),
DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7),
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8),
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9),
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10),
DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0),
DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1),
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8),
DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12),
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2, 0),
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5, 0),
DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0, 0),
DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1, 0),
DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2, 0),
DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3, 0),
DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4, 0),
DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5, 0),
DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6, 0),
DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7, 0),
DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8, 0),
DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9, 0),
DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10, 0),
DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11, 0),
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8, 0),
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8, 0),
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9, 0),
DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4, 0),
DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5, 0),
DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6, 0),
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12, 0),
DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12, 0),
DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0, 0),
DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4, 0),
DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5, 0),
DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6, 0),
DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7, 0),
DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8, 0),
DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9, 0),
DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10, 0),
DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11, 0),
DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12, 0),
DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0, 0),
DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4, 0),
DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5, 0),
DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6, 0),
DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7, 0),
DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8, 0),
DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9, 0),
DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10, 0),
DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11, 0),
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12, 0),
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13, 0),
DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0, 0),
DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4, 0),
DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5, 0),
DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6, 0),
DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7, 0),
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8, 0),
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9, 0),
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10, 0),
DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0, 0),
DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1, 0),
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4, 0),
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5, 0),
DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8, 0),
DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12, 0),
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0, 0),
};
static const struct rzg2l_reset r9a09g011_resets[] = {

72
drivers/clk/renesas/r9a09g047-cpg.c
View File

@@ -29,6 +29,7 @@ enum clk_ids {
CLK_PLLDTY,
CLK_PLLCA55,
CLK_PLLVDO,
CLK_PLLETH,
/* Internal Core Clocks */
CLK_PLLCM33_DIV3,
@@ -46,6 +47,15 @@ enum clk_ids {
CLK_PLLDTY_ACPU,
CLK_PLLDTY_ACPU_DIV2,
CLK_PLLDTY_ACPU_DIV4,
CLK_PLLDTY_DIV8,
CLK_PLLETH_DIV_250_FIX,
CLK_PLLETH_DIV_125_FIX,
CLK_CSDIV_PLLETH_GBE0,
CLK_CSDIV_PLLETH_GBE1,
CLK_SMUX2_GBE0_TXCLK,
CLK_SMUX2_GBE0_RXCLK,
CLK_SMUX2_GBE1_TXCLK,
CLK_SMUX2_GBE1_RXCLK,
CLK_PLLDTY_DIV16,
CLK_PLLVDO_CRU0,
CLK_PLLVDO_GPU,
@@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] = {
{0, 0},
};
static const struct clk_div_table dtable_2_100[] = {
{0, 2},
{1, 10},
{2, 100},
{0, 0},
};
/* Mux clock tables */
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
@@ -100,6 +121,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
/* Internal Core Clocks */
@@ -122,6 +144,18 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,
CSDIV0_DIVCTL0, dtable_2_100),
DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,
CSDIV0_DIVCTL1, dtable_2_100),
DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
@@ -139,6 +173,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
CDDIV1_DIVCTL3, dtable_1_8),
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
};
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -160,6 +198,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(5, BIT(13))),
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
BUS_MSTOP(3, BIT(14))),
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
BUS_MSTOP(10, BIT(15))),
DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
BUS_MSTOP(10, BIT(15))),
DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
BUS_MSTOP(10, BIT(15))),
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
BUS_MSTOP(3, BIT(13))),
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
@@ -214,6 +258,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(4))),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
BUS_MSTOP(8, BIT(4))),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
BUS_MSTOP(8, BIT(5))),
DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
BUS_MSTOP(8, BIT(5))),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
BUS_MSTOP(8, BIT(6))),
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
BUS_MSTOP(8, BIT(6))),
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
BUS_MSTOP(9, BIT(4))),
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -239,6 +307,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
@@ -255,6 +325,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */

202
drivers/clk/renesas/r9a09g056-cpg.c
View File

@@ -16,7 +16,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
LAST_DT_CORE_CLK = R9A09G056_SPI_CLK_SPI,
/* External Input Clocks */
CLK_AUDIO_EXTAL,
@@ -28,13 +28,34 @@ enum clk_ids {
CLK_PLLCLN,
CLK_PLLDTY,
CLK_PLLCA55,
CLK_PLLETH,
CLK_PLLGPU,
/* Internal Core Clocks */
CLK_PLLCM33_DIV3,
CLK_PLLCM33_DIV4,
CLK_PLLCM33_DIV5,
CLK_PLLCM33_DIV16,
CLK_SMUX2_XSPI_CLK0,
CLK_SMUX2_XSPI_CLK1,
CLK_PLLCM33_XSPI,
CLK_PLLCM33_GEAR,
CLK_PLLCLN_DIV2,
CLK_PLLCLN_DIV8,
CLK_PLLCLN_DIV16,
CLK_PLLDTY_ACPU,
CLK_PLLDTY_ACPU_DIV2,
CLK_PLLDTY_ACPU_DIV4,
CLK_PLLDTY_DIV8,
CLK_PLLETH_DIV_250_FIX,
CLK_PLLETH_DIV_125_FIX,
CLK_CSDIV_PLLETH_GBE0,
CLK_CSDIV_PLLETH_GBE1,
CLK_SMUX2_GBE0_TXCLK,
CLK_SMUX2_GBE0_RXCLK,
CLK_SMUX2_GBE1_TXCLK,
CLK_SMUX2_GBE1_RXCLK,
CLK_PLLGPU_GEAR,
/* Module Clocks */
MOD_CLK_BASE,
@@ -48,6 +69,14 @@ static const struct clk_div_table dtable_1_8[] = {
{0, 0},
};
static const struct clk_div_table dtable_2_16[] = {
{0, 2},
{1, 4},
{2, 8},
{3, 16},
{0, 0},
};
static const struct clk_div_table dtable_2_64[] = {
{0, 2},
{1, 4},
@@ -57,6 +86,21 @@ static const struct clk_div_table dtable_2_64[] = {
{0, 0},
};
static const struct clk_div_table dtable_2_100[] = {
{0, 2},
{1, 10},
{2, 100},
{0, 0},
};
/* Mux clock tables */
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -68,15 +112,41 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
/* Internal Core Clocks */
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
dtable_2_16),
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -89,13 +159,76 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
CDDIV1_DIVCTL3, dtable_1_8),
DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
DEF_FIXED("usb2_0_clk_core0", R9A09G056_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G056_GBETH_0_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
FIXED_MOD_CONF_XSPI),
};
static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
BUS_MSTOP(3, BIT(5))),
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
BUS_MSTOP(5, BIT(10))),
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
BUS_MSTOP(5, BIT(11))),
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
BUS_MSTOP(2, BIT(13))),
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
BUS_MSTOP(2, BIT(14))),
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
BUS_MSTOP(11, BIT(13))),
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
BUS_MSTOP(11, BIT(14))),
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
BUS_MSTOP(11, BIT(15))),
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
BUS_MSTOP(12, BIT(0))),
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
BUS_MSTOP(3, BIT(10))),
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
BUS_MSTOP(3, BIT(10))),
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
BUS_MSTOP(1, BIT(0))),
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
BUS_MSTOP(1, BIT(0))),
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
BUS_MSTOP(5, BIT(12))),
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
BUS_MSTOP(5, BIT(12))),
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
BUS_MSTOP(5, BIT(13))),
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
BUS_MSTOP(5, BIT(13))),
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
BUS_MSTOP(3, BIT(14))),
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
BUS_MSTOP(3, BIT(13))),
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
BUS_MSTOP(1, BIT(1))),
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
BUS_MSTOP(1, BIT(2))),
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
BUS_MSTOP(1, BIT(3))),
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
BUS_MSTOP(1, BIT(4))),
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
BUS_MSTOP(1, BIT(5))),
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
BUS_MSTOP(1, BIT(6))),
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
BUS_MSTOP(1, BIT(7))),
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
BUS_MSTOP(1, BIT(8))),
DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
BUS_MSTOP(4, BIT(5))),
DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
BUS_MSTOP(4, BIT(5))),
DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
BUS_MSTOP(4, BIT(5))),
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
BUS_MSTOP(8, BIT(2))),
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
@@ -120,16 +253,83 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(4))),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
BUS_MSTOP(8, BIT(4))),
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
BUS_MSTOP(7, BIT(7))),
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
BUS_MSTOP(7, BIT(9))),
DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
BUS_MSTOP(7, BIT(10))),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
BUS_MSTOP(8, BIT(5))),
DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
BUS_MSTOP(8, BIT(5))),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
BUS_MSTOP(8, BIT(6))),
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
BUS_MSTOP(8, BIT(6))),
DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
BUS_MSTOP(3, BIT(4))),
DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
BUS_MSTOP(3, BIT(4))),
DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
BUS_MSTOP(3, BIT(4))),
};
static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
};
const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {

127
drivers/clk/renesas/r9a09g057-cpg.c
View File

@@ -16,7 +16,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I,
LAST_DT_CORE_CLK = R9A09G057_SPI_CLK_SPI,
/* External Input Clocks */
CLK_AUDIO_EXTAL,
@@ -29,12 +29,18 @@ enum clk_ids {
CLK_PLLDTY,
CLK_PLLCA55,
CLK_PLLVDO,
CLK_PLLETH,
CLK_PLLGPU,
/* Internal Core Clocks */
CLK_PLLCM33_DIV3,
CLK_PLLCM33_DIV4,
CLK_PLLCM33_DIV4_PLLCM33,
CLK_PLLCM33_DIV5,
CLK_PLLCM33_DIV16,
CLK_PLLCM33_GEAR,
CLK_SMUX2_XSPI_CLK0,
CLK_SMUX2_XSPI_CLK1,
CLK_PLLCM33_XSPI,
CLK_PLLCLN_DIV2,
CLK_PLLCLN_DIV8,
CLK_PLLCLN_DIV16,
@@ -49,6 +55,14 @@ enum clk_ids {
CLK_PLLVDO_CRU1,
CLK_PLLVDO_CRU2,
CLK_PLLVDO_CRU3,
CLK_PLLETH_DIV_250_FIX,
CLK_PLLETH_DIV_125_FIX,
CLK_CSDIV_PLLETH_GBE0,
CLK_CSDIV_PLLETH_GBE1,
CLK_SMUX2_GBE0_TXCLK,
CLK_SMUX2_GBE0_RXCLK,
CLK_SMUX2_GBE1_TXCLK,
CLK_SMUX2_GBE1_RXCLK,
CLK_PLLGPU_GEAR,
/* Module Clocks */
@@ -69,6 +83,14 @@ static const struct clk_div_table dtable_2_4[] = {
{0, 0},
};
static const struct clk_div_table dtable_2_16[] = {
{0, 2},
{1, 4},
{2, 8},
{3, 16},
{0, 0},
};
static const struct clk_div_table dtable_2_64[] = {
{0, 2},
{1, 4},
@@ -78,6 +100,21 @@ static const struct clk_div_table dtable_2_64[] = {
{0, 0},
};
static const struct clk_div_table dtable_2_100[] = {
{0, 2},
{1, 10},
{2, 100},
{0, 0},
};
/* Mux clock tables */
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -90,13 +127,20 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
/* Internal Core Clocks */
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33,
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR,
CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
dtable_2_16),
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
@@ -115,6 +159,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
/* Core Clocks */
@@ -130,10 +185,16 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
FIXED_MOD_CONF_XSPI),
};
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0,
DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0,
BUS_MSTOP(5, BIT(9))),
DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
BUS_MSTOP(3, BIT(2))),
@@ -179,6 +240,24 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
BUS_MSTOP(5, BIT(13))),
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
BUS_MSTOP(5, BIT(13))),
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
BUS_MSTOP(11, BIT(0))),
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
BUS_MSTOP(11, BIT(0))),
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
BUS_MSTOP(11, BIT(0))),
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
BUS_MSTOP(11, BIT(1))),
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
BUS_MSTOP(11, BIT(1))),
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
BUS_MSTOP(11, BIT(1))),
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
BUS_MSTOP(11, BIT(2))),
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
BUS_MSTOP(11, BIT(2))),
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
BUS_MSTOP(11, BIT(2))),
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
BUS_MSTOP(3, BIT(14))),
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
@@ -199,6 +278,12 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
BUS_MSTOP(1, BIT(7))),
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
BUS_MSTOP(1, BIT(8))),
DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
BUS_MSTOP(4, BIT(5))),
DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
BUS_MSTOP(4, BIT(5))),
DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
BUS_MSTOP(4, BIT(5))),
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
BUS_MSTOP(8, BIT(2))),
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
@@ -233,6 +318,30 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
BUS_MSTOP(7, BIT(10))),
DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
BUS_MSTOP(7, BIT(11))),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
BUS_MSTOP(8, BIT(5))),
DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
BUS_MSTOP(8, BIT(5))),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
BUS_MSTOP(8, BIT(6)), 1),
DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
BUS_MSTOP(8, BIT(6))),
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
BUS_MSTOP(8, BIT(6))),
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
BUS_MSTOP(9, BIT(4))),
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -287,6 +396,12 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
@@ -297,6 +412,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
@@ -304,6 +421,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */

256
drivers/clk/renesas/r9a09g077-cpg.c Normal file
View File

@@ -0,0 +1,256 @@
// SPDX-License-Identifier: GPL-2.0
/*
* r9a09g077 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2025 Renesas Electronics Corp.
*
*/
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#define RZT2H_REG_BLOCK_SHIFT 11
#define RZT2H_REG_OFFSET_MASK GENMASK(10, 0)
#define RZT2H_REG_CONF(block, offset) (((block) << RZT2H_REG_BLOCK_SHIFT) | \
((offset) & RZT2H_REG_OFFSET_MASK))
#define RZT2H_REG_BLOCK(x) ((x) >> RZT2H_REG_BLOCK_SHIFT)
#define RZT2H_REG_OFFSET(x) ((x) & RZT2H_REG_OFFSET_MASK)
#define SCKCR RZT2H_REG_CONF(0, 0x00)
#define SCKCR2 RZT2H_REG_CONF(1, 0x04)
#define SCKCR3 RZT2H_REG_CONF(0, 0x08)
#define OFFSET_MASK GENMASK(31, 20)
#define SHIFT_MASK GENMASK(19, 12)
#define WIDTH_MASK GENMASK(11, 8)
#define CONF_PACK(offset, shift, width) \
(FIELD_PREP_CONST(OFFSET_MASK, (offset)) | \
FIELD_PREP_CONST(SHIFT_MASK, (shift)) | \
FIELD_PREP_CONST(WIDTH_MASK, (width)))
#define GET_SHIFT(val) FIELD_GET(SHIFT_MASK, val)
#define GET_WIDTH(val) FIELD_GET(WIDTH_MASK, val)
#define GET_REG_OFFSET(val) FIELD_GET(OFFSET_MASK, val)
#define DIVCA55C0 CONF_PACK(SCKCR2, 8, 1)
#define DIVCA55C1 CONF_PACK(SCKCR2, 9, 1)
#define DIVCA55C2 CONF_PACK(SCKCR2, 10, 1)
#define DIVCA55C3 CONF_PACK(SCKCR2, 11, 1)
#define DIVCA55S CONF_PACK(SCKCR2, 12, 1)
#define DIVSCI0ASYNC CONF_PACK(SCKCR3, 6, 2)
#define SEL_PLL CONF_PACK(SCKCR, 22, 1)
enum rzt2h_clk_types {
CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
};
#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
.parent = _parent, .dtable = _dtable, .flag = 0)
#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \
DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents, \
.flag = 0, .mux_flags = _mux_flags)
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R9A09G077_SDHI_CLKHS,
/* External Input Clocks */
CLK_EXTAL,
/* Internal Core Clocks */
CLK_LOCO,
CLK_PLL0,
CLK_PLL1,
CLK_PLL2,
CLK_PLL4,
CLK_SEL_CLK_PLL0,
CLK_SEL_CLK_PLL1,
CLK_SEL_CLK_PLL2,
CLK_SEL_CLK_PLL4,
CLK_PLL4D1,
CLK_SCI0ASYNC,
/* Module Clocks */
MOD_CLK_BASE,
};
static const struct clk_div_table dtable_1_2[] = {
{0, 2},
{1, 1},
{0, 0},
};
static const struct clk_div_table dtable_24_25_30_32[] = {
{0, 32},
{1, 30},
{2, 25},
{3, 24},
{0, 0},
};
/* Mux clock tables */
static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_RATE(".loco", CLK_LOCO, 1000 * 1000),
DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48),
DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32),
DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL,
sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
dtable_24_25_30_32),
/* Core output clk */
DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
dtable_1_2),
DEF_DIV("CA55C1", R9A09G077_CLK_CA55C1, CLK_SEL_CLK_PLL0, DIVCA55C1,
dtable_1_2),
DEF_DIV("CA55C2", R9A09G077_CLK_CA55C2, CLK_SEL_CLK_PLL0, DIVCA55C2,
dtable_1_2),
DEF_DIV("CA55C3", R9A09G077_CLK_CA55C3, CLK_SEL_CLK_PLL0, DIVCA55C3,
dtable_1_2),
DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
dtable_1_2),
DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
};
static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
};
static struct clk * __init
r9a09g077_cpg_div_clk_register(struct device *dev,
const struct cpg_core_clk *core,
void __iomem *addr, struct cpg_mssr_pub *pub)
{
const struct clk *parent;
const char *parent_name;
struct clk_hw *clk_hw;
parent = pub->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
parent_name = __clk_get_name(parent);
if (core->dtable)
clk_hw = clk_hw_register_divider_table(dev, core->name,
parent_name, 0,
addr,
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->flag,
core->dtable,
&pub->rmw_lock);
else
clk_hw = clk_hw_register_divider(dev, core->name,
parent_name, 0,
addr,
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->flag, &pub->rmw_lock);
if (IS_ERR(clk_hw))
return ERR_CAST(clk_hw);
return clk_hw->clk;
}
static struct clk * __init
r9a09g077_cpg_mux_clk_register(struct device *dev,
const struct cpg_core_clk *core,
void __iomem *addr, struct cpg_mssr_pub *pub)
{
struct clk_hw *clk_hw;
clk_hw = devm_clk_hw_register_mux(dev, core->name,
core->parent_names, core->num_parents,
core->flag,
addr,
GET_SHIFT(core->conf),
GET_WIDTH(core->conf),
core->mux_flags, &pub->rmw_lock);
if (IS_ERR(clk_hw))
return ERR_CAST(clk_hw);
return clk_hw->clk;
}
static struct clk * __init
r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core,
const struct cpg_mssr_info *info,
struct cpg_mssr_pub *pub)
{
u32 offset = GET_REG_OFFSET(core->conf);
void __iomem *base = RZT2H_REG_BLOCK(offset) ? pub->base1 : pub->base0;
void __iomem *addr = base + RZT2H_REG_OFFSET(offset);
switch (core->type) {
case CLK_TYPE_RZT2H_DIV:
return r9a09g077_cpg_div_clk_register(dev, core, addr, pub);
case CLK_TYPE_RZT2H_MUX:
return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub);
default:
return ERR_PTR(-EINVAL);
}
}
const struct cpg_mssr_info r9a09g077_cpg_mssr_info = {
/* Core Clocks */
.core_clks = r9a09g077_core_clks,
.num_core_clks = ARRAY_SIZE(r9a09g077_core_clks),
.last_dt_core_clk = LAST_DT_CORE_CLK,
.num_total_core_clks = MOD_CLK_BASE,
/* Module Clocks */
.mod_clks = r9a09g077_mod_clks,
.num_mod_clks = ARRAY_SIZE(r9a09g077_mod_clks),
.num_hw_mod_clks = 14 * 32,
.reg_layout = CLK_REG_LAYOUT_RZ_T2H,
.cpg_clk_register = r9a09g077_cpg_clk_register,
};

5
drivers/clk/renesas/rcar-gen2-cpg.c
View File

@@ -274,10 +274,11 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers)
struct cpg_mssr_pub *pub)
{
const struct clk_div_table *table = NULL;
void __iomem *base = pub->base0;
struct clk **clks = pub->clks;
const struct clk *parent;
const char *parent_name;
unsigned int mult = 1;

3
drivers/clk/renesas/rcar-gen2-cpg.h
View File

@@ -32,8 +32,7 @@ struct rcar_gen2_cpg_pll_config {
struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers);
struct cpg_mssr_pub *pub);
int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
unsigned int pll0_div, u32 mode);

6
drivers/clk/renesas/rcar-gen3-cpg.c
View File

@@ -345,9 +345,11 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers)
struct cpg_mssr_pub *pub)
{
struct raw_notifier_head *notifiers = &pub->notifiers;
void __iomem *base = pub->base0;
struct clk **clks = pub->clks;
const struct clk *parent;
unsigned int mult = 1;
unsigned int div = 1;

3
drivers/clk/renesas/rcar-gen3-cpg.h
View File

@@ -81,8 +81,7 @@ struct rcar_gen3_cpg_pll_config {
struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers);
struct cpg_mssr_pub *pub);
int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
unsigned int clk_extalr, u32 mode);

6
drivers/clk/renesas/rcar-gen4-cpg.c
View File

@@ -418,9 +418,11 @@ static const struct clk_div_table cpg_rpcsrc_div_table[] = {
struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers)
struct cpg_mssr_pub *pub)
{
struct raw_notifier_head *notifiers = &pub->notifiers;
void __iomem *base = pub->base0;
struct clk **clks = pub->clks;
const struct clk *parent;
unsigned int mult = 1;
unsigned int div = 1;

3
drivers/clk/renesas/rcar-gen4-cpg.h
View File

@@ -78,8 +78,7 @@ struct rcar_gen4_cpg_pll_config {
struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers);
struct cpg_mssr_pub *pub);
int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
unsigned int clk_extalr, u32 mode);

195
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@@ -80,6 +80,37 @@ static const u16 mstpcr_for_gen4[] = {
0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74,
};
/*
* Module Stop Control Register (RZ/T2H)
* RZ/T2H has 2 registers blocks,
* Bit 12 is used to differentiate them
*/
#define RZT2H_MSTPCR_BLOCK_SHIFT 12
#define RZT2H_MSTPCR_OFFSET_MASK GENMASK(11, 0)
#define RZT2H_MSTPCR(block, offset) (((block) << RZT2H_MSTPCR_BLOCK_SHIFT) | \
((offset) & RZT2H_MSTPCR_OFFSET_MASK))
#define RZT2H_MSTPCR_BLOCK(x) ((x) >> RZT2H_MSTPCR_BLOCK_SHIFT)
#define RZT2H_MSTPCR_OFFSET(x) ((x) & RZT2H_MSTPCR_OFFSET_MASK)
static const u16 mstpcr_for_rzt2h[] = {
RZT2H_MSTPCR(0, 0x300), /* MSTPCRA */
RZT2H_MSTPCR(0, 0x304), /* MSTPCRB */
RZT2H_MSTPCR(0, 0x308), /* MSTPCRC */
RZT2H_MSTPCR(0, 0x30c), /* MSTPCRD */
RZT2H_MSTPCR(0, 0x310), /* MSTPCRE */
0,
RZT2H_MSTPCR(1, 0x318), /* MSTPCRG */
0,
RZT2H_MSTPCR(1, 0x320), /* MSTPCRI */
RZT2H_MSTPCR(0, 0x324), /* MSTPCRJ */
RZT2H_MSTPCR(0, 0x328), /* MSTPCRK */
RZT2H_MSTPCR(0, 0x32c), /* MSTPCRL */
RZT2H_MSTPCR(0, 0x330), /* MSTPCRM */
RZT2H_MSTPCR(1, 0x334), /* MSTPCRN */
};
/*
* Standby Control Register offsets (RZ/A)
* Base address is FRQCR register
@@ -126,16 +157,14 @@ static const u16 srstclr_for_gen4[] = {
* struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
* and Software Reset Private Data
*
* @pub: Data passed to clock registration callback
* @rcdev: Optional reset controller entity
* @dev: CPG/MSSR device
* @base: CPG/MSSR register block base address
* @reg_layout: CPG/MSSR register layout
* @rmw_lock: protects RMW register accesses
* @np: Device node in DT for this CPG/MSSR module
* @num_core_clks: Number of Core Clocks in clks[]
* @num_mod_clks: Number of Module Clocks in clks[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @notifiers: Notifier chain to save/restore clock state for system resume
* @status_regs: Pointer to status registers array
* @control_regs: Pointer to control registers array
* @reset_regs: Pointer to reset registers array
@@ -147,20 +176,18 @@ static const u16 srstclr_for_gen4[] = {
* @clks: Array containing all Core and Module Clocks
*/
struct cpg_mssr_priv {
struct cpg_mssr_pub pub;
#ifdef CONFIG_RESET_CONTROLLER
struct reset_controller_dev rcdev;
#endif
struct device *dev;
void __iomem *base;
enum clk_reg_layout reg_layout;
spinlock_t rmw_lock;
struct device_node *np;
unsigned int num_core_clks;
unsigned int num_mod_clks;
unsigned int last_dt_core_clk;
struct raw_notifier_head notifiers;
const u16 *status_regs;
const u16 *control_regs;
const u16 *reset_regs;
@@ -192,6 +219,26 @@ struct mstp_clock {
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
static u32 cpg_rzt2h_mstp_read(struct clk_hw *hw, u16 offset)
{
struct mstp_clock *clock = to_mstp_clock(hw);
struct cpg_mssr_priv *priv = clock->priv;
void __iomem *base =
RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
return readl(base + RZT2H_MSTPCR_OFFSET(offset));
}
static void cpg_rzt2h_mstp_write(struct clk_hw *hw, u16 offset, u32 value)
{
struct mstp_clock *clock = to_mstp_clock(hw);
struct cpg_mssr_priv *priv = clock->priv;
void __iomem *base =
RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
writel(value, base + RZT2H_MSTPCR_OFFSET(offset));
}
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
{
struct mstp_clock *clock = to_mstp_clock(hw);
@@ -206,38 +253,52 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
str_on_off(enable));
spin_lock_irqsave(&priv->rmw_lock, flags);
spin_lock_irqsave(&priv->pub.rmw_lock, flags);
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
value = readb(priv->base + priv->control_regs[reg]);
value = readb(priv->pub.base0 + priv->control_regs[reg]);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
writeb(value, priv->base + priv->control_regs[reg]);
writeb(value, priv->pub.base0 + priv->control_regs[reg]);
/* dummy read to ensure write has completed */
readb(priv->base + priv->control_regs[reg]);
barrier_data(priv->base + priv->control_regs[reg]);
} else {
value = readl(priv->base + priv->control_regs[reg]);
readb(priv->pub.base0 + priv->control_regs[reg]);
barrier_data(priv->pub.base0 + priv->control_regs[reg]);
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
value = cpg_rzt2h_mstp_read(hw,
priv->control_regs[reg]);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
writel(value, priv->base + priv->control_regs[reg]);
cpg_rzt2h_mstp_write(hw,
priv->control_regs[reg],
value);
} else {
value = readl(priv->pub.base0 + priv->control_regs[reg]);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
writel(value, priv->pub.base0 + priv->control_regs[reg]);
}
spin_unlock_irqrestore(&priv->rmw_lock, flags);
spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
return 0;
error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],
error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
value, !(value & bitmask), 0, 10);
if (error)
dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
priv->base + priv->control_regs[reg], bit);
priv->pub.base0 + priv->control_regs[reg], bit);
return error;
}
@@ -256,12 +317,16 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mstp_clock(hw);
struct cpg_mssr_priv *priv = clock->priv;
unsigned int reg = clock->index / 32;
u32 value;
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
value = readb(priv->base + priv->control_regs[clock->index / 32]);
value = readb(priv->pub.base0 + priv->control_regs[reg]);
else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
value = cpg_rzt2h_mstp_read(hw,
priv->control_regs[reg]);
else
value = readl(priv->base + priv->status_regs[clock->index / 32]);
value = readl(priv->pub.base0 + priv->status_regs[reg]);
return !(value & BIT(clock->index % 32));
}
@@ -348,7 +413,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
case CLK_TYPE_DIV6P1:
case CLK_TYPE_DIV6_RO:
WARN_DEBUG(core->parent >= priv->num_core_clks);
parent = priv->clks[core->parent];
parent = priv->pub.clks[core->parent];
if (IS_ERR(parent)) {
clk = parent;
goto fail;
@@ -358,12 +423,12 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
if (core->type == CLK_TYPE_DIV6_RO)
/* Multiply with the DIV6 register value */
div *= (readl(priv->base + core->offset) & 0x3f) + 1;
div *= (readl(priv->pub.base0 + core->offset) & 0x3f) + 1;
if (core->type == CLK_TYPE_DIV6P1) {
clk = cpg_div6_register(core->name, 1, &parent_name,
priv->base + core->offset,
&priv->notifiers);
priv->pub.base0 + core->offset,
&priv->pub.notifiers);
} else {
clk = clk_register_fixed_factor(NULL, core->name,
parent_name, 0,
@@ -379,8 +444,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
default:
if (info->cpg_clk_register)
clk = info->cpg_clk_register(dev, core, info,
priv->clks, priv->base,
&priv->notifiers);
&priv->pub);
else
dev_err(dev, "%s has unsupported core clock type %u\n",
core->name, core->type);
@@ -391,7 +455,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
goto fail;
dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
priv->pub.clks[id] = clk;
return;
fail:
@@ -414,14 +478,14 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
WARN_DEBUG(id < priv->num_core_clks);
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
WARN_DEBUG(PTR_ERR(priv->pub.clks[id]) != -ENOENT);
if (!mod->name) {
/* Skip NULLified clock */
return;
}
parent = priv->clks[mod->parent];
parent = priv->pub.clks[mod->parent];
if (IS_ERR(parent)) {
clk = parent;
goto fail;
@@ -623,13 +687,13 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
/* Reset module */
writel(bitmask, priv->base + priv->reset_regs[reg]);
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
udelay(35);
/* Release module from reset state */
writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
return 0;
}
@@ -643,7 +707,7 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
writel(bitmask, priv->base + priv->reset_regs[reg]);
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
return 0;
}
@@ -657,7 +721,7 @@ static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
return 0;
}
@@ -669,7 +733,7 @@ static int cpg_mssr_status(struct reset_controller_dev *rcdev,
unsigned int bit = id % 32;
u32 bitmask = BIT(bit);
return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
return !!(readl(priv->pub.base0 + priv->reset_regs[reg]) & bitmask);
}
static const struct reset_control_ops cpg_mssr_reset_ops = {
@@ -871,6 +935,18 @@ static const struct of_device_id cpg_mssr_match[] = {
.compatible = "renesas,r8a779h0-cpg-mssr",
.data = &r8a779h0_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R9A09G077
{
.compatible = "renesas,r9a09g077-cpg-mssr",
.data = &r9a09g077_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R9A09G087
{
.compatible = "renesas,r9a09g087-cpg-mssr",
.data = &r9a09g077_cpg_mssr_info,
},
#endif
{ /* sentinel */ }
};
@@ -895,12 +971,12 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
if (priv->smstpcr_saved[reg].mask)
priv->smstpcr_saved[reg].val =
priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
readb(priv->base + priv->control_regs[reg]) :
readl(priv->base + priv->control_regs[reg]);
readb(priv->pub.base0 + priv->control_regs[reg]) :
readl(priv->pub.base0 + priv->control_regs[reg]);
}
/* Save core clocks */
raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_SUSPEND, NULL);
return 0;
}
@@ -917,7 +993,7 @@ static int cpg_mssr_resume_noirq(struct device *dev)
return 0;
/* Restore core clocks */
raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_RESUME, NULL);
/* Restore module clocks */
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
@@ -926,29 +1002,29 @@ static int cpg_mssr_resume_noirq(struct device *dev)
continue;
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
oldval = readb(priv->base + priv->control_regs[reg]);
oldval = readb(priv->pub.base0 + priv->control_regs[reg]);
else
oldval = readl(priv->base + priv->control_regs[reg]);
oldval = readl(priv->pub.base0 + priv->control_regs[reg]);
newval = oldval & ~mask;
newval |= priv->smstpcr_saved[reg].val & mask;
if (newval == oldval)
continue;
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
writeb(newval, priv->base + priv->control_regs[reg]);
writeb(newval, priv->pub.base0 + priv->control_regs[reg]);
/* dummy read to ensure write has completed */
readb(priv->base + priv->control_regs[reg]);
barrier_data(priv->base + priv->control_regs[reg]);
readb(priv->pub.base0 + priv->control_regs[reg]);
barrier_data(priv->pub.base0 + priv->control_regs[reg]);
continue;
} else
writel(newval, priv->base + priv->control_regs[reg]);
writel(newval, priv->pub.base0 + priv->control_regs[reg]);
/* Wait until enabled clocks are really enabled */
mask &= ~priv->smstpcr_saved[reg].val;
if (!mask)
continue;
error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],
error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
oldval, !(oldval & mask), 0, 10);
if (error)
dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,
@@ -1058,20 +1134,28 @@ static int __init cpg_mssr_common_init(struct device *dev,
if (!priv)
return -ENOMEM;
priv->pub.clks = priv->clks;
priv->np = np;
priv->dev = dev;
spin_lock_init(&priv->rmw_lock);
spin_lock_init(&priv->pub.rmw_lock);
priv->base = of_iomap(np, 0);
if (!priv->base) {
priv->pub.base0 = of_iomap(np, 0);
if (!priv->pub.base0) {
error = -ENOMEM;
goto out_err;
}
if (info->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
priv->pub.base1 = of_iomap(np, 1);
if (!priv->pub.base1) {
error = -ENOMEM;
goto out_err;
}
}
priv->num_core_clks = info->num_total_core_clks;
priv->num_mod_clks = info->num_hw_mod_clks;
priv->last_dt_core_clk = info->last_dt_core_clk;
RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
RAW_INIT_NOTIFIER_HEAD(&priv->pub.notifiers);
priv->reg_layout = info->reg_layout;
if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
priv->status_regs = mstpsr;
@@ -1080,6 +1164,8 @@ static int __init cpg_mssr_common_init(struct device *dev,
priv->reset_clear_regs = srstclr;
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
priv->control_regs = stbcr;
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
priv->control_regs = mstpcr_for_rzt2h;
} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
priv->status_regs = mstpsr_for_gen4;
priv->control_regs = mstpcr_for_gen4;
@@ -1091,7 +1177,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
}
for (i = 0; i < nclks; i++)
priv->clks[i] = ERR_PTR(-ENOENT);
priv->pub.clks[i] = ERR_PTR(-ENOENT);
error = cpg_mssr_reserved_init(priv, info);
if (error)
@@ -1108,8 +1194,10 @@ static int __init cpg_mssr_common_init(struct device *dev,
reserve_err:
cpg_mssr_reserved_exit(priv);
out_err:
if (priv->base)
iounmap(priv->base);
if (priv->pub.base0)
iounmap(priv->pub.base0);
if (priv->pub.base1)
iounmap(priv->pub.base1);
kfree(priv);
return error;
@@ -1174,7 +1262,8 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
goto reserve_exit;
/* Reset Controller not supported for Standby Control SoCs */
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
goto reserve_exit;
error = cpg_mssr_reset_controller_register(priv);

32
drivers/clk/renesas/renesas-cpg-mssr.h
View File

@@ -8,6 +8,8 @@
#ifndef __CLK_RENESAS_CPG_MSSR_H__
#define __CLK_RENESAS_CPG_MSSR_H__
#include <linux/notifier.h>
/*
* Definitions of CPG Core Clocks
*
@@ -27,6 +29,31 @@ struct cpg_core_clk {
unsigned int div;
unsigned int mult;
unsigned int offset;
union {
const char * const *parent_names;
const struct clk_div_table *dtable;
};
u32 conf;
u16 flag;
u8 mux_flags;
u8 num_parents;
};
/**
* struct cpg_mssr_pub - data shared with device-specific clk registration code
*
* @base0: CPG/MSSR register block base0 address
* @base1: CPG/MSSR register block base1 address
* @notifiers: Notifier chain to save/restore clock state for system resume
* @rmw_lock: protects RMW register accesses
* @clks: pointer to clocks
*/
struct cpg_mssr_pub {
void __iomem *base0;
void __iomem *base1;
struct raw_notifier_head notifiers;
spinlock_t rmw_lock;
struct clk **clks;
};
enum clk_types {
@@ -89,6 +116,7 @@ enum clk_reg_layout {
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
CLK_REG_LAYOUT_RZ_A,
CLK_REG_LAYOUT_RCAR_GEN4,
CLK_REG_LAYOUT_RZ_T2H,
};
/**
@@ -153,8 +181,7 @@ struct cpg_mssr_info {
struct clk *(*cpg_clk_register)(struct device *dev,
const struct cpg_core_clk *core,
const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
struct raw_notifier_head *notifiers);
struct cpg_mssr_pub *pub);
};
extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
@@ -181,6 +208,7 @@ extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
extern const struct cpg_mssr_info r8a779h0_cpg_mssr_info;
extern const struct cpg_mssr_info r9a09g077_cpg_mssr_info;
void __init cpg_mssr_early_init(struct device_node *np,
const struct cpg_mssr_info *info);

529
drivers/clk/renesas/rzg2l-cpg.c
View File

@@ -11,10 +11,13 @@
* Copyright (C) 2015 Renesas Electronics Corp.
*/
#include <linux/atomic.h>
#include <linux/bitfield.h>
#include <linux/cleanup.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
@@ -68,6 +71,9 @@
#define MAX_VCLK_FREQ (148500000)
#define MSTOP_OFF(conf) FIELD_GET(GENMASK(31, 16), (conf))
#define MSTOP_MASK(conf) FIELD_GET(GENMASK(15, 0), (conf))
/**
* struct clk_hw_data - clock hardware data
* @hw: clock hw
@@ -142,6 +148,7 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
* @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
@@ -158,6 +165,8 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
struct generic_pm_domain genpd;
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
@@ -1182,29 +1191,146 @@ fail:
}
/**
* struct mstp_clock - MSTP gating clock
*
* @hw: handle between common and hardware-specific interfaces
* @off: register offset
* @bit: ON/MON bit
* @enabled: soft state of the clock, if it is coupled with another clock
* @priv: CPG/MSTP private data
* @sibling: pointer to the other coupled clock
* struct mstop - MSTOP specific data structure
* @usecnt: Usage counter for MSTOP settings (when zero the settings
* are applied to register)
* @conf: MSTOP configuration (register offset, setup bits)
*/
struct mstp_clock {
struct clk_hw hw;
u16 off;
u8 bit;
bool enabled;
struct rzg2l_cpg_priv *priv;
struct mstp_clock *sibling;
struct mstop {
atomic_t usecnt;
u32 conf;
};
#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
/**
* struct mod_clock - Module clock
*
* @hw: handle between common and hardware-specific interfaces
* @priv: CPG/MSTP private data
* @sibling: pointer to the other coupled clock
* @mstop: MSTOP configuration
* @shared_mstop_clks: clocks sharing the MSTOP with this clock
* @off: register offset
* @bit: ON/MON bit
* @num_shared_mstop_clks: number of the clocks sharing MSTOP with this clock
* @enabled: soft state of the clock, if it is coupled with another clock
*/
struct mod_clock {
struct clk_hw hw;
struct rzg2l_cpg_priv *priv;
struct mod_clock *sibling;
struct mstop *mstop;
struct mod_clock **shared_mstop_clks;
u16 off;
u8 bit;
u8 num_shared_mstop_clks;
bool enabled;
};
#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
#define for_each_mod_clock(mod_clock, hw, priv) \
for (unsigned int i = 0; (priv) && i < (priv)->num_mod_clks; i++) \
if ((priv)->clks[(priv)->num_core_clks + i] == ERR_PTR(-ENOENT)) \
continue; \
else if (((hw) = __clk_get_hw((priv)->clks[(priv)->num_core_clks + i])) && \
((mod_clock) = to_mod_clock(hw)))
/* Need to be called with a lock held to avoid concurrent access to mstop->usecnt. */
static void rzg2l_mod_clock_module_set_state(struct mod_clock *clock,
bool standby)
{
struct rzg2l_cpg_priv *priv = clock->priv;
struct mstop *mstop = clock->mstop;
bool update = false;
u32 value;
if (!mstop)
return;
value = MSTOP_MASK(mstop->conf) << 16;
if (standby) {
unsigned int criticals = 0;
for (unsigned int i = 0; i < clock->num_shared_mstop_clks; i++) {
struct mod_clock *clk = clock->shared_mstop_clks[i];
if (clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL)
criticals++;
}
if (!clock->num_shared_mstop_clks &&
clk_hw_get_flags(&clock->hw) & CLK_IS_CRITICAL)
criticals++;
/*
* If this is a shared MSTOP and it is shared with critical clocks,
* and the system boots up with this clock enabled but no driver
* uses it the CCF will disable it (as it is unused). As we don't
* increment reference counter for it at registration (to avoid
* messing with clocks enabled at probe but later used by drivers)
* do not set the MSTOP here too if it is shared with critical
* clocks and ref counted only by those critical clocks.
*/
if (criticals && criticals == atomic_read(&mstop->usecnt))
return;
value |= MSTOP_MASK(mstop->conf);
/* Allow updates on probe when usecnt = 0. */
if (!atomic_read(&mstop->usecnt))
update = true;
else
update = atomic_dec_and_test(&mstop->usecnt);
} else {
if (!atomic_read(&mstop->usecnt))
update = true;
atomic_inc(&mstop->usecnt);
}
if (update)
writel(value, priv->base + MSTOP_OFF(mstop->conf));
}
static int rzg2l_mod_clock_mstop_show(struct seq_file *s, void *what)
{
struct rzg2l_cpg_priv *priv = s->private;
struct mod_clock *clk;
struct clk_hw *hw;
seq_printf(s, "%-20s %-5s %-10s\n", "", "", "MSTOP");
seq_printf(s, "%-20s %-5s %-10s\n", "", "clk", "-------------------------");
seq_printf(s, "%-20s %-5s %-5s %-5s %-6s %-6s\n",
"clk_name", "cnt", "cnt", "off", "val", "shared");
seq_printf(s, "%-20s %-5s %-5s %-5s %-6s %-6s\n",
"--------", "-----", "-----", "-----", "------", "------");
for_each_mod_clock(clk, hw, priv) {
u32 val;
if (!clk->mstop)
continue;
val = readl(priv->base + MSTOP_OFF(clk->mstop->conf)) &
MSTOP_MASK(clk->mstop->conf);
seq_printf(s, "%-20s %-5d %-5d 0x%-3lx 0x%-4x", clk_hw_get_name(hw),
__clk_get_enable_count(hw->clk), atomic_read(&clk->mstop->usecnt),
MSTOP_OFF(clk->mstop->conf), val);
for (unsigned int i = 0; i < clk->num_shared_mstop_clks; i++)
seq_printf(s, " %pC", clk->shared_mstop_clks[i]->hw.clk);
seq_puts(s, "\n");
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(rzg2l_mod_clock_mstop);
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct mod_clock *clock = to_mod_clock(hw);
struct rzg2l_cpg_priv *priv = clock->priv;
unsigned int reg = clock->off;
struct device *dev = priv->dev;
@@ -1224,7 +1350,15 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
if (enable)
value |= bitmask;
writel(value, priv->base + CLK_ON_R(reg));
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
if (enable) {
writel(value, priv->base + CLK_ON_R(reg));
rzg2l_mod_clock_module_set_state(clock, false);
} else {
rzg2l_mod_clock_module_set_state(clock, true);
writel(value, priv->base + CLK_ON_R(reg));
}
}
if (!enable)
return 0;
@@ -1243,7 +1377,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct mod_clock *clock = to_mod_clock(hw);
if (clock->sibling) {
struct rzg2l_cpg_priv *priv = clock->priv;
@@ -1263,7 +1397,7 @@ static int rzg2l_mod_clock_enable(struct clk_hw *hw)
static void rzg2l_mod_clock_disable(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct mod_clock *clock = to_mod_clock(hw);
if (clock->sibling) {
struct rzg2l_cpg_priv *priv = clock->priv;
@@ -1283,7 +1417,7 @@ static void rzg2l_mod_clock_disable(struct clk_hw *hw)
static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
{
struct mstp_clock *clock = to_mod_clock(hw);
struct mod_clock *clock = to_mod_clock(hw);
struct rzg2l_cpg_priv *priv = clock->priv;
u32 bitmask = BIT(clock->bit);
u32 value;
@@ -1310,21 +1444,14 @@ static const struct clk_ops rzg2l_mod_clock_ops = {
.is_enabled = rzg2l_mod_clock_is_enabled,
};
static struct mstp_clock
*rzg2l_mod_clock_get_sibling(struct mstp_clock *clock,
static struct mod_clock
*rzg2l_mod_clock_get_sibling(struct mod_clock *clock,
struct rzg2l_cpg_priv *priv)
{
struct mod_clock *clk;
struct clk_hw *hw;
unsigned int i;
for (i = 0; i < priv->num_mod_clks; i++) {
struct mstp_clock *clk;
if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT))
continue;
hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]);
clk = to_mod_clock(hw);
for_each_mod_clock(clk, hw, priv) {
if (clock->off == clk->off && clock->bit == clk->bit)
return clk;
}
@@ -1332,12 +1459,89 @@ static struct mstp_clock
return NULL;
}
static struct mstop *rzg2l_mod_clock_get_mstop(struct rzg2l_cpg_priv *priv, u32 conf)
{
struct mod_clock *clk;
struct clk_hw *hw;
for_each_mod_clock(clk, hw, priv) {
if (!clk->mstop)
continue;
if (clk->mstop->conf == conf)
return clk->mstop;
}
return NULL;
}
static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv)
{
struct mod_clock *clk;
struct clk_hw *hw;
for_each_mod_clock(clk, hw, priv) {
if (!clk->mstop)
continue;
/*
* Out of reset all modules are enabled. Set module state
* in case associated clocks are disabled at probe. Otherwise
* module is in invalid HW state.
*/
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
rzg2l_mod_clock_module_set_state(clk, true);
}
}
}
static int rzg2l_mod_clock_update_shared_mstop_clks(struct rzg2l_cpg_priv *priv,
struct mod_clock *clock)
{
struct mod_clock *clk;
struct clk_hw *hw;
if (!clock->mstop)
return 0;
for_each_mod_clock(clk, hw, priv) {
int num_shared_mstop_clks, incr = 1;
struct mod_clock **new_clks;
if (clk->mstop != clock->mstop)
continue;
num_shared_mstop_clks = clk->num_shared_mstop_clks;
if (!num_shared_mstop_clks)
incr++;
new_clks = devm_krealloc(priv->dev, clk->shared_mstop_clks,
(num_shared_mstop_clks + incr) * sizeof(*new_clks),
GFP_KERNEL);
if (!new_clks)
return -ENOMEM;
if (!num_shared_mstop_clks)
new_clks[num_shared_mstop_clks++] = clk;
new_clks[num_shared_mstop_clks++] = clock;
for (unsigned int i = 0; i < num_shared_mstop_clks; i++) {
new_clks[i]->shared_mstop_clks = new_clks;
new_clks[i]->num_shared_mstop_clks = num_shared_mstop_clks;
}
break;
}
return 0;
}
static void __init
rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
const struct rzg2l_cpg_info *info,
struct rzg2l_cpg_priv *priv)
{
struct mstp_clock *clock = NULL;
struct mod_clock *clock = NULL;
struct device *dev = priv->dev;
unsigned int id = mod->id;
struct clk_init_data init;
@@ -1383,18 +1587,29 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
clock->priv = priv;
clock->hw.init = &init;
if (mod->mstop_conf) {
struct mstop *mstop = rzg2l_mod_clock_get_mstop(priv, mod->mstop_conf);
if (!mstop) {
mstop = devm_kzalloc(dev, sizeof(*mstop), GFP_KERNEL);
if (!mstop) {
clk = ERR_PTR(-ENOMEM);
goto fail;
}
mstop->conf = mod->mstop_conf;
atomic_set(&mstop->usecnt, 0);
}
clock->mstop = mstop;
}
ret = devm_clk_hw_register(dev, &clock->hw);
if (ret) {
clk = ERR_PTR(ret);
goto fail;
}
clk = clock->hw.clk;
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
if (mod->is_coupled) {
struct mstp_clock *sibling;
struct mod_clock *sibling;
clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
sibling = rzg2l_mod_clock_get_sibling(clock, priv);
@@ -1404,6 +1619,17 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
}
}
/* Keep this before priv->clks[id] is updated. */
ret = rzg2l_mod_clock_update_shared_mstop_clks(priv, clock);
if (ret) {
clk = ERR_PTR(ret);
goto fail;
}
clk = clock->hw.clk;
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
return;
fail:
@@ -1540,39 +1766,14 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
return devm_reset_controller_register(priv->dev, &priv->rcdev);
}
/**
* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
* @onecell_data: cell data
* @domains: generic PM domains
*/
struct rzg2l_cpg_pm_domains {
struct genpd_onecell_data onecell_data;
struct generic_pm_domain *domains[];
};
/**
* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
* @genpd: generic PM domain
* @priv: pointer to CPG private data structure
* @conf: CPG PM domain configuration info
* @id: RZ/G2L power domain ID
*/
struct rzg2l_cpg_pd {
struct generic_pm_domain genpd;
struct rzg2l_cpg_priv *priv;
struct rzg2l_cpg_pm_domain_conf conf;
u16 id;
};
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd,
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
const struct of_phandle_args *clkspec)
{
if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
if (clkspec->np != priv->genpd.dev.of_node || clkspec->args_count != 2)
return false;
switch (clkspec->args[0]) {
case CPG_MOD: {
struct rzg2l_cpg_priv *priv = pd->priv;
const struct rzg2l_cpg_info *info = priv->info;
unsigned int id = clkspec->args[1];
@@ -1597,7 +1798,7 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd,
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
@@ -1606,7 +1807,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device
int error;
for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {
if (!rzg2l_cpg_is_pm_clk(pd, &clkspec)) {
if (!rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
of_node_put(clkspec.np);
continue;
}
@@ -1651,183 +1852,31 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
}
static void rzg2l_cpg_genpd_remove(void *data)
{
struct genpd_onecell_data *celldata = data;
for (unsigned int i = 0; i < celldata->num_domains; i++)
pm_genpd_remove(celldata->domains[i]);
}
static void rzg2l_cpg_genpd_remove_simple(void *data)
{
pm_genpd_remove(data);
}
static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
struct rzg2l_cpg_priv *priv = pd->priv;
/* Set MSTOP. */
if (mstop.mask)
writel(mstop.mask << 16, priv->base + mstop.off);
return 0;
}
static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
struct rzg2l_cpg_priv *priv = pd->priv;
/* Set MSTOP. */
if (mstop.mask)
writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
return 0;
}
static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd)
{
bool always_on = !!(pd->genpd.flags & GENPD_FLAG_ALWAYS_ON);
struct dev_power_governor *governor;
int ret;
if (always_on)
governor = &pm_domain_always_on_gov;
else
governor = &simple_qos_governor;
pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
pd->genpd.power_on = rzg2l_cpg_power_on;
pd->genpd.power_off = rzg2l_cpg_power_off;
ret = pm_genpd_init(&pd->genpd, governor, !always_on);
if (ret)
return ret;
if (always_on)
ret = rzg2l_cpg_power_on(&pd->genpd);
return ret;
}
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct rzg2l_cpg_pd *pd;
struct generic_pm_domain *genpd = &priv->genpd;
int ret;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->genpd.name = np->name;
pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
pd->priv = priv;
ret = rzg2l_cpg_pd_setup(pd);
genpd->name = np->name;
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
GENPD_FLAG_ACTIVE_WAKEUP;
genpd->attach_dev = rzg2l_cpg_attach_dev;
genpd->detach_dev = rzg2l_cpg_detach_dev;
ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
if (ret)
return ret;
return of_genpd_add_provider_simple(np, &pd->genpd);
}
static struct generic_pm_domain *
rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
{
struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
struct genpd_onecell_data *genpd = data;
if (spec->args_count != 1)
return ERR_PTR(-EINVAL);
for (unsigned int i = 0; i < genpd->num_domains; i++) {
struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
genpd);
if (pd->id == spec->args[0]) {
domain = &pd->genpd;
break;
}
}
return domain;
}
static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
{
const struct rzg2l_cpg_info *info = priv->info;
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
struct rzg2l_cpg_pm_domains *domains;
struct generic_pm_domain *parent;
u32 ncells;
int ret;
ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
if (ret)
return ret;
/* For backward compatibility. */
if (!ncells)
return rzg2l_cpg_add_clk_domain(priv);
domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
GFP_KERNEL);
if (!domains)
return -ENOMEM;
domains->onecell_data.domains = domains->domains;
domains->onecell_data.num_domains = info->num_pm_domains;
domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
if (ret)
return ret;
for (unsigned int i = 0; i < info->num_pm_domains; i++) {
struct rzg2l_cpg_pd *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
if (!pd)
return -ENOMEM;
pd->genpd.name = info->pm_domains[i].name;
pd->genpd.flags = info->pm_domains[i].genpd_flags;
pd->conf = info->pm_domains[i].conf;
pd->id = info->pm_domains[i].id;
pd->priv = priv;
ret = rzg2l_cpg_pd_setup(pd);
if (ret)
return ret;
domains->domains[i] = &pd->genpd;
/* Parent should be on the very first entry of info->pm_domains[]. */
if (!i) {
parent = &pd->genpd;
continue;
}
ret = pm_genpd_add_subdomain(parent, &pd->genpd);
if (ret)
return ret;
}
ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
if (ret)
return ret;
return 0;
return of_genpd_add_provider_simple(np, genpd);
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
@@ -1875,6 +1924,13 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
for (i = 0; i < info->num_mod_clks; i++)
rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
/*
* Initialize MSTOP after all the clocks were registered to avoid
* invalid reference counting when multiple clocks (critical,
* non-critical) share the same MSTOP.
*/
rzg2l_mod_clock_init_mstop(priv);
error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
if (error)
return error;
@@ -1883,7 +1939,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
error = rzg2l_cpg_add_pm_domains(priv);
error = rzg2l_cpg_add_clk_domain(priv);
if (error)
return error;
@@ -1891,9 +1947,23 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fops);
return 0;
}
static int rzg2l_cpg_resume(struct device *dev)
{
struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev);
rzg2l_mod_clock_init_mstop(priv);
return 0;
}
static const struct dev_pm_ops rzg2l_cpg_pm_ops = {
NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume)
};
static const struct of_device_id rzg2l_cpg_match[] = {
#ifdef CONFIG_CLK_R9A07G043
{
@@ -1932,6 +2002,7 @@ static struct platform_driver rzg2l_cpg_driver = {
.driver = {
.name = "rzg2l-cpg",
.of_match_table = rzg2l_cpg_match,
.pm = pm_sleep_ptr(&rzg2l_cpg_pm_ops),
},
};

66
drivers/clk/renesas/rzg2l-cpg.h
View File

@@ -82,6 +82,8 @@
#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
#define MSTOP(name, bitmask) ((CPG_##name##_MSTOP) << 16 | (bitmask))
#define EXTAL_FREQ_IN_MEGA_HZ (24)
/**
@@ -201,6 +203,7 @@ enum clk_types {
* @name: handle between common and hardware-specific interfaces
* @id: clock index in array containing all Core and Module Clocks
* @parent: id of parent clock
* @mstop_conf: MSTOP configuration
* @off: register offset
* @bit: ON/MON bit
* @is_coupled: flag to indicate coupled clock
@@ -209,26 +212,28 @@ struct rzg2l_mod_clk {
const char *name;
unsigned int id;
unsigned int parent;
u32 mstop_conf;
u16 off;
u8 bit;
bool is_coupled;
};
#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \
#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \
{ \
.name = _name, \
.id = MOD_CLK_BASE + (_id), \
.parent = (_parent), \
.mstop_conf = (_mstop_conf), \
.off = (_off), \
.bit = (_bit), \
.is_coupled = (_is_coupled), \
}
#define DEF_MOD(_name, _id, _parent, _off, _bit) \
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
#define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false)
#define DEF_COUPLED(_name, _id, _parent, _off, _bit) \
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
#define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \
DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true)
/**
* struct rzg2l_reset - Reset definitions
@@ -252,51 +257,6 @@ struct rzg2l_reset {
#define DEF_RST(_id, _off, _bit) \
DEF_RST_MON(_id, _off, _bit, -1)
/**
* struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
* @off: register offset
* @mask: register mask
*/
struct rzg2l_cpg_reg_conf {
u16 off;
u16 mask;
};
#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
/**
* struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
* @mstop: MSTOP register configuration
*/
struct rzg2l_cpg_pm_domain_conf {
struct rzg2l_cpg_reg_conf mstop;
};
/**
* struct rzg2l_cpg_pm_domain_init_data - PM domain init data
* @name: PM domain name
* @conf: PM domain configuration
* @genpd_flags: genpd flags (see GENPD_FLAG_*)
* @id: PM domain ID (similar to the ones defined in
* include/dt-bindings/clock/<soc-id>-cpg.h)
*/
struct rzg2l_cpg_pm_domain_init_data {
const char * const name;
struct rzg2l_cpg_pm_domain_conf conf;
u32 genpd_flags;
u16 id;
};
#define DEF_PD(_name, _id, _mstop_conf, _flags) \
{ \
.name = (_name), \
.id = (_id), \
.conf = { \
.mstop = (_mstop_conf), \
}, \
.genpd_flags = (_flags), \
}
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
@@ -315,8 +275,6 @@ struct rzg2l_cpg_pm_domain_init_data {
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
* @pm_domains: PM domains init data array
* @num_pm_domains: Number of PM domains
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
*/
struct rzg2l_cpg_info {
@@ -343,10 +301,6 @@ struct rzg2l_cpg_info {
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
/* Power domain. */
const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
unsigned int num_pm_domains;
bool has_clk_mon_regs;
};

130
drivers/clk/renesas/rzv2h-cpg.c
View File

@@ -77,6 +77,7 @@
* @resets: Array of resets
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @ff_mod_status_ops: Fixed Factor Module Status Clock operations
* @mstop_count: Array of mstop values
* @rcdev: Reset controller entity
*/
@@ -92,6 +93,8 @@ struct rzv2h_cpg_priv {
unsigned int num_resets;
unsigned int last_dt_core_clk;
struct clk_ops *ff_mod_status_ops;
atomic_t *mstop_count;
struct reset_controller_dev rcdev;
@@ -101,7 +104,6 @@ struct rzv2h_cpg_priv {
struct pll_clk {
struct rzv2h_cpg_priv *priv;
void __iomem *base;
struct clk_hw hw;
struct pll pll;
};
@@ -119,6 +121,7 @@ struct pll_clk {
* @on_bit: ON/MON bit
* @mon_index: monitor register offset
* @mon_bit: monitor bit
* @ext_clk_mux_index: mux index for external clock source, or -1 if internal
*/
struct mod_clock {
struct rzv2h_cpg_priv *priv;
@@ -129,6 +132,7 @@ struct mod_clock {
u8 on_bit;
s8 mon_index;
u8 mon_bit;
s8 ext_clk_mux_index;
};
#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
@@ -148,6 +152,22 @@ struct ddiv_clk {
#define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div)
/**
* struct rzv2h_ff_mod_status_clk - Fixed Factor Module Status Clock
*
* @priv: CPG private data
* @conf: fixed mod configuration
* @fix: fixed factor clock
*/
struct rzv2h_ff_mod_status_clk {
struct rzv2h_cpg_priv *priv;
struct fixed_mod_conf conf;
struct clk_fixed_factor fix;
};
#define to_rzv2h_ff_mod_status_clk(_hw) \
container_of(_hw, struct rzv2h_ff_mod_status_clk, fix.hw)
static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
{
struct pll_clk *pll_clk = to_pll(hw);
@@ -228,7 +248,6 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
struct rzv2h_cpg_priv *priv,
const struct clk_ops *ops)
{
void __iomem *base = priv->base;
struct device *dev = priv->dev;
struct clk_init_data init;
const struct clk *parent;
@@ -253,7 +272,6 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
pll_clk->hw.init = &init;
pll_clk->pll = core->cfg.pll;
pll_clk->base = base;
pll_clk->priv = priv;
ret = devm_clk_hw_register(dev, &pll_clk->hw);
@@ -381,6 +399,7 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
init.ops = &rzv2h_ddiv_clk_divider_ops;
init.parent_names = &parent_name;
init.num_parents = 1;
init.flags = CLK_SET_RATE_PARENT;
ddiv->priv = priv;
ddiv->mon = cfg_ddiv.monbit;
@@ -418,6 +437,65 @@ rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
return clk_hw->clk;
}
static int
rzv2h_clk_ff_mod_status_is_enabled(struct clk_hw *hw)
{
struct rzv2h_ff_mod_status_clk *fix = to_rzv2h_ff_mod_status_clk(hw);
struct rzv2h_cpg_priv *priv = fix->priv;
u32 offset = GET_CLK_MON_OFFSET(fix->conf.mon_index);
u32 bitmask = BIT(fix->conf.mon_bit);
u32 val;
val = readl(priv->base + offset);
return !!(val & bitmask);
}
static struct clk * __init
rzv2h_cpg_fixed_mod_status_clk_register(const struct cpg_core_clk *core,
struct rzv2h_cpg_priv *priv)
{
struct rzv2h_ff_mod_status_clk *clk_hw_data;
struct clk_init_data init = { };
struct clk_fixed_factor *fix;
const struct clk *parent;
const char *parent_name;
int ret;
WARN_DEBUG(core->parent >= priv->num_core_clks);
parent = priv->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
parent_name = __clk_get_name(parent);
parent = priv->clks[core->parent];
if (IS_ERR(parent))
return ERR_CAST(parent);
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
if (!clk_hw_data)
return ERR_PTR(-ENOMEM);
clk_hw_data->priv = priv;
clk_hw_data->conf = core->cfg.fixed_mod;
init.name = core->name;
init.ops = priv->ff_mod_status_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
fix = &clk_hw_data->fix;
fix->hw.init = &init;
fix->mult = core->mult;
fix->div = core->div;
ret = devm_clk_hw_register(priv->dev, &clk_hw_data->fix.hw);
if (ret)
return ERR_PTR(ret);
return clk_hw_data->fix.hw.clk;
}
static struct clk
*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
void *data)
@@ -496,6 +574,20 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
else
clk = clk_hw->clk;
break;
case CLK_TYPE_FF_MOD_STATUS:
if (!priv->ff_mod_status_ops) {
priv->ff_mod_status_ops =
devm_kzalloc(dev, sizeof(*priv->ff_mod_status_ops), GFP_KERNEL);
if (!priv->ff_mod_status_ops) {
clk = ERR_PTR(-ENOMEM);
goto fail;
}
memcpy(priv->ff_mod_status_ops, &clk_fixed_factor_ops,
sizeof(const struct clk_ops));
priv->ff_mod_status_ops->is_enabled = rzv2h_clk_ff_mod_status_is_enabled;
}
clk = rzv2h_cpg_fixed_mod_status_clk_register(core, priv);
break;
case CLK_TYPE_PLL:
clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops);
break;
@@ -563,15 +655,38 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
spin_unlock_irqrestore(&priv->rmw_lock, flags);
}
static int rzv2h_parent_clk_mux_to_index(struct clk_hw *hw)
{
struct clk_hw *parent_hw;
struct clk *parent_clk;
struct clk_mux *mux;
u32 val;
/* This will always succeed, so no need to check for IS_ERR() */
parent_clk = clk_get_parent(hw->clk);
parent_hw = __clk_get_hw(parent_clk);
mux = to_clk_mux(parent_hw);
val = readl(mux->reg) >> mux->shift;
val &= mux->mask;
return clk_mux_val_to_index(parent_hw, mux->table, 0, val);
}
static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
{
struct mod_clock *clock = to_mod_clock(hw);
struct rzv2h_cpg_priv *priv = clock->priv;
int mon_index = clock->mon_index;
u32 bitmask;
u32 offset;
if (clock->mon_index >= 0) {
offset = GET_CLK_MON_OFFSET(clock->mon_index);
if (clock->ext_clk_mux_index >= 0 &&
rzv2h_parent_clk_mux_to_index(hw) == clock->ext_clk_mux_index)
mon_index = -1;
if (mon_index >= 0) {
offset = GET_CLK_MON_OFFSET(mon_index);
bitmask = BIT(clock->mon_bit);
if (!(readl(priv->base + offset) & bitmask))
@@ -687,6 +802,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
clock->mon_index = mod->mon_index;
clock->mon_bit = mod->mon_bit;
clock->no_pm = mod->no_pm;
clock->ext_clk_mux_index = mod->ext_clk_mux_index;
clock->priv = priv;
clock->hw.init = &init;
clock->mstop_data = mod->mstop_data;
@@ -1004,8 +1120,8 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
/* Adjust for CPG_BUS_m_MSTOP starting from m = 1 */
priv->mstop_count -= 16;
priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
info->num_resets, GFP_KERNEL);
priv->resets = devm_kmemdup_array(dev, info->resets, info->num_resets,
sizeof(*info->resets), GFP_KERNEL);
if (!priv->resets)
return -ENOMEM;

49
drivers/clk/renesas/rzv2h-cpg.h
View File

@@ -9,6 +9,7 @@
#define __RENESAS_RZV2H_CPG_H__
#include <linux/bitfield.h>
#include <linux/types.h>
/**
* struct pll - Structure for PLL configuration
@@ -93,6 +94,24 @@ struct smuxed {
.width = (_width), \
})
/**
* struct fixed_mod_conf - Structure for fixed module configuration
*
* @mon_index: monitor index
* @mon_bit: monitor bit
*/
struct fixed_mod_conf {
u8 mon_index;
u8 mon_bit;
};
#define FIXED_MOD_CONF_PACK(_index, _bit) \
((struct fixed_mod_conf){ \
.mon_index = (_index), \
.mon_bit = (_bit), \
})
#define CPG_SSEL0 (0x300)
#define CPG_SSEL1 (0x304)
#define CPG_CDDIV0 (0x400)
#define CPG_CDDIV1 (0x404)
@@ -113,8 +132,14 @@ struct smuxed {
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1)
#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1)
#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
@@ -124,6 +149,8 @@ struct smuxed {
FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
#define BUS_MSTOP_NONE GENMASK(31, 0)
#define FIXED_MOD_CONF_XSPI FIXED_MOD_CONF_PACK(5, 1)
/**
* Definitions of CPG Core Clocks
*
@@ -144,6 +171,7 @@ struct cpg_core_clk {
struct ddiv ddiv;
struct pll pll;
struct smuxed smux;
struct fixed_mod_conf fixed_mod;
} cfg;
const struct clk_div_table *dtable;
const char * const *parent_names;
@@ -156,6 +184,7 @@ enum clk_types {
/* Generic */
CLK_TYPE_IN, /* External Clock Input */
CLK_TYPE_FF, /* Fixed Factor Clock */
CLK_TYPE_FF_MOD_STATUS, /* Fixed Factor Clock which can report the status of module clock */
CLK_TYPE_PLL,
CLK_TYPE_DDIV, /* Dynamic Switching Divider */
CLK_TYPE_SMUX, /* Static Mux */
@@ -171,6 +200,9 @@ enum clk_types {
DEF_TYPE(_name, _id, CLK_TYPE_IN)
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
#define DEF_FIXED_MOD_STATUS(_name, _id, _parent, _mult, _div, _gate) \
DEF_BASE(_name, _id, CLK_TYPE_FF_MOD_STATUS, _parent, .div = _div, \
.mult = _mult, .cfg.fixed_mod = _gate)
#define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \
.cfg.ddiv = _ddiv_packed, \
@@ -199,6 +231,7 @@ enum clk_types {
* @on_bit: ON bit
* @mon_index: monitor register index
* @mon_bit: monitor bit
* @ext_clk_mux_index: mux index for external clock source, or -1 if internal
*/
struct rzv2h_mod_clk {
const char *name;
@@ -210,9 +243,11 @@ struct rzv2h_mod_clk {
u8 on_bit;
s8 mon_index;
u8 mon_bit;
s8 ext_clk_mux_index;
};
#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \
#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \
_onbit, _monindex, _monbit, _ext_clk_mux_index) \
{ \
.name = (_name), \
.mstop_data = (_mstop), \
@@ -223,16 +258,22 @@ struct rzv2h_mod_clk {
.on_bit = (_onbit), \
.mon_index = (_monindex), \
.mon_bit = (_monbit), \
.ext_clk_mux_index = (_ext_clk_mux_index), \
}
#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit)
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1)
#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit)
DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1)
#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \
DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit)
DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1)
#define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \
_ext_clk_mux_index) \
DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \
_ext_clk_mux_index)
/**
* struct rzv2h_reset - Reset definitions

2
drivers/clk/samsung/clk-exynos850.c
View File

@@ -1360,7 +1360,7 @@ static const unsigned long cpucl1_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
};
/* List of parent clocks for Muxes in CMU_CPUCL0 */
/* List of parent clocks for Muxes in CMU_CPUCL1 */
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };

72
drivers/clk/samsung/clk-exynosautov920.c
View File

@@ -26,6 +26,7 @@
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
#define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1)
/* ---- CMU_TOP ------------------------------------------------------------ */
@@ -1752,6 +1753,74 @@ static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
.clk_name = "noc",
};
/* ---- CMU_HSI2 --------------------------------------------------------- */
/* Register Offset definitions for CMU_HSI2 (0x16b00000) */
#define PLL_LOCKTIME_PLL_ETH 0x0
#define PLL_CON3_PLL_ETH 0x10c
#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER 0x600
#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER 0x610
#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x630
#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET 0x1000
#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET 0x1800
#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP 0x1804
static const unsigned long hsi2_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_ETH,
PLL_CON3_PLL_ETH,
PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER,
PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER,
PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET,
CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
};
static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {
/* CMU_HSI2_PLL */
PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),
};
/* List of parent clocks for Muxes in CMU_HSI2 */
PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };
PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };
PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };
PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };
static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),
MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),
MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),
MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),
};
static const struct samsung_div_clock hsi2_div_clks[] __initconst = {
DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
"mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
0, 4),
DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
"mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
0, 4),
};
static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
.pll_clks = hsi2_pll_clks,
.nr_pll_clks = ARRAY_SIZE(hsi2_pll_clks),
.mux_clks = hsi2_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
.div_clks = hsi2_div_clks,
.nr_div_clks = ARRAY_SIZE(hsi2_div_clks),
.nr_clk_ids = CLKS_NR_HSI2,
.clk_regs = hsi2_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs),
.clk_name = "noc",
};
static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
@@ -1779,6 +1848,9 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov920-cmu-hsi1",
.data = &hsi1_cmu_info,
}, {
.compatible = "samsung,exynosautov920-cmu-hsi2",
.data = &hsi2_cmu_info,
},
{ }
};

4
drivers/clk/samsung/clk-gs101.c
View File

@@ -1154,7 +1154,7 @@ static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",
CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
DIV(CLK_DOUT_CMU_G3D_BUSD, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
@@ -2129,7 +2129,7 @@ PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk",
"dout_cmu_hsi0_usbdpdbg" };
PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user",
"mout_hsi0_alt_user" };
PNAME(mout_hsi0_usb20_ref_p) = { "fout_usb_pll",
PNAME(mout_hsi0_usb20_ref_p) = { "mout_pll_usb",
"mout_hsi0_tcxo_user" };
PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
"mout_hsi0_usb31drd_user",

1
drivers/clk/spacemit/Kconfig
View File

@@ -3,6 +3,7 @@
config SPACEMIT_CCU
tristate "Clock support for SpacemiT SoCs"
depends on ARCH_SPACEMIT || COMPILE_TEST
select AUXILIARY_BUS
select MFD_SYSCON
help
Say Y to enable clock controller unit support for SpacemiT SoCs.

242
drivers/clk/spacemit/ccu-k1.c
View File

@@ -5,12 +5,16 @@
*/
#include <linux/array_size.h>
#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/idr.h>
#include <linux/mfd/syscon.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <soc/spacemit/k1-syscon.h>
#include "ccu_common.h"
#include "ccu_pll.h"
@@ -19,121 +23,14 @@
#include <dt-bindings/clock/spacemit,k1-syscon.h>
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
#define APBS_PLL1_SWCR2 0x104
#define APBS_PLL1_SWCR3 0x108
#define APBS_PLL2_SWCR1 0x118
#define APBS_PLL2_SWCR2 0x11c
#define APBS_PLL2_SWCR3 0x120
#define APBS_PLL3_SWCR1 0x124
#define APBS_PLL3_SWCR2 0x128
#define APBS_PLL3_SWCR3 0x12c
/* MPMU register offset */
#define MPMU_POSR 0x0010
#define POSR_PLL1_LOCK BIT(27)
#define POSR_PLL2_LOCK BIT(28)
#define POSR_PLL3_LOCK BIT(29)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024
#define MPMU_APBCSCR 0x1050
#define MPMU_SUCCR_1 0x10b0
/* APBC register offset */
#define APBC_UART1_CLK_RST 0x00
#define APBC_UART2_CLK_RST 0x04
#define APBC_GPIO_CLK_RST 0x08
#define APBC_PWM0_CLK_RST 0x0c
#define APBC_PWM1_CLK_RST 0x10
#define APBC_PWM2_CLK_RST 0x14
#define APBC_PWM3_CLK_RST 0x18
#define APBC_TWSI8_CLK_RST 0x20
#define APBC_UART3_CLK_RST 0x24
#define APBC_RTC_CLK_RST 0x28
#define APBC_TWSI0_CLK_RST 0x2c
#define APBC_TWSI1_CLK_RST 0x30
#define APBC_TIMERS1_CLK_RST 0x34
#define APBC_TWSI2_CLK_RST 0x38
#define APBC_AIB_CLK_RST 0x3c
#define APBC_TWSI4_CLK_RST 0x40
#define APBC_TIMERS2_CLK_RST 0x44
#define APBC_ONEWIRE_CLK_RST 0x48
#define APBC_TWSI5_CLK_RST 0x4c
#define APBC_DRO_CLK_RST 0x58
#define APBC_IR_CLK_RST 0x5c
#define APBC_TWSI6_CLK_RST 0x60
#define APBC_COUNTER_CLK_SEL 0x64
#define APBC_TWSI7_CLK_RST 0x68
#define APBC_TSEN_CLK_RST 0x6c
#define APBC_UART4_CLK_RST 0x70
#define APBC_UART5_CLK_RST 0x74
#define APBC_UART6_CLK_RST 0x78
#define APBC_SSP3_CLK_RST 0x7c
#define APBC_SSPA0_CLK_RST 0x80
#define APBC_SSPA1_CLK_RST 0x84
#define APBC_IPC_AP2AUD_CLK_RST 0x90
#define APBC_UART7_CLK_RST 0x94
#define APBC_UART8_CLK_RST 0x98
#define APBC_UART9_CLK_RST 0x9c
#define APBC_CAN0_CLK_RST 0xa0
#define APBC_PWM4_CLK_RST 0xa8
#define APBC_PWM5_CLK_RST 0xac
#define APBC_PWM6_CLK_RST 0xb0
#define APBC_PWM7_CLK_RST 0xb4
#define APBC_PWM8_CLK_RST 0xb8
#define APBC_PWM9_CLK_RST 0xbc
#define APBC_PWM10_CLK_RST 0xc0
#define APBC_PWM11_CLK_RST 0xc4
#define APBC_PWM12_CLK_RST 0xc8
#define APBC_PWM13_CLK_RST 0xcc
#define APBC_PWM14_CLK_RST 0xd0
#define APBC_PWM15_CLK_RST 0xd4
#define APBC_PWM16_CLK_RST 0xd8
#define APBC_PWM17_CLK_RST 0xdc
#define APBC_PWM18_CLK_RST 0xe0
#define APBC_PWM19_CLK_RST 0xe4
/* APMU register offset */
#define APMU_JPG_CLK_RES_CTRL 0x020
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
#define APMU_ISP_CLK_RES_CTRL 0x038
#define APMU_LCD_CLK_RES_CTRL1 0x044
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
#define APMU_LCD_CLK_RES_CTRL2 0x04c
#define APMU_CCIC_CLK_RES_CTRL 0x050
#define APMU_SDH0_CLK_RES_CTRL 0x054
#define APMU_SDH1_CLK_RES_CTRL 0x058
#define APMU_USB_CLK_RES_CTRL 0x05c
#define APMU_QSPI_CLK_RES_CTRL 0x060
#define APMU_DMA_CLK_RES_CTRL 0x064
#define APMU_AES_CLK_RES_CTRL 0x068
#define APMU_VPU_CLK_RES_CTRL 0x0a4
#define APMU_GPU_CLK_RES_CTRL 0x0cc
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
#define APMU_PMUA_MC_CTRL 0x0e8
#define APMU_PMU_CC2_AP 0x100
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
#define APMU_CCI550_CLK_CTRL 0x300
#define APMU_ACLK_CLK_CTRL 0x388
#define APMU_CPU_C0_CLK_CTRL 0x38C
#define APMU_CPU_C1_CLK_CTRL 0x390
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
struct spacemit_ccu_data {
const char *reset_name;
struct clk_hw **hws;
size_t num;
};
static DEFINE_IDA(auxiliary_ids);
/* APBS clocks start, APBS region contains and only contains all PLL clocks */
/*
@@ -170,7 +67,8 @@ CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4,
CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1);
CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,
CLK_IS_CRITICAL);
CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1);
CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1);
@@ -819,8 +717,9 @@ static struct clk_hw *k1_ccu_pll_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_pll_data = {
.hws = k1_ccu_pll_hws,
.num = ARRAY_SIZE(k1_ccu_pll_hws),
/* The PLL CCU implements no resets */
.hws = k1_ccu_pll_hws,
.num = ARRAY_SIZE(k1_ccu_pll_hws),
};
static struct clk_hw *k1_ccu_mpmu_hws[] = {
@@ -860,8 +759,9 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
.hws = k1_ccu_mpmu_hws,
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
.reset_name = "mpmu-reset",
.hws = k1_ccu_mpmu_hws,
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
};
static struct clk_hw *k1_ccu_apbc_hws[] = {
@@ -968,8 +868,9 @@ static struct clk_hw *k1_ccu_apbc_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apbc_data = {
.hws = k1_ccu_apbc_hws,
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
.reset_name = "apbc-reset",
.hws = k1_ccu_apbc_hws,
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
};
static struct clk_hw *k1_ccu_apmu_hws[] = {
@@ -1038,8 +939,21 @@ static struct clk_hw *k1_ccu_apmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apmu_data = {
.hws = k1_ccu_apmu_hws,
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
.reset_name = "apmu-reset",
.hws = k1_ccu_apmu_hws,
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
};
static const struct spacemit_ccu_data k1_ccu_rcpu_data = {
.reset_name = "rcpu-reset",
};
static const struct spacemit_ccu_data k1_ccu_rcpu2_data = {
.reset_name = "rcpu2-reset",
};
static const struct spacemit_ccu_data k1_ccu_apbc2_data = {
.reset_name = "apbc2-reset",
};
static int spacemit_ccu_register(struct device *dev,
@@ -1050,6 +964,10 @@ static int spacemit_ccu_register(struct device *dev,
struct clk_hw_onecell_data *clk_data;
int i, ret;
/* Nothing to do if the CCU does not implement any clocks */
if (!data->hws)
return 0;
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
GFP_KERNEL);
if (!clk_data)
@@ -1090,9 +1008,74 @@ static int spacemit_ccu_register(struct device *dev,
return ret;
}
static void spacemit_cadev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
ida_free(&auxiliary_ids, adev->id);
kfree(to_spacemit_ccu_adev(adev));
}
static void spacemit_adev_unregister(void *data)
{
struct auxiliary_device *adev = data;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
static int spacemit_ccu_reset_register(struct device *dev,
struct regmap *regmap,
const char *reset_name)
{
struct spacemit_ccu_adev *cadev;
struct auxiliary_device *adev;
int ret;
/* Nothing to do if the CCU does not implement a reset controller */
if (!reset_name)
return 0;
cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
if (!cadev)
return -ENOMEM;
cadev->regmap = regmap;
adev = &cadev->adev;
adev->name = reset_name;
adev->dev.parent = dev;
adev->dev.release = spacemit_cadev_release;
adev->dev.of_node = dev->of_node;
ret = ida_alloc(&auxiliary_ids, GFP_KERNEL);
if (ret < 0)
goto err_free_cadev;
adev->id = ret;
ret = auxiliary_device_init(adev);
if (ret)
goto err_free_aux_id;
ret = auxiliary_device_add(adev);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);
err_free_aux_id:
ida_free(&auxiliary_ids, adev->id);
err_free_cadev:
kfree(cadev);
return ret;
}
static int k1_ccu_probe(struct platform_device *pdev)
{
struct regmap *base_regmap, *lock_regmap = NULL;
const struct spacemit_ccu_data *data;
struct device *dev = &pdev->dev;
int ret;
@@ -1121,11 +1104,16 @@ static int k1_ccu_probe(struct platform_device *pdev)
"failed to get lock regmap\n");
}
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap,
of_device_get_match_data(dev));
data = of_device_get_match_data(dev);
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data);
if (ret)
return dev_err_probe(dev, ret, "failed to register clocks\n");
ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name);
if (ret)
return dev_err_probe(dev, ret, "failed to register resets\n");
return 0;
}
@@ -1146,6 +1134,18 @@ static const struct of_device_id of_k1_ccu_match[] = {
.compatible = "spacemit,k1-syscon-apmu",
.data = &k1_ccu_apmu_data,
},
{
.compatible = "spacemit,k1-syscon-rcpu",
.data = &k1_ccu_rcpu_data,
},
{
.compatible = "spacemit,k1-syscon-rcpu2",
.data = &k1_ccu_rcpu2_data,
},
{
.compatible = "spacemit,k1-syscon-apbc2",
.data = &k1_ccu_apbc2_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, of_k1_ccu_match);

11
drivers/clk/spacemit/ccu_mix.h
View File

@@ -101,17 +101,22 @@ static struct ccu_mix _name = { \
} \
}
#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
_mul) \
#define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
_mul, _flags) \
static struct ccu_mix _name = { \
.gate = CCU_GATE_INIT(_mask_gate), \
.factor = CCU_FACTOR_INIT(_div, _mul), \
.common = { \
.reg_ctrl = _reg_ctrl, \
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, 0) \
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, _flags) \
} \
}
#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
_mul) \
CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
_mul, 0)
#define CCU_MUX_GATE_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, \
_mask_gate, _flags) \
static struct ccu_mix _name = { \

2
drivers/clk/spacemit/ccu_pll.c
View File

@@ -122,7 +122,7 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
WARN_ON_ONCE(!entry);
return entry ? entry->rate : -EINVAL;
return entry ? entry->rate : 0;
}
static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,

1
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c
View File

@@ -204,6 +204,7 @@ static struct ccu_reset_map sun55i_a523_r_ccu_resets[] = {
[RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
[RST_BUS_R_RTC] = { 0x20c, BIT(16) },
[RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
[RST_BUS_R_PPU0] = { 0x1ac, BIT(16) },
};
static const struct sunxi_ccu_desc sun55i_a523_r_ccu_desc = {

22
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View File

@@ -347,12 +347,13 @@ static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram",
static const char * const de_parents[] = { "pll-video", "pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_NO_REPARENT);
static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
0x118, 0, 4, 24, 3, BIT(31), 0);
0x118, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_NO_REPARENT);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
0x130, BIT(31), 0);
@@ -754,6 +755,21 @@ static int sun8i_v3s_ccu_probe(struct platform_device *pdev)
val &= ~GENMASK(19, 16);
writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG);
/*
* Assign the DE and TCON clock to the video PLL. Both clocks need to
* have the same parent for the units to work together.
*/
val = readl(reg + de_clk.common.reg);
val &= ~GENMASK(de_clk.mux.shift + de_clk.mux.width - 1,
de_clk.mux.shift);
writel(val, reg + de_clk.common.reg);
val = readl(reg + tcon_clk.common.reg);
val &= ~GENMASK(tcon_clk.mux.shift + tcon_clk.mux.width - 1,
tcon_clk.mux.shift);
writel(val, reg + tcon_clk.common.reg);
return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}

14
drivers/clk/sunxi-ng/ccu_gate.c
View File

@@ -91,8 +91,8 @@ static unsigned long ccu_gate_recalc_rate(struct clk_hw *hw,
return rate;
}
static long ccu_gate_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
static int ccu_gate_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_gate *cg = hw_to_ccu_gate(hw);
int div = 1;
@@ -101,14 +101,16 @@ static long ccu_gate_round_rate(struct clk_hw *hw, unsigned long rate,
div = cg->common.prediv;
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
unsigned long best_parent = rate;
unsigned long best_parent = req->rate;
if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
best_parent *= div;
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
}
return *prate / div;
req->rate = req->best_parent_rate / div;
return 0;
}
static int ccu_gate_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -127,7 +129,7 @@ const struct clk_ops ccu_gate_ops = {
.disable = ccu_gate_disable,
.enable = ccu_gate_enable,
.is_enabled = ccu_gate_is_enabled,
.round_rate = ccu_gate_round_rate,
.determine_rate = ccu_gate_determine_rate,
.set_rate = ccu_gate_set_rate,
.recalc_rate = ccu_gate_recalc_rate,
};

14
drivers/clk/sunxi-ng/ccu_nk.c
View File

@@ -92,26 +92,26 @@ static unsigned long ccu_nk_recalc_rate(struct clk_hw *hw,
return rate;
}
static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int ccu_nk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
struct _ccu_nk _nk;
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nk->fixed_post_div;
req->rate *= nk->fixed_post_div;
_nk.min_n = nk->n.min ?: 1;
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
_nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
rate = ccu_nk_find_best(*parent_rate, rate, &_nk);
req->rate = ccu_nk_find_best(req->best_parent_rate, req->rate, &_nk);
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate / nk->fixed_post_div;
req->rate = req->rate / nk->fixed_post_div;
return rate;
return 0;
}
static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -155,7 +155,7 @@ const struct clk_ops ccu_nk_ops = {
.is_enabled = ccu_nk_is_enabled,
.recalc_rate = ccu_nk_recalc_rate,
.round_rate = ccu_nk_round_rate,
.determine_rate = ccu_nk_determine_rate,
.set_rate = ccu_nk_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_nk_ops, "SUNXI_CCU");

23
drivers/clk/sunxi-ng/ccu_nkmp.c
View File

@@ -127,20 +127,20 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
return rate;
}
static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int ccu_nkmp_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkmp->fixed_post_div;
req->rate *= nkmp->fixed_post_div;
if (nkmp->max_rate && rate > nkmp->max_rate) {
rate = nkmp->max_rate;
if (nkmp->max_rate && req->rate > nkmp->max_rate) {
req->rate = nkmp->max_rate;
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkmp->fixed_post_div;
return rate;
req->rate /= nkmp->fixed_post_div;
return 0;
}
_nkmp.min_n = nkmp->n.min ?: 1;
@@ -152,12 +152,13 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
rate = ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
req->rate = ccu_nkmp_find_best(req->best_parent_rate, req->rate,
&_nkmp);
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate / nkmp->fixed_post_div;
req->rate = req->rate / nkmp->fixed_post_div;
return rate;
return 0;
}
static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -227,7 +228,7 @@ const struct clk_ops ccu_nkmp_ops = {
.is_enabled = ccu_nkmp_is_enabled,
.recalc_rate = ccu_nkmp_recalc_rate,
.round_rate = ccu_nkmp_round_rate,
.determine_rate = ccu_nkmp_determine_rate,
.set_rate = ccu_nkmp_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_nkmp_ops, "SUNXI_CCU");

43
drivers/clk/sunxi-ng/ccu_nm.c
View File

@@ -116,39 +116,39 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
return rate;
}
static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int ccu_nm_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
struct _ccu_nm _nm;
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nm->fixed_post_div;
req->rate *= nm->fixed_post_div;
if (rate < nm->min_rate) {
rate = nm->min_rate;
if (req->rate < nm->min_rate) {
req->rate = nm->min_rate;
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
req->rate /= nm->fixed_post_div;
return 0;
}
if (nm->max_rate && rate > nm->max_rate) {
rate = nm->max_rate;
if (nm->max_rate && req->rate > nm->max_rate) {
req->rate = nm->max_rate;
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
req->rate /= nm->fixed_post_div;
return 0;
}
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, req->rate)) {
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
req->rate /= nm->fixed_post_div;
return 0;
}
if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) {
if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, req->rate)) {
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
req->rate /= nm->fixed_post_div;
return 0;
}
_nm.min_n = nm->n.min ?: 1;
@@ -156,12 +156,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
rate = ccu_nm_find_best(&nm->common, *parent_rate, rate, &_nm);
req->rate = ccu_nm_find_best(&nm->common, req->best_parent_rate,
req->rate, &_nm);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
req->rate /= nm->fixed_post_div;
return rate;
return 0;
}
static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -233,7 +234,7 @@ const struct clk_ops ccu_nm_ops = {
.is_enabled = ccu_nm_is_enabled,
.recalc_rate = ccu_nm_recalc_rate,
.round_rate = ccu_nm_round_rate,
.determine_rate = ccu_nm_determine_rate,
.set_rate = ccu_nm_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_nm_ops, "SUNXI_CCU");

9
drivers/reset/Kconfig
View File

@@ -270,6 +270,15 @@ config RESET_SOCFPGA
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
config RESET_SPACEMIT
tristate "SpacemiT reset driver"
depends on ARCH_SPACEMIT || COMPILE_TEST
select AUXILIARY_BUS
default ARCH_SPACEMIT
help
This enables the reset controller driver for SpacemiT SoCs,
including the K1.
config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
default ARCH_SUNPLUS

1
drivers/reset/Makefile
View File

@@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TH1520) += reset-th1520.o

304
drivers/reset/reset-spacemit.c Normal file
View File

@@ -0,0 +1,304 @@
// SPDX-License-Identifier: GPL-2.0-only
/* SpacemiT reset controller driver */
#include <linux/auxiliary_bus.h>
#include <linux/container_of.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/types.h>
#include <soc/spacemit/k1-syscon.h>
#include <dt-bindings/clock/spacemit,k1-syscon.h>
struct ccu_reset_data {
u32 offset;
u32 assert_mask;
u32 deassert_mask;
};
struct ccu_reset_controller_data {
const struct ccu_reset_data *reset_data; /* array */
size_t count;
};
struct ccu_reset_controller {
struct reset_controller_dev rcdev;
const struct ccu_reset_controller_data *data;
struct regmap *regmap;
};
#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \
{ \
.offset = (_offset), \
.assert_mask = (_assert_mask), \
.deassert_mask = (_deassert_mask), \
}
static const struct ccu_reset_data k1_mpmu_resets[] = {
[RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0),
};
static const struct ccu_reset_controller_data k1_mpmu_reset_data = {
.reset_data = k1_mpmu_resets,
.count = ARRAY_SIZE(k1_mpmu_resets),
};
static const struct ccu_reset_data k1_apbc_resets[] = {
[RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0),
[RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0),
[RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0),
[RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)),
[RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)),
[RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0),
[RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0),
[RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0),
[RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0),
[RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0),
[RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0),
[RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0),
[RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0),
[RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0),
[RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0),
[RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0),
[RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0),
[RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0),
[RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0),
[RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0),
[RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0),
[RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0),
[RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0),
[RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0),
[RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0),
[RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0),
[RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0),
[RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0),
[RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0),
[RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0),
[RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0),
[RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0),
[RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0),
};
static const struct ccu_reset_controller_data k1_apbc_reset_data = {
.reset_data = k1_apbc_resets,
.count = ARRAY_SIZE(k1_apbc_resets),
};
static const struct ccu_reset_data k1_apmu_resets[] = {
[RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)),
[RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)),
[RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)),
[RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
[RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)),
[RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
[RESET_USB30_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
[RESET_USB30_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
[RESET_USB30_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
[RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
[RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
[RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
[RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)),
[RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)),
[RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)),
[RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)),
[RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)),
[RESET_AUDIO_SYS] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(0)),
[RESET_AUDIO_MCU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(2)),
[RESET_AUDIO_APMU] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, BIT(3)),
[RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)),
[RESET_PCIE0_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(3)),
[RESET_PCIE0_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(4)),
[RESET_PCIE0_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, 0, BIT(5)),
[RESET_PCIE0_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0),
[RESET_PCIE1_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(3)),
[RESET_PCIE1_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(4)),
[RESET_PCIE1_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, 0, BIT(5)),
[RESET_PCIE1_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), 0),
[RESET_PCIE2_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(3)),
[RESET_PCIE2_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(4)),
[RESET_PCIE2_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, 0, BIT(5)),
[RESET_PCIE2_GLOBAL] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), 0),
[RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
[RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
[RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)),
[RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)),
[RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)),
[RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)),
[RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)),
[RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)),
[RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)),
[RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)),
[RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)),
[RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)),
[RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)),
[RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)),
[RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)),
[RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)),
[RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)),
[RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)),
};
static const struct ccu_reset_controller_data k1_apmu_reset_data = {
.reset_data = k1_apmu_resets,
.count = ARRAY_SIZE(k1_apmu_resets),
};
static const struct ccu_reset_data k1_rcpu_resets[] = {
[RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)),
[RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)),
[RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)),
[RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)),
[RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)),
[RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)),
[RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)),
};
static const struct ccu_reset_controller_data k1_rcpu_reset_data = {
.reset_data = k1_rcpu_resets,
.count = ARRAY_SIZE(k1_rcpu_resets),
};
static const struct ccu_reset_data k1_rcpu2_resets[] = {
[RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
[RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)),
};
static const struct ccu_reset_controller_data k1_rcpu2_reset_data = {
.reset_data = k1_rcpu2_resets,
.count = ARRAY_SIZE(k1_rcpu2_resets),
};
static const struct ccu_reset_data k1_apbc2_resets[] = {
[RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0),
[RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0),
[RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0),
[RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0),
[RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0),
[RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0),
[RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0),
};
static const struct ccu_reset_controller_data k1_apbc2_reset_data = {
.reset_data = k1_apbc2_resets,
.count = ARRAY_SIZE(k1_apbc2_resets),
};
static int spacemit_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct ccu_reset_controller *controller;
const struct ccu_reset_data *data;
u32 mask;
u32 val;
controller = container_of(rcdev, struct ccu_reset_controller, rcdev);
data = &controller->data->reset_data[id];
mask = data->assert_mask | data->deassert_mask;
val = assert ? data->assert_mask : data->deassert_mask;
return regmap_update_bits(controller->regmap, data->offset, mask, val);
}
static int spacemit_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return spacemit_reset_update(rcdev, id, true);
}
static int spacemit_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return spacemit_reset_update(rcdev, id, false);
}
static const struct reset_control_ops spacemit_reset_control_ops = {
.assert = spacemit_reset_assert,
.deassert = spacemit_reset_deassert,
};
static int spacemit_reset_controller_register(struct device *dev,
struct ccu_reset_controller *controller)
{
struct reset_controller_dev *rcdev = &controller->rcdev;
rcdev->ops = &spacemit_reset_control_ops;
rcdev->owner = THIS_MODULE;
rcdev->of_node = dev->of_node;
rcdev->nr_resets = controller->data->count;
return devm_reset_controller_register(dev, &controller->rcdev);
}
static int spacemit_reset_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev);
struct ccu_reset_controller *controller;
struct device *dev = &adev->dev;
controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
if (!controller)
return -ENOMEM;
controller->data = (const struct ccu_reset_controller_data *)id->driver_data;
controller->regmap = rdev->regmap;
return spacemit_reset_controller_register(dev, controller);
}
#define K1_AUX_DEV_ID(_unit) \
{ \
.name = "spacemit_ccu_k1." #_unit "-reset", \
.driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
}
static const struct auxiliary_device_id spacemit_reset_ids[] = {
K1_AUX_DEV_ID(mpmu),
K1_AUX_DEV_ID(apbc),
K1_AUX_DEV_ID(apmu),
K1_AUX_DEV_ID(rcpu),
K1_AUX_DEV_ID(rcpu2),
K1_AUX_DEV_ID(apbc2),
{ },
};
MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids);
static struct auxiliary_driver spacemit_k1_reset_driver = {
.probe = spacemit_reset_probe,
.id_table = spacemit_reset_ids,
};
module_auxiliary_driver(spacemit_k1_reset_driver);
MODULE_AUTHOR("Alex Elder <elder@kernel.org>");
MODULE_DESCRIPTION("SpacemiT reset controller driver");
MODULE_LICENSE("GPL");

53
include/dt-bindings/clock/r9a07g043-cpg.h
View File

@@ -200,57 +200,4 @@
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
/* Power domain IDs. */
#define R9A07G043_PD_ALWAYS_ON 0
#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
#define R9A07G043_PD_DMAC 6
#define R9A07G043_PD_GTM0 7
#define R9A07G043_PD_GTM1 8
#define R9A07G043_PD_GTM2 9
#define R9A07G043_PD_MTU 10
#define R9A07G043_PD_POE3 11
#define R9A07G043_PD_WDT0 12
#define R9A07G043_PD_SPI 13
#define R9A07G043_PD_SDHI0 14
#define R9A07G043_PD_SDHI1 15
#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
#define R9A07G043_PD_SSI0 19
#define R9A07G043_PD_SSI1 20
#define R9A07G043_PD_SSI2 21
#define R9A07G043_PD_SSI3 22
#define R9A07G043_PD_SRC 23
#define R9A07G043_PD_USB0 24
#define R9A07G043_PD_USB1 25
#define R9A07G043_PD_USB_PHY 26
#define R9A07G043_PD_ETHER0 27
#define R9A07G043_PD_ETHER1 28
#define R9A07G043_PD_I2C0 29
#define R9A07G043_PD_I2C1 30
#define R9A07G043_PD_I2C2 31
#define R9A07G043_PD_I2C3 32
#define R9A07G043_PD_SCIF0 33
#define R9A07G043_PD_SCIF1 34
#define R9A07G043_PD_SCIF2 35
#define R9A07G043_PD_SCIF3 36
#define R9A07G043_PD_SCIF4 37
#define R9A07G043_PD_SCI0 38
#define R9A07G043_PD_SCI1 39
#define R9A07G043_PD_IRDA 40
#define R9A07G043_PD_RSPI0 41
#define R9A07G043_PD_RSPI1 42
#define R9A07G043_PD_RSPI2 43
#define R9A07G043_PD_CANFD 44
#define R9A07G043_PD_ADC 45
#define R9A07G043_PD_TSU 46
#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */

58
include/dt-bindings/clock/r9a07g044-cpg.h
View File

@@ -217,62 +217,4 @@
#define R9A07G044_ADC_ADRST_N 82
#define R9A07G044_TSU_PRESETN 83
/* Power domain IDs. */
#define R9A07G044_PD_ALWAYS_ON 0
#define R9A07G044_PD_GIC 1
#define R9A07G044_PD_IA55 2
#define R9A07G044_PD_MHU 3
#define R9A07G044_PD_CORESIGHT 4
#define R9A07G044_PD_SYC 5
#define R9A07G044_PD_DMAC 6
#define R9A07G044_PD_GTM0 7
#define R9A07G044_PD_GTM1 8
#define R9A07G044_PD_GTM2 9
#define R9A07G044_PD_MTU 10
#define R9A07G044_PD_POE3 11
#define R9A07G044_PD_GPT 12
#define R9A07G044_PD_POEGA 13
#define R9A07G044_PD_POEGB 14
#define R9A07G044_PD_POEGC 15
#define R9A07G044_PD_POEGD 16
#define R9A07G044_PD_WDT0 17
#define R9A07G044_PD_WDT1 18
#define R9A07G044_PD_SPI 19
#define R9A07G044_PD_SDHI0 20
#define R9A07G044_PD_SDHI1 21
#define R9A07G044_PD_3DGE 22
#define R9A07G044_PD_ISU 23
#define R9A07G044_PD_VCPL4 24
#define R9A07G044_PD_CRU 25
#define R9A07G044_PD_MIPI_DSI 26
#define R9A07G044_PD_LCDC 27
#define R9A07G044_PD_SSI0 28
#define R9A07G044_PD_SSI1 29
#define R9A07G044_PD_SSI2 30
#define R9A07G044_PD_SSI3 31
#define R9A07G044_PD_SRC 32
#define R9A07G044_PD_USB0 33
#define R9A07G044_PD_USB1 34
#define R9A07G044_PD_USB_PHY 35
#define R9A07G044_PD_ETHER0 36
#define R9A07G044_PD_ETHER1 37
#define R9A07G044_PD_I2C0 38
#define R9A07G044_PD_I2C1 39
#define R9A07G044_PD_I2C2 40
#define R9A07G044_PD_I2C3 41
#define R9A07G044_PD_SCIF0 42
#define R9A07G044_PD_SCIF1 43
#define R9A07G044_PD_SCIF2 44
#define R9A07G044_PD_SCIF3 45
#define R9A07G044_PD_SCIF4 46
#define R9A07G044_PD_SCI0 47
#define R9A07G044_PD_SCI1 48
#define R9A07G044_PD_IRDA 49
#define R9A07G044_PD_RSPI0 50
#define R9A07G044_PD_RSPI1 51
#define R9A07G044_PD_RSPI2 52
#define R9A07G044_PD_CANFD 53
#define R9A07G044_PD_ADC 54
#define R9A07G044_PD_TSU 55
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */

58
include/dt-bindings/clock/r9a07g054-cpg.h
View File

@@ -226,62 +226,4 @@
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
/* Power domain IDs. */
#define R9A07G054_PD_ALWAYS_ON 0
#define R9A07G054_PD_GIC 1
#define R9A07G054_PD_IA55 2
#define R9A07G054_PD_MHU 3
#define R9A07G054_PD_CORESIGHT 4
#define R9A07G054_PD_SYC 5
#define R9A07G054_PD_DMAC 6
#define R9A07G054_PD_GTM0 7
#define R9A07G054_PD_GTM1 8
#define R9A07G054_PD_GTM2 9
#define R9A07G054_PD_MTU 10
#define R9A07G054_PD_POE3 11
#define R9A07G054_PD_GPT 12
#define R9A07G054_PD_POEGA 13
#define R9A07G054_PD_POEGB 14
#define R9A07G054_PD_POEGC 15
#define R9A07G054_PD_POEGD 16
#define R9A07G054_PD_WDT0 17
#define R9A07G054_PD_WDT1 18
#define R9A07G054_PD_SPI 19
#define R9A07G054_PD_SDHI0 20
#define R9A07G054_PD_SDHI1 21
#define R9A07G054_PD_3DGE 22
#define R9A07G054_PD_ISU 23
#define R9A07G054_PD_VCPL4 24
#define R9A07G054_PD_CRU 25
#define R9A07G054_PD_MIPI_DSI 26
#define R9A07G054_PD_LCDC 27
#define R9A07G054_PD_SSI0 28
#define R9A07G054_PD_SSI1 29
#define R9A07G054_PD_SSI2 30
#define R9A07G054_PD_SSI3 31
#define R9A07G054_PD_SRC 32
#define R9A07G054_PD_USB0 33
#define R9A07G054_PD_USB1 34
#define R9A07G054_PD_USB_PHY 35
#define R9A07G054_PD_ETHER0 36
#define R9A07G054_PD_ETHER1 37
#define R9A07G054_PD_I2C0 38
#define R9A07G054_PD_I2C1 39
#define R9A07G054_PD_I2C2 40
#define R9A07G054_PD_I2C3 41
#define R9A07G054_PD_SCIF0 42
#define R9A07G054_PD_SCIF1 43
#define R9A07G054_PD_SCIF2 44
#define R9A07G054_PD_SCIF3 45
#define R9A07G054_PD_SCIF4 46
#define R9A07G054_PD_SCI0 47
#define R9A07G054_PD_SCI1 48
#define R9A07G054_PD_IRDA 49
#define R9A07G054_PD_RSPI0 50
#define R9A07G054_PD_RSPI1 51
#define R9A07G054_PD_RSPI2 52
#define R9A07G054_PD_CANFD 53
#define R9A07G054_PD_ADC 54
#define R9A07G054_PD_TSU 55
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */

71
include/dt-bindings/clock/r9a08g045-cpg.h
View File

@@ -239,75 +239,4 @@
#define R9A08G045_I3C_PRESETN 92
#define R9A08G045_VBAT_BRESETN 93
/* Power domain IDs. */
#define R9A08G045_PD_ALWAYS_ON 0
#define R9A08G045_PD_GIC 1
#define R9A08G045_PD_IA55 2
#define R9A08G045_PD_MHU 3
#define R9A08G045_PD_CORESIGHT 4
#define R9A08G045_PD_SYC 5
#define R9A08G045_PD_DMAC 6
#define R9A08G045_PD_GTM0 7
#define R9A08G045_PD_GTM1 8
#define R9A08G045_PD_GTM2 9
#define R9A08G045_PD_GTM3 10
#define R9A08G045_PD_GTM4 11
#define R9A08G045_PD_GTM5 12
#define R9A08G045_PD_GTM6 13
#define R9A08G045_PD_GTM7 14
#define R9A08G045_PD_MTU 15
#define R9A08G045_PD_POE3 16
#define R9A08G045_PD_GPT 17
#define R9A08G045_PD_POEGA 18
#define R9A08G045_PD_POEGB 19
#define R9A08G045_PD_POEGC 20
#define R9A08G045_PD_POEGD 21
#define R9A08G045_PD_WDT0 22
#define R9A08G045_PD_XSPI 23
#define R9A08G045_PD_SDHI0 24
#define R9A08G045_PD_SDHI1 25
#define R9A08G045_PD_SDHI2 26
#define R9A08G045_PD_SSI0 27
#define R9A08G045_PD_SSI1 28
#define R9A08G045_PD_SSI2 29
#define R9A08G045_PD_SSI3 30
#define R9A08G045_PD_SRC 31
#define R9A08G045_PD_USB0 32
#define R9A08G045_PD_USB1 33
#define R9A08G045_PD_USB_PHY 34
#define R9A08G045_PD_ETHER0 35
#define R9A08G045_PD_ETHER1 36
#define R9A08G045_PD_I2C0 37
#define R9A08G045_PD_I2C1 38
#define R9A08G045_PD_I2C2 39
#define R9A08G045_PD_I2C3 40
#define R9A08G045_PD_SCIF0 41
#define R9A08G045_PD_SCIF1 42
#define R9A08G045_PD_SCIF2 43
#define R9A08G045_PD_SCIF3 44
#define R9A08G045_PD_SCIF4 45
#define R9A08G045_PD_SCIF5 46
#define R9A08G045_PD_SCI0 47
#define R9A08G045_PD_SCI1 48
#define R9A08G045_PD_IRDA 49
#define R9A08G045_PD_RSPI0 50
#define R9A08G045_PD_RSPI1 51
#define R9A08G045_PD_RSPI2 52
#define R9A08G045_PD_RSPI3 53
#define R9A08G045_PD_RSPI4 54
#define R9A08G045_PD_CANFD 55
#define R9A08G045_PD_ADC 56
#define R9A08G045_PD_TSU 57
#define R9A08G045_PD_OCTA 58
#define R9A08G045_PD_PDM 59
#define R9A08G045_PD_PCI 60
#define R9A08G045_PD_SPDIF 61
#define R9A08G045_PD_I3C 62
#define R9A08G045_PD_VBAT 63
#define R9A08G045_PD_DDR 64
#define R9A08G045_PD_TZCDDR 65
#define R9A08G045_PD_OTFDE_DDR 66
#define R9A08G045_PD_RTC 67
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */

1
include/dt-bindings/clock/renesas,r9a09g056-cpg.h
View File

@@ -20,5 +20,6 @@
#define R9A09G056_USB2_0_CLK_CORE0 9
#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10
#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11
#define R9A09G056_SPI_CLK_SPI 12
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */

1
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
View File

@@ -21,5 +21,6 @@
#define R9A09G057_USB2_0_CLK_CORE1 10
#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11
#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12
#define R9A09G057_SPI_CLK_SPI 13
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */

29
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h Normal file
View File

@@ -0,0 +1,29 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A09G077 CPG Core Clocks */
#define R9A09G077_CLK_CA55C0 0
#define R9A09G077_CLK_CA55C1 1
#define R9A09G077_CLK_CA55C2 2
#define R9A09G077_CLK_CA55C3 3
#define R9A09G077_CLK_CA55S 4
#define R9A09G077_CLK_CR52_CPU0 5
#define R9A09G077_CLK_CR52_CPU1 6
#define R9A09G077_CLK_CKIO 7
#define R9A09G077_CLK_PCLKAH 8
#define R9A09G077_CLK_PCLKAM 9
#define R9A09G077_CLK_PCLKAL 10
#define R9A09G077_CLK_PCLKGPTL 11
#define R9A09G077_CLK_PCLKH 12
#define R9A09G077_CLK_PCLKM 13
#define R9A09G077_CLK_PCLKL 14
#define R9A09G077_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

29
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h Normal file
View File

@@ -0,0 +1,29 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A09G087 CPG Core Clocks */
#define R9A09G087_CLK_CA55C0 0
#define R9A09G087_CLK_CA55C1 1
#define R9A09G087_CLK_CA55C2 2
#define R9A09G087_CLK_CA55C3 3
#define R9A09G087_CLK_CA55S 4
#define R9A09G087_CLK_CR52_CPU0 5
#define R9A09G087_CLK_CR52_CPU1 6
#define R9A09G087_CLK_CKIO 7
#define R9A09G087_CLK_PCLKAH 8
#define R9A09G087_CLK_PCLKAM 9
#define R9A09G087_CLK_PCLKAL 10
#define R9A09G087_CLK_PCLKGPTL 11
#define R9A09G087_CLK_PCLKH 12
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
#define R9A09G087_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */

9
include/dt-bindings/clock/samsung,exynosautov920.h
View File

@@ -286,4 +286,13 @@
#define CLK_MOUT_HSI1_USBDRD_USER 3
#define CLK_MOUT_HSI1_USBDRD 4
/* CMU_HSI2 */
#define FOUT_PLL_ETH 1
#define CLK_MOUT_HSI2_NOC_UFS_USER 2
#define CLK_MOUT_HSI2_UFS_EMBD_USER 3
#define CLK_MOUT_HSI2_ETHERNET 4
#define CLK_MOUT_HSI2_ETHERNET_USER 5
#define CLK_DOUT_HSI2_ETHERNET 6
#define CLK_DOUT_HSI2_ETHERNET_PTP 7
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */

141
include/dt-bindings/clock/spacemit,k1-syscon.h
View File

@@ -78,6 +78,9 @@
#define CLK_APB 31
#define CLK_WDT_BUS 32
/* MPMU resets */
#define RESET_WDT 0
/* APBC clocks */
#define CLK_UART0 0
#define CLK_UART2 1
@@ -180,6 +183,59 @@
#define CLK_TSEN_BUS 98
#define CLK_IPC_AP2AUD_BUS 99
/* APBC resets */
#define RESET_UART0 0
#define RESET_UART2 1
#define RESET_UART3 2
#define RESET_UART4 3
#define RESET_UART5 4
#define RESET_UART6 5
#define RESET_UART7 6
#define RESET_UART8 7
#define RESET_UART9 8
#define RESET_GPIO 9
#define RESET_PWM0 10
#define RESET_PWM1 11
#define RESET_PWM2 12
#define RESET_PWM3 13
#define RESET_PWM4 14
#define RESET_PWM5 15
#define RESET_PWM6 16
#define RESET_PWM7 17
#define RESET_PWM8 18
#define RESET_PWM9 19
#define RESET_PWM10 20
#define RESET_PWM11 21
#define RESET_PWM12 22
#define RESET_PWM13 23
#define RESET_PWM14 24
#define RESET_PWM15 25
#define RESET_PWM16 26
#define RESET_PWM17 27
#define RESET_PWM18 28
#define RESET_PWM19 29
#define RESET_SSP3 30
#define RESET_RTC 31
#define RESET_TWSI0 32
#define RESET_TWSI1 33
#define RESET_TWSI2 34
#define RESET_TWSI4 35
#define RESET_TWSI5 36
#define RESET_TWSI6 37
#define RESET_TWSI7 38
#define RESET_TWSI8 39
#define RESET_TIMERS1 40
#define RESET_TIMERS2 41
#define RESET_AIB 42
#define RESET_ONEWIRE 43
#define RESET_SSPA0 44
#define RESET_SSPA1 45
#define RESET_DRO 46
#define RESET_IR 47
#define RESET_TSEN 48
#define RESET_IPC_AP2AUD 49
#define RESET_CAN0 50
/* APMU clocks */
#define CLK_CCI550 0
#define CLK_CPU_C0_HI 1
@@ -244,4 +300,89 @@
#define CLK_V2D 60
#define CLK_EMMC_BUS 61
/* APMU resets */
#define RESET_CCIC_4X 0
#define RESET_CCIC1_PHY 1
#define RESET_SDH_AXI 2
#define RESET_SDH0 3
#define RESET_SDH1 4
#define RESET_SDH2 5
#define RESET_USBP1_AXI 6
#define RESET_USB_AXI 7
#define RESET_USB30_AHB 8
#define RESET_USB30_VCC 9
#define RESET_USB30_PHY 10
#define RESET_QSPI 11
#define RESET_QSPI_BUS 12
#define RESET_DMA 13
#define RESET_AES 14
#define RESET_VPU 15
#define RESET_GPU 16
#define RESET_EMMC 17
#define RESET_EMMC_X 18
#define RESET_AUDIO_SYS 19
#define RESET_AUDIO_MCU 20
#define RESET_AUDIO_APMU 21
#define RESET_HDMI 22
#define RESET_PCIE0_MASTER 23
#define RESET_PCIE0_SLAVE 24
#define RESET_PCIE0_DBI 25
#define RESET_PCIE0_GLOBAL 26
#define RESET_PCIE1_MASTER 27
#define RESET_PCIE1_SLAVE 28
#define RESET_PCIE1_DBI 29
#define RESET_PCIE1_GLOBAL 30
#define RESET_PCIE2_MASTER 31
#define RESET_PCIE2_SLAVE 32
#define RESET_PCIE2_DBI 33
#define RESET_PCIE2_GLOBAL 34
#define RESET_EMAC0 35
#define RESET_EMAC1 36
#define RESET_JPG 37
#define RESET_CCIC2PHY 38
#define RESET_CCIC3PHY 39
#define RESET_CSI 40
#define RESET_ISP_CPP 41
#define RESET_ISP_BUS 42
#define RESET_ISP 43
#define RESET_ISP_CI 44
#define RESET_DPU_MCLK 45
#define RESET_DPU_ESC 46
#define RESET_DPU_HCLK 47
#define RESET_DPU_SPIBUS 48
#define RESET_DPU_SPI_HBUS 49
#define RESET_V2D 50
#define RESET_MIPI 51
#define RESET_MC 52
/* RCPU resets */
#define RESET_RCPU_SSP0 0
#define RESET_RCPU_I2C0 1
#define RESET_RCPU_UART1 2
#define RESET_RCPU_IR 3
#define RESET_RCPU_CAN 4
#define RESET_RCPU_UART0 5
#define RESET_RCPU_HDMI_AUDIO 6
/* RCPU2 resets */
#define RESET_RCPU2_PWM0 0
#define RESET_RCPU2_PWM1 1
#define RESET_RCPU2_PWM2 2
#define RESET_RCPU2_PWM3 3
#define RESET_RCPU2_PWM4 4
#define RESET_RCPU2_PWM5 5
#define RESET_RCPU2_PWM6 6
#define RESET_RCPU2_PWM7 7
#define RESET_RCPU2_PWM8 8
#define RESET_RCPU2_PWM9 9
/* APBC2 resets */
#define RESET_APBC2_UART1 0
#define RESET_APBC2_SSP2 1
#define RESET_APBC2_TWSI3 2
#define RESET_APBC2_RTC 3
#define RESET_APBC2_TIMERS0 4
#define RESET_APBC2_KPC 5
#define RESET_APBC2_GPIO 6
#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */

1
include/dt-bindings/reset/sun55i-a523-r-ccu.h
View File

@@ -21,5 +21,6 @@
#define RST_BUS_R_IR_RX 12
#define RST_BUS_R_RTC 13
#define RST_BUS_R_CPUCFG 14
#define RST_BUS_R_PPU0 15
#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */

160
include/soc/spacemit/k1-syscon.h Normal file
View File

@@ -0,0 +1,160 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* SpacemiT clock and reset driver definitions for the K1 SoC */
#ifndef __SOC_K1_SYSCON_H__
#define __SOC_K1_SYSCON_H__
/* Auxiliary device used to represent a CCU reset controller */
struct spacemit_ccu_adev {
struct auxiliary_device adev;
struct regmap *regmap;
};
static inline struct spacemit_ccu_adev *
to_spacemit_ccu_adev(struct auxiliary_device *adev)
{
return container_of(adev, struct spacemit_ccu_adev, adev);
}
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
#define APBS_PLL1_SWCR2 0x104
#define APBS_PLL1_SWCR3 0x108
#define APBS_PLL2_SWCR1 0x118
#define APBS_PLL2_SWCR2 0x11c
#define APBS_PLL2_SWCR3 0x120
#define APBS_PLL3_SWCR1 0x124
#define APBS_PLL3_SWCR2 0x128
#define APBS_PLL3_SWCR3 0x12c
/* MPMU register offset */
#define MPMU_POSR 0x0010
#define POSR_PLL1_LOCK BIT(27)
#define POSR_PLL2_LOCK BIT(28)
#define POSR_PLL3_LOCK BIT(29)
#define MPMU_SUCCR 0x0014
#define MPMU_ISCCR 0x0044
#define MPMU_WDTPCR 0x0200
#define MPMU_RIPCCR 0x0210
#define MPMU_ACGR 0x1024
#define MPMU_APBCSCR 0x1050
#define MPMU_SUCCR_1 0x10b0
/* APBC register offset */
#define APBC_UART1_CLK_RST 0x00
#define APBC_UART2_CLK_RST 0x04
#define APBC_GPIO_CLK_RST 0x08
#define APBC_PWM0_CLK_RST 0x0c
#define APBC_PWM1_CLK_RST 0x10
#define APBC_PWM2_CLK_RST 0x14
#define APBC_PWM3_CLK_RST 0x18
#define APBC_TWSI8_CLK_RST 0x20
#define APBC_UART3_CLK_RST 0x24
#define APBC_RTC_CLK_RST 0x28
#define APBC_TWSI0_CLK_RST 0x2c
#define APBC_TWSI1_CLK_RST 0x30
#define APBC_TIMERS1_CLK_RST 0x34
#define APBC_TWSI2_CLK_RST 0x38
#define APBC_AIB_CLK_RST 0x3c
#define APBC_TWSI4_CLK_RST 0x40
#define APBC_TIMERS2_CLK_RST 0x44
#define APBC_ONEWIRE_CLK_RST 0x48
#define APBC_TWSI5_CLK_RST 0x4c
#define APBC_DRO_CLK_RST 0x58
#define APBC_IR_CLK_RST 0x5c
#define APBC_TWSI6_CLK_RST 0x60
#define APBC_COUNTER_CLK_SEL 0x64
#define APBC_TWSI7_CLK_RST 0x68
#define APBC_TSEN_CLK_RST 0x6c
#define APBC_UART4_CLK_RST 0x70
#define APBC_UART5_CLK_RST 0x74
#define APBC_UART6_CLK_RST 0x78
#define APBC_SSP3_CLK_RST 0x7c
#define APBC_SSPA0_CLK_RST 0x80
#define APBC_SSPA1_CLK_RST 0x84
#define APBC_IPC_AP2AUD_CLK_RST 0x90
#define APBC_UART7_CLK_RST 0x94
#define APBC_UART8_CLK_RST 0x98
#define APBC_UART9_CLK_RST 0x9c
#define APBC_CAN0_CLK_RST 0xa0
#define APBC_PWM4_CLK_RST 0xa8
#define APBC_PWM5_CLK_RST 0xac
#define APBC_PWM6_CLK_RST 0xb0
#define APBC_PWM7_CLK_RST 0xb4
#define APBC_PWM8_CLK_RST 0xb8
#define APBC_PWM9_CLK_RST 0xbc
#define APBC_PWM10_CLK_RST 0xc0
#define APBC_PWM11_CLK_RST 0xc4
#define APBC_PWM12_CLK_RST 0xc8
#define APBC_PWM13_CLK_RST 0xcc
#define APBC_PWM14_CLK_RST 0xd0
#define APBC_PWM15_CLK_RST 0xd4
#define APBC_PWM16_CLK_RST 0xd8
#define APBC_PWM17_CLK_RST 0xdc
#define APBC_PWM18_CLK_RST 0xe0
#define APBC_PWM19_CLK_RST 0xe4
/* APMU register offset */
#define APMU_JPG_CLK_RES_CTRL 0x020
#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
#define APMU_ISP_CLK_RES_CTRL 0x038
#define APMU_LCD_CLK_RES_CTRL1 0x044
#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
#define APMU_LCD_CLK_RES_CTRL2 0x04c
#define APMU_CCIC_CLK_RES_CTRL 0x050
#define APMU_SDH0_CLK_RES_CTRL 0x054
#define APMU_SDH1_CLK_RES_CTRL 0x058
#define APMU_USB_CLK_RES_CTRL 0x05c
#define APMU_QSPI_CLK_RES_CTRL 0x060
#define APMU_DMA_CLK_RES_CTRL 0x064
#define APMU_AES_CLK_RES_CTRL 0x068
#define APMU_VPU_CLK_RES_CTRL 0x0a4
#define APMU_GPU_CLK_RES_CTRL 0x0cc
#define APMU_SDH2_CLK_RES_CTRL 0x0e0
#define APMU_PMUA_MC_CTRL 0x0e8
#define APMU_PMU_CC2_AP 0x100
#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
#define APMU_CCI550_CLK_CTRL 0x300
#define APMU_ACLK_CLK_CTRL 0x388
#define APMU_CPU_C0_CLK_CTRL 0x38C
#define APMU_CPU_C1_CLK_CTRL 0x390
#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
/* RCPU register offsets */
#define RCPU_SSP0_CLK_RST 0x0028
#define RCPU_I2C0_CLK_RST 0x0030
#define RCPU_UART1_CLK_RST 0x003c
#define RCPU_CAN_CLK_RST 0x0048
#define RCPU_IR_CLK_RST 0x004c
#define RCPU_UART0_CLK_RST 0x00d8
#define AUDIO_HDMI_CLK_CTRL 0x2044
/* RCPU2 register offsets */
#define RCPU2_PWM0_CLK_RST 0x0000
#define RCPU2_PWM1_CLK_RST 0x0004
#define RCPU2_PWM2_CLK_RST 0x0008
#define RCPU2_PWM3_CLK_RST 0x000c
#define RCPU2_PWM4_CLK_RST 0x0010
#define RCPU2_PWM5_CLK_RST 0x0014
#define RCPU2_PWM6_CLK_RST 0x0018
#define RCPU2_PWM7_CLK_RST 0x001c
#define RCPU2_PWM8_CLK_RST 0x0020
#define RCPU2_PWM9_CLK_RST 0x0024
/* APBC2 register offsets */
#define APBC2_UART1_CLK_RST 0x0000
#define APBC2_SSP2_CLK_RST 0x0004
#define APBC2_TWSI3_CLK_RST 0x0008
#define APBC2_RTC_CLK_RST 0x000c
#define APBC2_TIMERS0_CLK_RST 0x0010
#define APBC2_KPC_CLK_RST 0x0014
#define APBC2_GPIO_CLK_RST 0x001c
#endif /* __SOC_K1_SYSCON_H__ */