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Merge tag 'sunxi-clk-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Browse Source 
Pull Allwinner clk driver updates from Chen-Yu Tsai:

 - Add sigma-delta modulation settings for audio PLL on the H616 SoC,
   crucial for accurate audio reproduction
 - Constify |struct ccu_reset_map| throughout the sunxi-ng clk drivers
 - Fix the audio PLL divider preset on the D1 SoC
 - Switch to of_property_present() for checking DT property presence

* tag 'sunxi-clk-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: Use of_property_present() for non-boolean properties
  clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
  clk: sunxi-ng: Constify struct ccu_reset_map
  clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
This commit is contained in:
Stephen Boyd
2024-11-06 14:37:32 -08:00
parent 9852d85ec9 1054861bc2
commit ea1ba20048
26 changed files with 64 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
View File

@@ -91,7 +91,7 @@ static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
},
};
static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
static const struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
[RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
[RST_BUS_R_TWD] = { 0x12c, BIT(16) },
[RST_BUS_R_PPU] = { 0x1ac, BIT(16) },

4
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
View File

@@ -1232,7 +1232,7 @@ static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
},
};
static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
static const struct ccu_reset_map sun20i_d1_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
[RST_BUS_DI] = { 0x62c, BIT(16) },
@@ -1371,7 +1371,7 @@ static int sun20i_d1_ccu_probe(struct platform_device *pdev)
/* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
val &= ~BIT(1) | BIT(0);
val &= ~(BIT(1) | BIT(0));
writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
/* Force fanout-27M factor N to 0. */

2
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
View File

@@ -1382,7 +1382,7 @@ static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
.num = CLK_NUMBER_SUN7I,
};
static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
static const struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
View File

@@ -166,7 +166,7 @@ static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
[RST_R_APB1_PPU] = { 0x17c, BIT(16) },

2
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
View File

@@ -1061,7 +1061,7 @@ static struct clk_hw_onecell_data sun50i_a100_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a100_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a100_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },

2
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
View File

@@ -858,7 +858,7 @@ static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a64_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

4
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
View File

@@ -179,7 +179,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
[RST_R_APB1_PWM] = { 0x13c, BIT(16) },
@@ -190,7 +190,7 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
};
static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
[RST_R_APB2_I2C] = { 0x19c, BIT(16) },
[RST_R_APB2_RSB] = { 0x1bc, BIT(16) },

2
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
View File

@@ -1076,7 +1076,7 @@ static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h6_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h6_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },

46
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
View File

@@ -216,19 +216,29 @@ static struct ccu_nkmp pll_de_clk = {
};
/*
* TODO: Determine SDM settings for the audio PLL. The manual suggests
* PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b
* for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2,
* pattern=0xe001288c for 22.5792 MHz.
* This clashes with our fixed PLL_POST_DIV_P.
* Sigma-delta modulation settings table obtained from the vendor SDK driver.
* There are additional M0 and M1 divider bits not modelled here, so forced to
* fixed values in the probe routine. Sigma-delta modulation allows providing a
* fractional-N divider in the PLL, to help reaching those specific
* frequencies with less error.
*/
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 },
{ .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
};
#define SUN50I_H616_PLL_AUDIO_REG 0x078
static struct ccu_nm pll_audio_hs_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.m = _SUNXI_CCU_DIV(16, 6),
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
BIT(24), 0x178, BIT(31)),
.fixed_post_div = 2,
.common = {
.features = CCU_FEATURE_FIXED_POSTDIV |
CCU_FEATURE_SIGMA_DELTA_MOD,
.reg = 0x078,
.hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M",
&ccu_nm_ops,
@@ -685,18 +695,20 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
};
/*
* The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
* rates can be set exactly in conjunction with sigma-delta modulation.
* The PLL_AUDIO_4X clock defaults to 24.5714 MHz according to the manual, with
* a final divider of 1. The 2X and 1X clocks use 2 and 4 respectively. The 1x
* clock is set to either 24576000 or 22579200 for 48Khz and 44.1Khz (and
* multiples).
*/
static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
clk_parent_pll_audio,
96, 1, CLK_SET_RATE_PARENT);
4, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
48, 1, CLK_SET_RATE_PARENT);
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
24, 1, CLK_SET_RATE_PARENT);
1, 1, CLK_SET_RATE_PARENT);
static const struct clk_hw *pll_periph0_parents[] = {
&pll_periph0_clk.common.hw
@@ -990,7 +1002,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
@@ -1136,12 +1148,14 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
}
/*
* Force the post-divider of pll-audio to 12 and the output divider
* of it to 2, so 24576000 and 22579200 rates can be set exactly.
* Set the output-divider for the pll-audio clocks (M0) to 2 and the
* input divider (M1) to 1 as recommended by the manual when using
* SDM.
*/
val = readl(reg + SUN50I_H616_PLL_AUDIO_REG);
val &= ~(GENMASK(21, 16) | BIT(0));
writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG);
val &= ~BIT(1);
val |= BIT(0);
writel(val, reg + SUN50I_H616_PLL_AUDIO_REG);
/*
* First clock parent (osc32K) is unusable for CEC. But since there

2
drivers/clk/sunxi-ng/ccu-sun5i.c
View File

@@ -731,7 +731,7 @@ static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
static const struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },

2
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
View File

@@ -1146,7 +1146,7 @@ static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
static const struct ccu_reset_map sun6i_a31_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
View File

@@ -356,7 +356,7 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
const char *fw_name;
/* ext-osc32k was the only input clock in the old binding. */
fw_name = of_property_read_bool(dev->of_node, "clock-names")
fw_name = of_property_present(dev->of_node, "clock-names")
? "ext-osc32k" : NULL;
ext_osc32k_clk = devm_clk_get_optional(dev, fw_name);
if (IS_ERR(ext_osc32k_clk))

2
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
View File

@@ -668,7 +668,7 @@ static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a23_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
View File

@@ -712,7 +712,7 @@ static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a33_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
View File

@@ -797,7 +797,7 @@ static struct clk_hw_onecell_data sun8i_a83t_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

8
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
View File

@@ -146,7 +146,7 @@ static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
.num = CLK_NUMBER_WITH_ROT,
};
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
static const struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* Mixer1 reset line is shared with wb, so only RST_WB is
@@ -156,7 +156,7 @@ static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
static const struct ccu_reset_map sun8i_h3_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* Mixer1 reset line is shared with wb, so only RST_WB is
@@ -166,14 +166,14 @@ static struct ccu_reset_map sun8i_h3_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
static struct ccu_reset_map sun50i_a64_de2_resets[] = {
static const struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
static const struct ccu_reset_map sun50i_h5_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },

4
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View File

@@ -876,7 +876,7 @@ static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
.num = CLK_NUMBER_H5,
};
static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
static const struct ccu_reset_map sun8i_h3_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
@@ -939,7 +939,7 @@ static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
[RST_BUS_SCR0] = { 0x2d8, BIT(20) },
};
static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
static const struct ccu_reset_map sun50i_h5_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

6
drivers/clk/sunxi-ng/ccu-sun8i-r.c
View File

@@ -178,7 +178,7 @@ static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
static const struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_RSB] = { 0xb0, BIT(3) },
@@ -186,14 +186,14 @@ static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
[RST_APB0_I2C] = { 0xb0, BIT(6) },
};
static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
static const struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_UART] = { 0xb0, BIT(4) },
[RST_APB0_I2C] = { 0xb0, BIT(6) },
};
static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
static const struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_RSB] = { 0xb0, BIT(3) },

2
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
View File

@@ -1162,7 +1162,7 @@ static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
static const struct ccu_reset_map sun8i_r40_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

4
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View File

@@ -644,7 +644,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
.num = CLK_I2S0 + 1,
};
static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
static const struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_MBUS] = { 0x0fc, BIT(31) },
@@ -679,7 +679,7 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
};
static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
static const struct ccu_reset_map sun8i_v3_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_MBUS] = { 0x0fc, BIT(31) },

2
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
View File

@@ -177,7 +177,7 @@ static struct clk_hw_onecell_data sun9i_a80_de_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_de_resets[] = {
static const struct ccu_reset_map sun9i_a80_de_resets[] = {
[RST_FE0] = { 0x0c, BIT(0) },
[RST_FE1] = { 0x0c, BIT(1) },
[RST_FE2] = { 0x0c, BIT(2) },

2
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
View File

@@ -68,7 +68,7 @@ static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_usb_resets[] = {
static const struct ccu_reset_map sun9i_a80_usb_resets[] = {
[RST_USB0_HCI] = { 0x0, BIT(17) },
[RST_USB1_HCI] = { 0x0, BIT(18) },
[RST_USB2_HCI] = { 0x0, BIT(19) },

2
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
View File

@@ -1108,7 +1108,7 @@ static struct clk_hw_onecell_data sun9i_a80_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_ccu_resets[] = {
static const struct ccu_reset_map sun9i_a80_ccu_resets[] = {
/* AHB0 reset controls */
[RST_BUS_FD] = { 0x5a0, BIT(0) },
[RST_BUS_VE] = { 0x5a0, BIT(1) },

2
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
View File

@@ -477,7 +477,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
.num = CLK_NUMBER,
};
static struct ccu_reset_map suniv_ccu_resets[] = {
static const struct ccu_reset_map suniv_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },

2
drivers/clk/sunxi-ng/ccu_common.h
View File

@@ -50,7 +50,7 @@ struct sunxi_ccu_desc {
struct clk_hw_onecell_data *hw_clks;
struct ccu_reset_map *resets;
const struct ccu_reset_map *resets;
unsigned long num_resets;
};

2
drivers/clk/sunxi-ng/ccu_reset.h
View File

@@ -17,7 +17,7 @@ struct ccu_reset_map {
struct ccu_reset {
void __iomem *base;
struct ccu_reset_map *reset_map;
const struct ccu_reset_map *reset_map;
spinlock_t *lock;
struct reset_controller_dev rcdev;