soc/tegra: cbb: Add support for CBB fabrics in Tegra264
Add support for CBB 2.0 based fabrics in Tegra264 SoC using DT. Fabrics reporting errors are: SYSTEM, TOP0, UPHY0 and VISION. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sumit Gupta
committed by
Thierry Reding
Thierry Reding
parent
5f2c2c4399
commit
fa4854a9f5
@@ -89,6 +89,34 @@ enum tegra234_cbb_fabric_ids {
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T234_MAX_FABRIC_ID,
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};
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enum tegra264_cbb_fabric_ids {
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T264_SYSTEM_CBB_FABRIC_ID,
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T264_TOP_0_CBB_FABRIC_ID,
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T264_VISION_CBB_FABRIC_ID,
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T264_DISP_USB_CBB_FABRIC_ID,
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T264_UPHY0_CBB_FABRIC_ID,
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T264_RSVD0_FABRIC_ID,
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T264_RSVD1_FABRIC_ID,
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T264_RSVD2_FABRIC_ID,
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T264_RSVD3_FABRIC_ID,
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T264_RSVD4_FABRIC_ID,
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T264_RSVD5_FABRIC_ID,
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T264_AON_FABRIC_ID,
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T264_PSC_FABRIC_ID,
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T264_OESP_FABRIC_ID,
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T264_APE_FABRIC_ID,
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T264_BPMP_FABRIC_ID,
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T264_RCE_0_FABRIC_ID,
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T264_RCE_1_FABRIC_ID,
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T264_RSVD6_FABRIC_ID,
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T264_DCE_FABRIC_ID,
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T264_FSI_FABRIC_ID,
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T264_ISC_FABRIC_ID,
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T264_SB_FABRIC_ID,
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T264_ISC_CPU_FABRIC_ID,
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T264_RSVD7_FABRIC_ID,
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};
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struct tegra234_target_lookup {
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const char *name;
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unsigned int offset;
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@@ -455,6 +483,17 @@ static void print_errlog_err(struct seq_file *file, struct tegra234_cbb *cbb)
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tegra_cbb_print_err(file, "\t Fabric\t\t: %s (id:%#x)\n",
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cbb->fabric->fab_list[fab_id].name, fab_id);
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if (of_machine_is_compatible("nvidia,tegra264") && fab_id == T264_UPHY0_CBB_FABRIC_ID) {
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/*
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* In T264, AON Fabric ID value is incorrectly same as UPHY0 fabric ID.
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* For 'ID = 0x4', we must check for the address which caused the error
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* to find the correct fabric which returned error.
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*/
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tegra_cbb_print_err(file, "\t or Fabric\t\t: %s\n",
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cbb->fabric->fab_list[T264_AON_FABRIC_ID].name);
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tegra_cbb_print_err(file, "\t Please use Address to determine correct fabric.\n");
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}
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tegra_cbb_print_err(file, "\t Target_Id\t\t: %#x\n", target_id);
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tegra_cbb_print_err(file, "\t Burst_length\t\t: %#x\n", burst_length);
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tegra_cbb_print_err(file, "\t Burst_type\t\t: %#x\n", burst_type);
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@@ -1143,6 +1182,242 @@ static const struct tegra234_cbb_fabric tegra241_bpmp_fabric = {
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.firewall_wr_ctl = 0x8e8,
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};
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static const char * const tegra264_initiator_id[] = {
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[0x0] = "TZ",
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[0x1] = "CCPLEX",
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[0x2] = "ISC",
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[0x3] = "BPMP_FW",
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[0x4] = "AON",
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[0x5] = "MSS_SEQ",
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[0x6] = "GPCDMA_P",
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[0x7] = "TSECA_NONSECURE",
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[0x8] = "TSECA_LIGHTSECURE",
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[0x9] = "TSECA_HEAVYSECURE",
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[0xa] = "CORESIGHT",
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[0xb] = "APE_0",
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[0xc] = "APE_1",
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[0xd] = "PEATRANS",
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[0xe] = "JTAGM_DFT",
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[0xf] = "RCE",
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[0x10] = "DCE",
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[0x11] = "PSC_FW_USER",
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[0x12] = "PSC_FW_SUPERVISOR",
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[0x13] = "PSC_FW_MACHINE",
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[0x14] = "PSC_BOOT",
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[0x15] = "BPMP_BOOT",
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[0x16] = "GPU_0",
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[0x17] = "GPU_1",
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[0x18] = "GPU_2",
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[0x19] = "GPU_3",
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[0x1a] = "GPU_4",
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[0x1b] = "PSC_EXT_BOOT",
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[0x1c] = "PSC_EXT_RUNTIME",
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[0x1d] = "OESP_EXT",
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[0x1e] = "SB_EXT",
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[0x1f] = "FSI_SAFETY_0",
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[0x20] = "FSI_SAFETY_1",
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[0x21] = "FSI_SAFETY_2",
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[0x22] = "FSI_SAFETY_3",
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[0x23] = "FSI_CHSM",
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[0x24] = "RCE_1",
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[0x25] = "BPMP_OEM_FW",
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[0x26 ... 0x3d] = "RSVD",
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[0x3e] = "CBB_SMN",
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[0x3f] = "CBB_RSVD"
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};
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static const struct tegra234_target_lookup tegra264_top0_cbb_target_map[] = {
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{ "RSVD", 0x000000 },
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{ "CBB_CENTRAL", 0xC020000 },
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{ "AXI2APB_1", 0x80000 },
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{ "AXI2APB_10", 0x81000 },
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{ "AXI2APB_11", 0x82000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "AXI2APB_14", 0x83000 },
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{ "AXI2APB_15", 0x84000 },
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{ "AXI2APB_16", 0x85000 },
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{ "AXI2APB_17", 0x86000 },
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{ "AXI2APB_2", 0x87000 },
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{ "AXI2APB_3", 0x88000 },
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{ "RSVD", 0x00000 },
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{ "AXI2APB_5", 0x8A000 },
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{ "AXI2APB_6", 0x8B000 },
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{ "AXI2APB_7", 0x8C000 },
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{ "AXI2APB_8", 0x8D000 },
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{ "AXI2APB_9", 0x8E000 },
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{ "FSI_SLAVE", 0x64000 },
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{ "DISP_USB_CBB_T", 0x65000 },
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{ "SYSTEM_CBB_T", 0x66000 },
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{ "UPHY0_CBB_T", 0x67000 },
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{ "VISION_CBB_T", 0x68000 },
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{ "CCPLEX_SLAVE", 0x69000 },
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{ "PCIE_C0", 0x6A000 },
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{ "SMN_UCF_RX_0", 0x6B000 },
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{ "SMN_UCF_RX_1", 0x6C000 },
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{ "AXI2APB_4", 0x89000 },
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};
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static const struct tegra234_target_lookup tegra264_sys_cbb_target_map[] = {
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{ "RSVD", 0x00000 },
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{ "AXI2APB_1", 0xE1000 },
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{ "RSVD", 0x00000 },
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{ "AON_SLAVE", 0x79000 },
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{ "APE_SLAVE", 0x73000 },
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{ "BPMP_SLAVE", 0x74000 },
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{ "OESP_SLAVE", 0x75000 },
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{ "PSC_SLAVE", 0x76000 },
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{ "SB_SLAVE", 0x7A000 },
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{ "SMN_SYSTEM_RX", 0x7B000 },
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{ "STM", 0x77000 },
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{ "RSVD", 0x00000 },
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{ "AXI2APB_3", 0xE3000 },
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{ "TOP_CBB_T", 0x7C000 },
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{ "AXI2APB_2", 0xE4000 },
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{ "AXI2APB_4", 0xE5000 },
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{ "AXI2APB_5", 0xE6000 },
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};
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static const struct tegra234_target_lookup tegra264_uphy0_cbb_target_map[] = {
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[0 ... 20] = { "RSVD", 0x00000 },
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{ "AXI2APB_1", 0x71000 },
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{ "RSVD", 0x00000 },
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{ "AXI2APB_3", 0x75000 },
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{ "SMN_UPHY0_RX", 0x53000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "PCIE_C4", 0x4B000 },
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{ "AXI2APB_2", 0x74000 },
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{ "AXI2APB_4", 0x76000 },
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{ "AXI2APB_5", 0x77000 },
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{ "RSVD", 0x00000 },
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{ "AXI2APB_7", 0x79000 },
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{ "PCIE_C2", 0x56000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "PCIE_C1", 0x55000 },
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{ "RSVD", 0x00000 },
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{ "AXI2APB_10", 0x72000 },
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{ "AXI2APB_11", 0x7C000 },
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{ "AXI2APB_8", 0x7A000 },
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{ "AXI2APB_9", 0x7B000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "PCIE_C5", 0x4E000 },
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{ "PCIE_C3", 0x58000 },
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{ "RSVD", 0x00000 },
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{ "ISC_SLAVE", 0x54000 },
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{ "TOP_CBB_T", 0x57000 },
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{ "AXI2APB_12", 0x7D000 },
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{ "AXI2APB_13", 0x70000 },
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{ "AXI2APB_6", 0x7E000 },
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};
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static const struct tegra234_target_lookup tegra264_vision_cbb_target_map[] = {
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[0 ... 5] = { "RSVD", 0x0 },
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{ "HOST1X", 0x45000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "AXI2APB_2", 0x71000 },
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{ "RSVD", 0x00000 },
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{ "RSVD", 0x00000 },
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{ "SMN_VISION_RX", 0x47000 },
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[13 ... 19] = { "RSVD", 0x0 },
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{ "RCE_0_SLAVE", 0x4B000 },
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{ "RCE_1_SLAVE", 0x4C000 },
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{ "AXI2APB_1", 0x72000 },
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{ "AXI2APB_3", 0x73000 },
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{ "TOP_CBB_T", 0x4D000 },
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};
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static const struct tegra234_fabric_lookup tegra264_cbb_fab_list[] = {
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[T264_SYSTEM_CBB_FABRIC_ID] = { "system-cbb-fabric", true,
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tegra264_sys_cbb_target_map,
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ARRAY_SIZE(tegra264_sys_cbb_target_map) },
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[T264_TOP_0_CBB_FABRIC_ID] = { "top0-cbb-fabric", true,
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tegra264_top0_cbb_target_map,
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ARRAY_SIZE(tegra264_top0_cbb_target_map) },
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[T264_VISION_CBB_FABRIC_ID] = { "vision-cbb-fabric", true,
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tegra264_vision_cbb_target_map,
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ARRAY_SIZE(tegra264_vision_cbb_target_map) },
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[T264_DISP_USB_CBB_FABRIC_ID] = { "disp-usb-cbb-fabric" },
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[T264_UPHY0_CBB_FABRIC_ID] = { "uphy0-cbb-fabric", true,
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tegra264_uphy0_cbb_target_map,
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ARRAY_SIZE(tegra264_uphy0_cbb_target_map) },
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[T264_AON_FABRIC_ID] = { "aon-fabric" },
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[T264_PSC_FABRIC_ID] = { "psc-fabric" },
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[T264_OESP_FABRIC_ID] = { "oesp-fabric" },
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[T264_APE_FABRIC_ID] = { "ape-fabirc" },
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[T264_BPMP_FABRIC_ID] = { "bpmp-fabric" },
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[T264_RCE_0_FABRIC_ID] = { "rce0-fabric" },
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[T264_RCE_1_FABRIC_ID] = { "rce1-fabric" },
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[T264_DCE_FABRIC_ID] = { "dce-fabric" },
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[T264_FSI_FABRIC_ID] = { "fsi-fabric" },
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[T264_ISC_FABRIC_ID] = { "isc-fabric" },
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[T264_SB_FABRIC_ID] = { "sb-fabric" },
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[T264_ISC_CPU_FABRIC_ID] = { "isc-cpu-fabric" },
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};
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static const struct tegra234_cbb_fabric tegra264_top0_cbb_fabric = {
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.fab_id = T264_TOP_0_CBB_FABRIC_ID,
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.fab_list = tegra264_cbb_fab_list,
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.initiator_id = tegra264_initiator_id,
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.errors = tegra241_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
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.err_intr_enbl = 0x7,
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.err_status_clr = 0x1ff007f,
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.notifier_offset = 0x90000,
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.off_mask_erd = 0x4a004,
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.firewall_base = 0x3c0000,
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.firewall_ctl = 0x5b0,
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.firewall_wr_ctl = 0x5a8,
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};
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static const struct tegra234_cbb_fabric tegra264_sys_cbb_fabric = {
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.fab_id = T264_SYSTEM_CBB_FABRIC_ID,
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.fab_list = tegra264_cbb_fab_list,
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.initiator_id = tegra264_initiator_id,
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.errors = tegra241_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
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.err_intr_enbl = 0xf,
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.err_status_clr = 0x1ff007f,
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.notifier_offset = 0x40000,
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.firewall_base = 0x29c000,
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.firewall_ctl = 0x170,
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.firewall_wr_ctl = 0x168,
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};
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static const struct tegra234_cbb_fabric tegra264_uphy0_cbb_fabric = {
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.fab_id = T264_UPHY0_CBB_FABRIC_ID,
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.fab_list = tegra264_cbb_fab_list,
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.initiator_id = tegra264_initiator_id,
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.errors = tegra241_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
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.err_intr_enbl = 0x1,
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.err_status_clr = 0x1ff007f,
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.notifier_offset = 0x80000,
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.firewall_base = 0x360000,
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.firewall_ctl = 0x590,
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.firewall_wr_ctl = 0x588,
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};
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static const struct tegra234_cbb_fabric tegra264_vision_cbb_fabric = {
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.fab_id = T264_VISION_CBB_FABRIC_ID,
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.fab_list = tegra264_cbb_fab_list,
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.initiator_id = tegra264_initiator_id,
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.errors = tegra241_cbb_errors,
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.max_errors = ARRAY_SIZE(tegra241_cbb_errors),
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.err_intr_enbl = 0x1,
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.err_status_clr = 0x1ff007f,
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.notifier_offset = 0x80000,
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.firewall_base = 0x290000,
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.firewall_ctl = 0x5d0,
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.firewall_wr_ctl = 0x5c8,
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};
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static const struct of_device_id tegra234_cbb_dt_ids[] = {
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{ .compatible = "nvidia,tegra234-cbb-fabric", .data = &tegra234_cbb_fabric },
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{ .compatible = "nvidia,tegra234-aon-fabric", .data = &tegra234_aon_fabric },
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@@ -1150,6 +1425,10 @@ static const struct of_device_id tegra234_cbb_dt_ids[] = {
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{ .compatible = "nvidia,tegra234-dce-fabric", .data = &tegra234_dce_fabric },
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{ .compatible = "nvidia,tegra234-rce-fabric", .data = &tegra234_rce_fabric },
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{ .compatible = "nvidia,tegra234-sce-fabric", .data = &tegra234_sce_fabric },
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{ .compatible = "nvidia,tegra264-sys-cbb-fabric", .data = &tegra264_sys_cbb_fabric },
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{ .compatible = "nvidia,tegra264-top0-cbb-fabric", .data = &tegra264_top0_cbb_fabric },
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{ .compatible = "nvidia,tegra264-uphy0-cbb-fabric", .data = &tegra264_uphy0_cbb_fabric },
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{ .compatible = "nvidia,tegra264-vision-cbb-fabric", .data = &tegra264_vision_cbb_fabric },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids);
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