clk: sophgo: Add PLL clock controller support for SG2044 SoC
Add PLL clock driver and clock definition for SG2044 SoC. Link: https://lore.kernel.org/r/20250418020325.421257-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Inochi Amaoto
@@ -37,3 +37,13 @@ config CLK_SOPHGO_SG2042_RPGATE
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This clock IP depends on SG2042 Clock Generator because it uses
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clock from Clock Generator IP as input.
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This driver provides Gate function for RP.
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config CLK_SOPHGO_SG2044_PLL
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tristate "Sophgo SG2044 PLL clock controller support"
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depends on ARCH_SOPHGO || COMPILE_TEST
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select MFD_SYSCON
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select REGMAP_MMIO
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help
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This driver supports the PLL clock controller on the Sophgo
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SG2044 SoC. This controller requires 25M oscillator as input.
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This clock control provides PLL clocks on the SoC.
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@@ -9,3 +9,4 @@ clk-sophgo-cv1800-y += clk-cv18xx-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o
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obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
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obj-$(CONFIG_CLK_SOPHGO_SG2044_PLL) += clk-sg2044-pll.o
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628
drivers/clk/sophgo/clk-sg2044-pll.c
Normal file
628
drivers/clk/sophgo/clk-sg2044-pll.c
Normal file
@@ -0,0 +1,628 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Sophgo SG2044 PLL clock controller driver
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*
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* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
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*/
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/cleanup.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/math64.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/clock/sophgo,sg2044-pll.h>
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/* Low Control part */
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#define PLL_VCOSEL_MASK GENMASK(17, 16)
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/* High Control part */
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#define PLL_FBDIV_MASK GENMASK(11, 0)
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#define PLL_REFDIV_MASK GENMASK(17, 12)
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#define PLL_POSTDIV1_MASK GENMASK(20, 18)
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#define PLL_POSTDIV2_MASK GENMASK(23, 21)
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#define PLL_CALIBRATE_EN BIT(24)
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#define PLL_CALIBRATE_MASK GENMASK(29, 27)
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#define PLL_CALIBRATE_DEFAULT FIELD_PREP(PLL_CALIBRATE_MASK, 2)
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#define PLL_UPDATE_EN BIT(30)
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#define PLL_HIGH_CTRL_MASK \
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(PLL_FBDIV_MASK | PLL_REFDIV_MASK | \
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PLL_POSTDIV1_MASK | PLL_POSTDIV2_MASK | \
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PLL_CALIBRATE_EN | PLL_CALIBRATE_MASK | \
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PLL_UPDATE_EN)
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#define PLL_HIGH_CTRL_OFFSET 4
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#define PLL_VCOSEL_1G6 0x2
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#define PLL_VCOSEL_2G4 0x3
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#define PLL_LIMIT_FOUTVCO 0
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#define PLL_LIMIT_FOUT 1
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#define PLL_LIMIT_REFDIV 2
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#define PLL_LIMIT_FBDIV 3
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#define PLL_LIMIT_POSTDIV1 4
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#define PLL_LIMIT_POSTDIV2 5
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#define for_each_pll_limit_range(_var, _limit) \
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for (_var = (_limit)->min; _var <= (_limit)->max; _var++)
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struct sg2044_pll_limit {
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u64 min;
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u64 max;
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};
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struct sg2044_pll_internal {
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u32 ctrl_offset;
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u32 status_offset;
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u32 enable_offset;
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u8 status_lock_bit;
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u8 status_updating_bit;
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u8 enable_bit;
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const struct sg2044_pll_limit *limits;
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};
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struct sg2044_clk_common {
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struct clk_hw hw;
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struct regmap *regmap;
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spinlock_t *lock;
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unsigned int id;
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};
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struct sg2044_pll {
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struct sg2044_clk_common common;
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struct sg2044_pll_internal pll;
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unsigned int syscon_offset;
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};
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struct sg2044_pll_desc_data {
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struct sg2044_clk_common * const *pll;
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u16 num_pll;
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};
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#define SG2044_SYSCON_PLL_OFFSET 0x98
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struct sg2044_pll_ctrl {
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spinlock_t lock;
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struct clk_hw_onecell_data data;
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};
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#define hw_to_sg2044_clk_common(_hw) \
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container_of((_hw), struct sg2044_clk_common, hw)
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static inline bool sg2044_clk_fit_limit(u64 value,
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const struct sg2044_pll_limit *limit)
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{
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return value >= limit->min && value <= limit->max;
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}
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static inline struct sg2044_pll *hw_to_sg2044_pll(struct clk_hw *hw)
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{
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return container_of(hw_to_sg2044_clk_common(hw),
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struct sg2044_pll, common);
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}
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static unsigned long sg2044_pll_calc_vco_rate(unsigned long parent_rate,
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unsigned long refdiv,
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unsigned long fbdiv)
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{
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u64 numerator = parent_rate * fbdiv;
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return div64_ul(numerator, refdiv);
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}
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static unsigned long sg2044_pll_calc_rate(unsigned long parent_rate,
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unsigned long refdiv,
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unsigned long fbdiv,
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unsigned long postdiv1,
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unsigned long postdiv2)
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{
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u64 numerator, denominator;
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numerator = parent_rate * fbdiv;
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denominator = refdiv * (postdiv1 + 1) * (postdiv2 + 1);
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return div64_u64(numerator, denominator);
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}
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static unsigned long sg2044_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
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u32 value;
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int ret;
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ret = regmap_read(pll->common.regmap,
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pll->syscon_offset + pll->pll.ctrl_offset + PLL_HIGH_CTRL_OFFSET,
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&value);
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if (ret < 0)
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return 0;
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return sg2044_pll_calc_rate(parent_rate,
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FIELD_GET(PLL_REFDIV_MASK, value),
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FIELD_GET(PLL_FBDIV_MASK, value),
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FIELD_GET(PLL_POSTDIV1_MASK, value),
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FIELD_GET(PLL_POSTDIV2_MASK, value));
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}
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static bool pll_is_better_rate(unsigned long target, unsigned long now,
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unsigned long best)
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{
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return abs_diff(target, now) < abs_diff(target, best);
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}
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static int sg2042_pll_compute_postdiv(const struct sg2044_pll_limit *limits,
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unsigned long target,
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unsigned long parent_rate,
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unsigned int refdiv,
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unsigned int fbdiv,
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unsigned int *postdiv1,
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unsigned int *postdiv2)
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{
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unsigned int div1, div2;
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unsigned long tmp, best_rate = 0;
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unsigned int best_div1 = 0, best_div2 = 0;
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for_each_pll_limit_range(div2, &limits[PLL_LIMIT_POSTDIV2]) {
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for_each_pll_limit_range(div1, &limits[PLL_LIMIT_POSTDIV1]) {
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tmp = sg2044_pll_calc_rate(parent_rate,
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refdiv, fbdiv,
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div1, div2);
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if (tmp > target)
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continue;
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if (pll_is_better_rate(target, tmp, best_rate)) {
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best_div1 = div1;
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best_div2 = div2;
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best_rate = tmp;
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if (tmp == target)
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goto find;
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}
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}
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}
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find:
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if (best_rate) {
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*postdiv1 = best_div1;
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*postdiv2 = best_div2;
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return 0;
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}
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return -EINVAL;
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}
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static int sg2044_compute_pll_setting(const struct sg2044_pll_limit *limits,
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unsigned long req_rate,
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unsigned long parent_rate,
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unsigned int *value)
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{
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unsigned int refdiv, fbdiv, postdiv1, postdiv2;
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unsigned int best_refdiv, best_fbdiv, best_postdiv1, best_postdiv2;
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unsigned long tmp, best_rate = 0;
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int ret;
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for_each_pll_limit_range(fbdiv, &limits[PLL_LIMIT_FBDIV]) {
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for_each_pll_limit_range(refdiv, &limits[PLL_LIMIT_REFDIV]) {
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u64 vco = sg2044_pll_calc_vco_rate(parent_rate,
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refdiv, fbdiv);
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if (!sg2044_clk_fit_limit(vco, &limits[PLL_LIMIT_FOUTVCO]))
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continue;
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ret = sg2042_pll_compute_postdiv(limits,
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req_rate, parent_rate,
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refdiv, fbdiv,
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&postdiv1, &postdiv2);
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if (ret)
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continue;
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tmp = sg2044_pll_calc_rate(parent_rate,
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refdiv, fbdiv,
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postdiv1, postdiv2);
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if (pll_is_better_rate(req_rate, tmp, best_rate)) {
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best_refdiv = refdiv;
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best_fbdiv = fbdiv;
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best_postdiv1 = postdiv1;
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best_postdiv2 = postdiv2;
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best_rate = tmp;
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if (tmp == req_rate)
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goto find;
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}
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}
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}
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find:
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if (best_rate) {
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*value = FIELD_PREP(PLL_REFDIV_MASK, best_refdiv) |
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FIELD_PREP(PLL_FBDIV_MASK, best_fbdiv) |
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FIELD_PREP(PLL_POSTDIV1_MASK, best_postdiv1) |
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FIELD_PREP(PLL_POSTDIV2_MASK, best_postdiv2);
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return 0;
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}
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return -EINVAL;
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}
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static int sg2044_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
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unsigned int value;
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u64 target;
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int ret;
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target = clamp(req->rate, pll->pll.limits[PLL_LIMIT_FOUT].min,
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pll->pll.limits[PLL_LIMIT_FOUT].max);
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ret = sg2044_compute_pll_setting(pll->pll.limits, target,
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req->best_parent_rate, &value);
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if (ret < 0)
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return ret;
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req->rate = sg2044_pll_calc_rate(req->best_parent_rate,
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FIELD_GET(PLL_REFDIV_MASK, value),
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FIELD_GET(PLL_FBDIV_MASK, value),
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FIELD_GET(PLL_POSTDIV1_MASK, value),
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FIELD_GET(PLL_POSTDIV2_MASK, value));
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return 0;
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}
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static int sg2044_pll_poll_update(struct sg2044_pll *pll)
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{
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int ret;
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unsigned int value;
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ret = regmap_read_poll_timeout_atomic(pll->common.regmap,
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pll->syscon_offset + pll->pll.status_offset,
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value,
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(value & BIT(pll->pll.status_lock_bit)),
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1, 100000);
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if (ret)
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return ret;
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return regmap_read_poll_timeout_atomic(pll->common.regmap,
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pll->syscon_offset + pll->pll.status_offset,
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value,
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(!(value & BIT(pll->pll.status_updating_bit))),
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1, 100000);
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}
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static int sg2044_pll_enable(struct sg2044_pll *pll, bool en)
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{
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if (en) {
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if (sg2044_pll_poll_update(pll) < 0)
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pr_warn("%s: fail to lock pll\n", clk_hw_get_name(&pll->common.hw));
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return regmap_set_bits(pll->common.regmap,
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pll->syscon_offset + pll->pll.enable_offset,
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BIT(pll->pll.enable_bit));
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}
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return regmap_clear_bits(pll->common.regmap,
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pll->syscon_offset + pll->pll.enable_offset,
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BIT(pll->pll.enable_bit));
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}
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static int sg2044_pll_update_vcosel(struct sg2044_pll *pll, u64 rate)
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{
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unsigned int sel;
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if (rate < U64_C(2400000000))
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sel = PLL_VCOSEL_1G6;
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else
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sel = PLL_VCOSEL_2G4;
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return regmap_write_bits(pll->common.regmap,
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pll->syscon_offset + pll->pll.ctrl_offset,
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PLL_VCOSEL_MASK,
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FIELD_PREP(PLL_VCOSEL_MASK, sel));
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}
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static int sg2044_pll_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
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unsigned int value;
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u64 vco;
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int ret;
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ret = sg2044_compute_pll_setting(pll->pll.limits, rate,
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parent_rate, &value);
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if (ret < 0)
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return ret;
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vco = sg2044_pll_calc_vco_rate(parent_rate,
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FIELD_GET(PLL_REFDIV_MASK, value),
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FIELD_GET(PLL_FBDIV_MASK, value));
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value |= PLL_CALIBRATE_EN;
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value |= PLL_CALIBRATE_DEFAULT;
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value |= PLL_UPDATE_EN;
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guard(spinlock_irqsave)(pll->common.lock);
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ret = sg2044_pll_enable(pll, false);
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if (ret)
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return ret;
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sg2044_pll_update_vcosel(pll, vco);
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regmap_write_bits(pll->common.regmap,
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pll->syscon_offset + pll->pll.ctrl_offset +
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PLL_HIGH_CTRL_OFFSET,
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PLL_HIGH_CTRL_MASK, value);
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sg2044_pll_enable(pll, true);
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return ret;
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}
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static const struct clk_ops sg2044_pll_ops = {
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.recalc_rate = sg2044_pll_recalc_rate,
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.determine_rate = sg2044_pll_determine_rate,
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.set_rate = sg2044_pll_set_rate,
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};
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static const struct clk_ops sg2044_pll_ro_ops = {
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.recalc_rate = sg2044_pll_recalc_rate,
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};
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#define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \
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{ \
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.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
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_op, (_flags)), \
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.id = (_id), \
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}
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#define DEFINE_SG2044_PLL(_id, _name, _parent, _flags, \
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_ctrl_offset, \
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_status_offset, _status_lock_bit, \
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_status_updating_bit, \
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_enable_offset, _enable_bit, \
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_limits) \
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struct sg2044_pll _name = { \
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.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
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&sg2044_pll_ops, \
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(_flags)), \
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.pll = { \
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.ctrl_offset = (_ctrl_offset), \
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.status_offset = (_status_offset), \
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.enable_offset = (_enable_offset), \
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.status_lock_bit = (_status_lock_bit), \
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.status_updating_bit = (_status_updating_bit), \
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.enable_bit = (_enable_bit), \
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.limits = (_limits), \
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}, \
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}
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#define DEFINE_SG2044_PLL_RO(_id, _name, _parent, _flags, \
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_ctrl_offset, \
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_status_offset, _status_lock_bit, \
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_status_updating_bit, \
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_enable_offset, _enable_bit, \
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_limits) \
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struct sg2044_pll _name = { \
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.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
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&sg2044_pll_ro_ops, \
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(_flags)), \
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.pll = { \
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.ctrl_offset = (_ctrl_offset), \
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.status_offset = (_status_offset), \
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.enable_offset = (_enable_offset), \
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.status_lock_bit = (_status_lock_bit), \
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.status_updating_bit = (_status_updating_bit), \
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.enable_bit = (_enable_bit), \
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.limits = (_limits), \
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}, \
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}
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static const struct clk_parent_data osc_parents[] = {
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{ .index = 0 },
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};
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static const struct sg2044_pll_limit pll_limits[] = {
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[PLL_LIMIT_FOUTVCO] = {
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.min = U64_C(1600000000),
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.max = U64_C(3200000000),
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},
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[PLL_LIMIT_FOUT] = {
|
||||
.min = U64_C(25000),
|
||||
.max = U64_C(3200000000),
|
||||
},
|
||||
[PLL_LIMIT_REFDIV] = {
|
||||
.min = U64_C(1),
|
||||
.max = U64_C(63),
|
||||
},
|
||||
[PLL_LIMIT_FBDIV] = {
|
||||
.min = U64_C(8),
|
||||
.max = U64_C(1066),
|
||||
},
|
||||
[PLL_LIMIT_POSTDIV1] = {
|
||||
.min = U64_C(0),
|
||||
.max = U64_C(7),
|
||||
},
|
||||
[PLL_LIMIT_POSTDIV2] = {
|
||||
.min = U64_C(0),
|
||||
.max = U64_C(7),
|
||||
},
|
||||
};
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_FPLL0, clk_fpll0, osc_parents, CLK_IS_CRITICAL,
|
||||
0x58, 0x00, 22, 6,
|
||||
0x04, 6, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_FPLL1, clk_fpll1, osc_parents, CLK_IS_CRITICAL,
|
||||
0x60, 0x00, 23, 7,
|
||||
0x04, 7, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_FPLL2, clk_fpll2, osc_parents, CLK_IS_CRITICAL,
|
||||
0x20, 0x08, 16, 0,
|
||||
0x0c, 0, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL0, clk_dpll0, osc_parents, CLK_IS_CRITICAL,
|
||||
0x68, 0x00, 24, 8,
|
||||
0x04, 8, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL1, clk_dpll1, osc_parents, CLK_IS_CRITICAL,
|
||||
0x70, 0x00, 25, 9,
|
||||
0x04, 9, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL2, clk_dpll2, osc_parents, CLK_IS_CRITICAL,
|
||||
0x78, 0x00, 26, 10,
|
||||
0x04, 10, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL3, clk_dpll3, osc_parents, CLK_IS_CRITICAL,
|
||||
0x80, 0x00, 27, 11,
|
||||
0x04, 11, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL4, clk_dpll4, osc_parents, CLK_IS_CRITICAL,
|
||||
0x88, 0x00, 28, 12,
|
||||
0x04, 12, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL5, clk_dpll5, osc_parents, CLK_IS_CRITICAL,
|
||||
0x90, 0x00, 29, 13,
|
||||
0x04, 13, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL6, clk_dpll6, osc_parents, CLK_IS_CRITICAL,
|
||||
0x98, 0x00, 30, 14,
|
||||
0x04, 14, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL_RO(CLK_DPLL7, clk_dpll7, osc_parents, CLK_IS_CRITICAL,
|
||||
0xa0, 0x00, 31, 15,
|
||||
0x04, 15, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL(CLK_MPLL0, clk_mpll0, osc_parents, CLK_IS_CRITICAL,
|
||||
0x28, 0x00, 16, 0,
|
||||
0x04, 0, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL(CLK_MPLL1, clk_mpll1, osc_parents, CLK_IS_CRITICAL,
|
||||
0x30, 0x00, 17, 1,
|
||||
0x04, 1, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL(CLK_MPLL2, clk_mpll2, osc_parents, CLK_IS_CRITICAL,
|
||||
0x38, 0x00, 18, 2,
|
||||
0x04, 2, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL(CLK_MPLL3, clk_mpll3, osc_parents, CLK_IS_CRITICAL,
|
||||
0x40, 0x00, 19, 3,
|
||||
0x04, 3, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL(CLK_MPLL4, clk_mpll4, osc_parents, CLK_IS_CRITICAL,
|
||||
0x48, 0x00, 20, 4,
|
||||
0x04, 4, pll_limits);
|
||||
|
||||
static DEFINE_SG2044_PLL(CLK_MPLL5, clk_mpll5, osc_parents, CLK_IS_CRITICAL,
|
||||
0x50, 0x00, 21, 5,
|
||||
0x04, 5, pll_limits);
|
||||
|
||||
static struct sg2044_clk_common * const sg2044_pll_commons[] = {
|
||||
&clk_fpll0.common,
|
||||
&clk_fpll1.common,
|
||||
&clk_fpll2.common,
|
||||
&clk_dpll0.common,
|
||||
&clk_dpll1.common,
|
||||
&clk_dpll2.common,
|
||||
&clk_dpll3.common,
|
||||
&clk_dpll4.common,
|
||||
&clk_dpll5.common,
|
||||
&clk_dpll6.common,
|
||||
&clk_dpll7.common,
|
||||
&clk_mpll0.common,
|
||||
&clk_mpll1.common,
|
||||
&clk_mpll2.common,
|
||||
&clk_mpll3.common,
|
||||
&clk_mpll4.common,
|
||||
&clk_mpll5.common,
|
||||
};
|
||||
|
||||
static int sg2044_pll_init_ctrl(struct device *dev, struct regmap *regmap,
|
||||
struct sg2044_pll_ctrl *ctrl,
|
||||
const struct sg2044_pll_desc_data *desc)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
spin_lock_init(&ctrl->lock);
|
||||
|
||||
for (i = 0; i < desc->num_pll; i++) {
|
||||
struct sg2044_clk_common *common = desc->pll[i];
|
||||
struct sg2044_pll *pll = hw_to_sg2044_pll(&common->hw);
|
||||
|
||||
common->lock = &ctrl->lock;
|
||||
common->regmap = regmap;
|
||||
pll->syscon_offset = SG2044_SYSCON_PLL_OFFSET;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &common->hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ctrl->data.hws[common->id] = &common->hw;
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
||||
&ctrl->data);
|
||||
}
|
||||
|
||||
static int sg2044_pll_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sg2044_pll_ctrl *ctrl;
|
||||
const struct sg2044_pll_desc_data *desc;
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = device_node_to_regmap(pdev->dev.parent->of_node);
|
||||
if (IS_ERR(regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(regmap),
|
||||
"fail to get the regmap for PLL\n");
|
||||
|
||||
desc = (const struct sg2044_pll_desc_data *)platform_get_device_id(pdev)->driver_data;
|
||||
if (!desc)
|
||||
return dev_err_probe(dev, -EINVAL, "no match data for platform\n");
|
||||
|
||||
ctrl = devm_kzalloc(dev, struct_size(ctrl, data.hws, desc->num_pll), GFP_KERNEL);
|
||||
if (!ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
ctrl->data.num = desc->num_pll;
|
||||
|
||||
return sg2044_pll_init_ctrl(dev, regmap, ctrl, desc);
|
||||
}
|
||||
|
||||
static const struct sg2044_pll_desc_data sg2044_pll_desc_data = {
|
||||
.pll = sg2044_pll_commons,
|
||||
.num_pll = ARRAY_SIZE(sg2044_pll_commons),
|
||||
};
|
||||
|
||||
static const struct platform_device_id sg2044_pll_match[] = {
|
||||
{ .name = "sg2044-pll",
|
||||
.driver_data = (unsigned long)&sg2044_pll_desc_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, sg2044_pll_match);
|
||||
|
||||
static struct platform_driver sg2044_clk_driver = {
|
||||
.probe = sg2044_pll_probe,
|
||||
.driver = {
|
||||
.name = "sg2044-pll",
|
||||
},
|
||||
.id_table = sg2044_pll_match,
|
||||
};
|
||||
module_platform_driver(sg2044_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Inochi Amaoto <inochiama@gmail.com>");
|
||||
MODULE_DESCRIPTION("Sophgo SG2044 pll clock driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue
Block a user