From Simon Horman <horms+renesas@verge.net.au>:
Update for Renesas INTC External IRQ pin driver for v3.10
This adds support for shared interrupt lines to the
Renesas INTC External IRQ pin driver which has already
been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10).
* tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
irqchip: intc-irqpin: Add support for shared interrupt lines
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
On some hardware we don't have a 1-1 mapping from the external
interrupts coming from INTC to the GIC SPI pins. We can however
share lines to demux incoming IRQs on these SoCs.
This patch enables the intc_irqpin driver to detect requests for shared
interrupt lines and demuxes them properly by querying the INTC INTREQx0A
registers.
If you need multiple shared intc_irqpin device instances, be sure to mask
out all interrupts on the INTC that share the one line before you start
to register them. Else you run into IRQ floods that would be caused by
interrupts for which no handler has been set up yet when the first
intc_irqpin device is registered.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
From Simon Horman <horms@verge.net.au>:
Renesas ARM and SH based SoC clocksource update for v3.10
I has been agreed by Paul Mundt and myself, that it would be best to take
these changes through the renesas tree and in turn the arm-soc tree.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-clocksource-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clocksource: sh_mtu2: Set initcall level to subsys
clocksource: em_sti: Set initcall level to subsys
clocksource: sh_tmu: Set initcall level to subsys
clocksource: sh_cmt: Set initcall level to subsys
clocksource: sh_cmt: Add CMT register layout comment
clocksource: sh_cmt: Add control register callbacks
clocksource: sh_cmt: CMCNT and CMCOR register access update
clocksource: sh_cmt: CMSTR and CMCSR register access update
clocksource: sh_cmt: Consolidate platform_set_drvdata() call
clocksource: sh_cmt: Introduce per-register functions
clocksource: sh_cmt: Initialize 'max_match_value' and 'lock' in sh_cmt_setup()
clocksource: sh_cmt: Take care of clk_put() when setup_irq() fails
From Simon Horman <horms+renesas@verge.net.au>:
Renesas INTC External IRQ pin driver
This provides two new INTC drivers for use with Renesas ARM-based SoCs and
makes use of them on the r8a7779 and sh73a0 SoCs.
It has been agreed by the relevant parties, Thomas Gleixner, Magnus Damm,
and myself that it would be best to merge this code through the renesas
tree and thus through the arm-soc tree.
This is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-v3.10
* tag 'renesas-intc-external-irq-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
irqchip: irqc: Add DT support
irqchip: intc-irqpin: Initial DT support
ARM: shmobile: Make r8a7779 INTC irqpin platform data static
ARM: shmobile: Make sh73a0 INTC irqpin platform data static
irqchip: Renesas IRQC driver
irqchip: intc-irqpin: GPL header for platform data
irqchip: intc-irqpin: Make use of devm functions
irqchip: intc-irqpin: Add force comments
irqchip: intc-irqpin: Cache mapped IRQ
irqchip: intc-irqpin: Whitespace fixes
ARM: shmobile: INTC External IRQ pin driver on r8a7779
ARM: shmobile: INTC External IRQ pin driver on sh73a0
ARM: shmobile: irq_pin() for static IRQ pin assignment
irqchip: Renesas INTC External IRQ pin driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add initial DT support to the INTC External IRQ Pin
driver. At this point only hardware with 4-bit wide
sense registers is supported via DT.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The platform data for the INTC irq pin driver
seems to be global symbols, make it static to
allow multi-soc build.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The platform data for the INTC irq pin driver
seems to be global symbols, make it static to
allow multi-soc build.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a driver for external IRQ pins connected
to the IRQC hardware block on recent SoCs from Renesas.
The IRQC hardware block is used together with more
recent ARM based SoCs using the GIC. As usual the GIC
requires external IRQ trigger setup somewhere else
which in this particular case happens to be IRQC.
This driver implements the glue code needed to configure
IRQ trigger and also handle mask/unmask and demux of
external IRQ pins hooked up from the IRQC to the GIC.
Tested on r8a73a4 but is designed to work with a wide
range of SoCs. The driver requires one GIC SPI per
external IRQ pin to operate. Each driver instance
will handle up to 32 external IRQ pins.
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt base address. DT support will
be added incrementally in the not so distant future.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Cache IRQ in domain_irq variable instead of
making use of irq_find_mapping(). While at it
rename the irq variable to requested_irq.
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the r8a7779 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ3.
The r8a7779 SoC can like older SH SoCs configure
to use the IRQ0 -> IRQ3 signals as individual
interrupts or a combined IRL mode.
Without this patch the r8a7779 SoC code does
not fully support external IRQ pins in individual
IRQ mode. The r8a7779 PFC code does not yet have
gpio_to_irq() support so no need to update such
code.
At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Adjust the sh73a0 IRQ code to make use of the
INTC External IRQ pin driver for external
interrupt pins IRQ0 -> IRQ31.
This removes quite a bit of special-case code
in intc-sh73a0.c but the number of lines get
replaced with platform device information in
setup-sh73a0.c. The PFC code is also adjusted
to make gpio_to_irq() return the correct
interrupt number.
At this point the DT reference implementations
are not covered. In the future such code shall
tie in the INTC External IRQ pin driver via
DT, so this kind of verbose code is not needed
for the long term DT case.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the macro irq_pin() to let board-specific code using
platform devices tie in external IRQn pins in a common way.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from external IRQ pin handling
to legacy interrupt controller support. On older SoCs
the INTC is used as a general purpose interrupt controller
both for external IRQ pins and on-chip devices.
On more recent ARM based SoCs with Cortex-A9 the main
interrupt controller is the GIC, but IRQ trigger setup
still need to happen in the INTC hardware block.
This driver implements the glue code needed to configure
IRQ trigger and also handle mask/unmask and demux of
external IRQ pins hooked up from the INTC to the GIC.
Tested on sh73a0 and r8a7779. The hardware varies quite
a bit with SoC model, for instance register width and
bitfield widths vary wildly. The driver requires one GIC
SPI per external IRQ pin to operate. Each driver instance
will handle up to 8 external IRQ pins.
The SoCs using this driver are currently mainly used
together with regular platform devices so this driver
allows configuration via platform data to support things
like static interrupt base address. DT support will
be added incrementally in the not so distant future.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
From Nicolas Ferre <nicolas.ferre@atmel.com>:
Some Atmel framebuffer driver enhancements with modification
of configuration data in ARM/AT91 and AVR32/AP7 trees.
A merge of these modifications seems easier through arm-soc
git tree nowadays.
* tag 'at91-driversLCD' of git://github.com/at91linux/linux-at91:
ARM: at91/avr32/atmel_lcdfb: add platform device-id table
atmel_lcdfb: move lcdcon2 register access to compute_hozval
ARM: at91/avr32/atmel_lcdfb: add bus-clock entry
ARM: at91: fix LCD-wiring mode
atmel_lcdfb: fix 16-bpp modes on older SOCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Kukjin Kim <kgene.kim@samsung.com>:
Here is support pinctrl-exynos5250 and that already got ack from Linus Walleij.
* 'next/pinctrl-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled
gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250
pinctrl: exynos: add exynos5250 SoC specific data
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Kukjin Kim <kgene.kim@samsung.com>:
Here is finish the irq rework for s3c2412, s3c2440 and s3c2442 into the new
structure and eint0 to 3 on the s3c2412.
* 'next/irq-s3c24xx' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
gpio: samsung: fixes build warning with s3c2410_defconfig
ARM: S3C24XX: handle s3c2412 eints using new infrastructure
ARM: S3C24XX: add soc_is_s3c2412 option
ARM: S3C24XX: include first 4 bits of the eint register in irq mapping
ARM: S3C24XX: transform s3c2412 irqs into new structure
ARM: S3C24XX: modify s3c2412 irq init to initialize all irqs
ARM: S3C24XX: move s3c2412 irq init to common code
ARM: S3C24XX: use samsung_sync_wakemask in s3c2412 pm
ARM: S3C24XX: transform s3c2440 irqs into new structure
ARM: S3C24XX: transform s3c2442 irqs into new structure
ARM: S3C24XX: integrate s3c2440 irqs into common init
ARM: S3C24XX: move s3c2440 irqs to common irq code
ARM: S3C24XX: create dedicated irq init functions for s3c2440 and s3c2442
ARM: S3C24XX: move s3c244x irq init to common irq code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Kukjin Kim <kgene.kim@samsung.com>:
Here is re-work samsung-time which was s5p-time to support
clocksource/clockevent API for s3c and s5pc100 timer driver. And this enables to
support high resolution timer and tickles mode on them.
Note, this depends on previous pull request (cleanup-s3c) because of touching
while s3c stuff.
* 'next/timer-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Remove unused plat-samsung/time.c
ARM: S5PC100: Add samsung-time support for s5pc100
ARM: S3C64XX: Add samsung-time support for s3c64xx
ARM: S3C24XX: Add samsung-time support for s3c24xx
ARM: SAMSUNG: Rename s5p-time to samsung-time
ARM: S3C24XX: cleanup the included soc init functions in common.h
ARM: S3C24XX: move plat-samsung/s3c24XX headers to local common.h
ARM: S3C24XX: remove plat/irq.h in plat-samsung
ARM: S3C24XX: plat/common-smdk.h local
mmc: s3cmci: moved mach/regs-sdi.h into s3cmci device driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add platform device-id table in order to identify the controller and
determine its configuration.
The currently used configuration parameters are:
have_alt_pixclock
- SOC uses an alternate pixel-clock calculation formula (at91sam9g45
non-ES)
have_hozval
- SOC has a HOZVAL field in LCDFRMCFG which is used to determine the
linesize for STN displays (at91sam9261, at921sam9g10 and at32ap)
have_intensity_bit
- SOC uses IBGR:555 rather than BGR:565 16-bit pixel layout
(at91sam9261, at91sam9263 and at91sam9rl)
This allows us to remove all the remaining uses of cpu_is macros from
the driver.
Tested on at91sam9263 and at91sam9g45, compile-tested for other
AT91-SOCs, and untested for AVR32.
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Pass atmel_lcd_info structure to compute_hozval and only do the register
access on SOCs that actually use it.
This will also simplify the removal of the cpu_is macros.
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add hclk entry for the atmel_lcdfb bus clock.
On at91sam9261, at91sam9g10 and at32ap the bus clock has to be enabled
as well as the peripheral clock. Add the appropriate lookup entries to
these SOCs and fake clocks to the SOCs that do not use it.
This allows us to get rid of the conditional enabling of the clocks in
the driver which relied on the cpu_is macros.
Tested on at91sam9263 and at91sam9g45, compile-tested for other
AT91-SOCs, and untested for AVR32.
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Fix regression introduced by commit 787f9fd232 ("atmel_lcdfb: support
16bit BGR:565 mode, remove unsupported 15bit modes") which broke 16-bpp
modes for older SOCs which use IBGR:555 (msb is intensity) rather than
BGR:565.
The above commit removes the RGB:555-wiring hack by
removing the no longer used ATMEL_LCDC_WIRING_RGB555 define.
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Fix regression introduced by commit 787f9fd232 ("atmel_lcdfb: support
16bit BGR:565 mode, remove unsupported 15bit modes") which broke 16-bpp
modes for older SOCs which use IBGR:555 (msb is intensity) rather
than BGR:565.
Use SOC-type to determine the pixel layout.
Tested on at91sam9263 and at91sam9g45.
Cc: <stable@vger.kernel.org>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The reason for this is to ensure that MTU2 is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using CMT as a clock source kzm9g-reference
which does not make use of early timers or devices. In that scenario
initialisation of SDHI and MMCIF both stall on msleep() calls due to the
absence of a initialised clock source.
The purpose of this change is to keep the MTU2 code in sync with the CMT code
which has been modified in a similar manner..
Compile tested only using se7206_defconfig.
I do not believe I have any boards that support the MTU2.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The reason for this is to ensure that STI is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using CMT as a clock source kzm9g-reference
which does not make use of early timers or devices. In that scenario
initialisation of SDHI and MMCIF both stall on msleep() calls due to the
absence of a initialised clock source.
The purpose of this change is to keep the STI code in sync with the CMT code
which has been modified in a similar manner..
Boot tested on: kzm9d.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The reason for this is to ensure that TMU is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using CMT as a clock source kzm9g-reference
which does not make use of early timers or devices. In that scenario
initialisation of SDHI and MMCIF both stall on msleep() calls due to the
absence of a initialised clock source.
The purpose of this change is to keep the TMU code in sync with the CMT code
which has been modified in a similar manner..
Boot tested on: mackerel.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The reason for this is to ensure that CMT is probed earlier
than with its previous initcall level, module init.
This came up as a problem with using kzm9g-reference which does
not make use of early timers or devices. In that scenario initialisation
of SDHI and MMCIF both stall on msleep() calls due to the absence
of a initialised clock source.
Boot tested on: armadillo800eva, mackerel and kzm9g
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds control register callbacks for the CMT
driver. At this point only 16-bit access is supported
but in the future this will be updated to allow 32-bit
access as well.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: John Stultz <john.stultz@linaro.org>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Break out the CMCNT and CMCOR register access code
into separate 16-bit and 32-bit functions that are
hooked into callbacks at init time. This reduces
the amount of software calculations happening at
runtime.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: John Stultz <john.stultz@linaro.org>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update hardware register access code for CMSTR and CMCSR
from using sh_cmt_read() and sh_cmt_write() to make use
of 16-bit register access functions such as sh_cmt_read16()
and sh_cmt_write16(). Also update sh_cmt_read() and
sh_cmt_write() now when the special cases are gone.
This patch moves us one step closer to the goal of separating
counter register access functions from control control register
functions.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: John Stultz <john.stultz@linaro.org>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Introduce sh_cmt_read_cmstr/cmcsr/cmcnt() and
sh_cmt_write_cmstr/cmcsr/cmcnt/cmcor() to in the
future allow us to split counter registers from
control registers and reduce code complexity by
removing sh_cmt_read() and sh_cmt_write().
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: John Stultz <john.stultz@linaro.org>
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit "ARM: shmobile: r8a7779: use gic_iid macro" switched R8A7779 platform
devices to using gic_iid() macro instead of gic_spi() but commit "ARM: mach-
shmobile: r8a7779: add SATA support" added another use of gic_spi(). Convert
the SATA IRQ resource to using gic_iid().
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
76cc188749
(thermal: rcar: add Device Tree support)
supported rcar_thermal DT probing.
rcar thermal driver doesn't support IRQ on r8a7779 chip
since it is using old design IRQ.
R-Car/R-Mobile next generation chips are using new design IRQ,
and rcar thermal driver is supporting these.
This patch adds rcar_thermal DT support for r8a7779 without IRQ.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
"ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID"
enabled to use gic_iid macro.
This patch exchange current GIC interrupt setting
from gic_spi() to gic_iid()
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[ horms+renesas@verge.net.au: Updated git commit id in changelog ]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
R-Car H1 datasheet GIC number is indicating
GIC ICCIAR / interrupt ID number, not SPI number,
but current marzen board code is using gic_spi() with
un-understandable calculation.
This patch adds new gic_iid() macro which means
ICCIAR / interrupt ID, and used the number
currently written on datasheet.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[ horms+renesas@verge.net.au: Split board-marzen.c portion into a separate patch ]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds temporarily the alternative device names to the clock list
that are used when booting via Device Tree setup.
Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
