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Merge tag 'amlogic-arm-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt

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Amlogic ARM DT changes for v6.15:
- switch to the new PWM controller bindings

* tag 'amlogic-arm-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  ARM: dts: amlogic: meson8b: switch to the new PWM controller binding
  ARM: dts: amlogic: meson8: switch to the new PWM controller binding

Link: https://lore.kernel.org/r/8632a8fa-7af6-4fb7-ba87-297df4f084f5@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-03-20 17:53:00 +01:00
parent 519b8dfd8a dbf9218619
commit b82310b572
5 changed files with 30 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/boot/dts/amlogic/meson8.dtsi
View File

@@ -449,7 +449,11 @@
};
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
compatible = "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
reg = <0x86c0 0x10>;
#pwm-cells = <3>;
status = "disabled";
@@ -699,11 +703,19 @@
};
&pwm_ab {
compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
compatible = "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
&pwm_cd {
compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
compatible = "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
&rtc {

2
arch/arm/boot/dts/amlogic/meson8b-ec100.dts
View File

@@ -443,8 +443,6 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
&rtc {

2
arch/arm/boot/dts/amlogic/meson8b-mxq.dts
View File

@@ -162,8 +162,6 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
&uart_AO {

2
arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
View File

@@ -347,8 +347,6 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
&rtc {

18
arch/arm/boot/dts/amlogic/meson8b.dtsi
View File

@@ -403,8 +403,12 @@
};
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson8b-pwm";
compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
reg = <0x86c0 0x10>;
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
#pwm-cells = <3>;
status = "disabled";
};
@@ -674,11 +678,19 @@
};
&pwm_ab {
compatible = "amlogic,meson8b-pwm";
compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
&pwm_cd {
compatible = "amlogic,meson8b-pwm";
compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
clocks = <&xtal>,
<>, /* unknown/untested, the datasheet calls it "Video PLL" */
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_FCLK_DIV3>;
};
&rtc {